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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/pstate
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headers
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/pstate')
-rw-r--r--include/pstate/pstate.c488
-rw-r--r--include/pstate/pstate.h74
2 files changed, 0 insertions, 562 deletions
diff --git a/include/pstate/pstate.c b/include/pstate/pstate.c
deleted file mode 100644
index c1f696a..0000000
--- a/include/pstate/pstate.c
+++ /dev/null
@@ -1,488 +0,0 @@
1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/bios.h>
26#include <nvgpu/gk20a.h>
27
28#include "clk/clk.h"
29#include "pmu_perf/pmu_perf.h"
30#include "pmgr/pmgr.h"
31#include "pstate/pstate.h"
32#include "therm/thrm.h"
33
34static int pstate_sw_setup(struct gk20a *g);
35
36void gk20a_deinit_pstate_support(struct gk20a *g)
37{
38 if (g->ops.clk.mclk_deinit) {
39 g->ops.clk.mclk_deinit(g);
40 }
41
42 nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex);
43}
44
45/*sw setup for pstate components*/
46int gk20a_init_pstate_support(struct gk20a *g)
47{
48 int err;
49
50 nvgpu_log_fn(g, " ");
51
52 err = volt_rail_sw_setup(g);
53 if (err) {
54 return err;
55 }
56
57 err = volt_dev_sw_setup(g);
58 if (err) {
59 return err;
60 }
61
62 err = volt_policy_sw_setup(g);
63 if (err) {
64 return err;
65 }
66
67 err = clk_vin_sw_setup(g);
68 if (err) {
69 return err;
70 }
71
72 err = clk_fll_sw_setup(g);
73 if (err) {
74 return err;
75 }
76
77 err = therm_domain_sw_setup(g);
78 if (err) {
79 return err;
80 }
81
82 err = vfe_var_sw_setup(g);
83 if (err) {
84 return err;
85 }
86
87 err = vfe_equ_sw_setup(g);
88 if (err) {
89 return err;
90 }
91
92 err = clk_domain_sw_setup(g);
93 if (err) {
94 return err;
95 }
96
97 err = clk_vf_point_sw_setup(g);
98 if (err) {
99 return err;
100 }
101
102 err = clk_prog_sw_setup(g);
103 if (err) {
104 return err;
105 }
106
107 err = pstate_sw_setup(g);
108 if (err) {
109 return err;
110 }
111
112 if(g->ops.clk.support_pmgr_domain) {
113 err = pmgr_domain_sw_setup(g);
114 if (err) {
115 return err;
116 }
117 }
118
119 if (g->ops.clk.support_clk_freq_controller) {
120 err = clk_freq_controller_sw_setup(g);
121 if (err) {
122 return err;
123 }
124 }
125
126 if(g->ops.clk.support_lpwr_pg) {
127 err = nvgpu_lpwr_pg_setup(g);
128 if (err) {
129 return err;
130 }
131 }
132
133 return err;
134}
135
136/*sw setup for pstate components*/
137int gk20a_init_pstate_pmu_support(struct gk20a *g)
138{
139 u32 err;
140
141 nvgpu_log_fn(g, " ");
142
143 if (g->ops.clk.mclk_init) {
144 err = g->ops.clk.mclk_init(g);
145 if (err) {
146 nvgpu_err(g, "failed to set mclk");
147 /* Indicate error and continue */
148 }
149 }
150
151 err = volt_rail_pmu_setup(g);
152 if (err) {
153 return err;
154 }
155
156 err = volt_dev_pmu_setup(g);
157 if (err) {
158 return err;
159 }
160
161 err = volt_policy_pmu_setup(g);
162 if (err) {
163 return err;
164 }
165
166 err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g);
167 if (err) {
168 nvgpu_err(g,
169 "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.",
170 err);
171 return err;
172 }
173
174 err = therm_domain_pmu_setup(g);
175 if (err) {
176 return err;
177 }
178
179 err = vfe_var_pmu_setup(g);
180 if (err) {
181 return err;
182 }
183
184 err = vfe_equ_pmu_setup(g);
185 if (err) {
186 return err;
187 }
188
189 err = clk_domain_pmu_setup(g);
190 if (err) {
191 return err;
192 }
193
194 err = clk_prog_pmu_setup(g);
195 if (err) {
196 return err;
197 }
198
199 err = clk_vin_pmu_setup(g);
200 if (err) {
201 return err;
202 }
203
204 err = clk_fll_pmu_setup(g);
205 if (err) {
206 return err;
207 }
208
209 err = clk_vf_point_pmu_setup(g);
210 if (err) {
211 return err;
212 }
213
214 if (g->ops.clk.support_clk_freq_controller) {
215 err = clk_freq_controller_pmu_setup(g);
216 if (err) {
217 return err;
218 }
219 }
220 err = clk_pmu_vin_load(g);
221 if (err) {
222 return err;
223 }
224
225 err = g->ops.clk.perf_pmu_vfe_load(g);
226 if (err) {
227 return err;
228 }
229
230 if (g->ops.clk.support_pmgr_domain) {