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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/os/linux/platform_gk20a.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/os/linux/platform_gk20a.h')
-rw-r--r--include/os/linux/platform_gk20a.h329
1 files changed, 0 insertions, 329 deletions
diff --git a/include/os/linux/platform_gk20a.h b/include/os/linux/platform_gk20a.h
deleted file mode 100644
index adec860..0000000
--- a/include/os/linux/platform_gk20a.h
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * GK20A Platform (SoC) Interface
3 *
4 * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GK20A_PLATFORM_H_
17#define _GK20A_PLATFORM_H_
18
19#include <linux/device.h>
20
21#include <nvgpu/lock.h>
22#include <nvgpu/gk20a.h>
23
24#define GK20A_CLKS_MAX 4
25
26struct gk20a;
27struct channel_gk20a;
28struct gr_ctx_buffer_desc;
29struct gk20a_scale_profile;
30
31struct secure_page_buffer {
32 void (*destroy)(struct gk20a *, struct secure_page_buffer *);
33 size_t size;
34 dma_addr_t phys;
35 size_t used;
36};
37
38struct gk20a_platform {
39 /* Populated by the gk20a driver before probing the platform. */
40 struct gk20a *g;
41
42 /* Should be populated at probe. */
43 bool can_railgate_init;
44
45 /* Should be populated at probe. */
46 bool can_tpc_powergate;
47
48 /* Should be populated at probe. */
49 bool can_elpg_init;
50
51 /* Should be populated at probe. */
52 bool has_syncpoints;
53
54 /* channel limit after which to start aggressive sync destroy */
55 unsigned int aggressive_sync_destroy_thresh;
56
57 /* flag to set sync destroy aggressiveness */
58 bool aggressive_sync_destroy;
59
60 /* set if ASPM should be disabled on boot; only makes sense for PCI */
61 bool disable_aspm;
62
63 /* Set if the platform can unify the small/large address spaces. */
64 bool unify_address_spaces;
65
66 /* Clock configuration is stored here. Platform probe is responsible
67 * for filling this data. */
68 struct clk *clk[GK20A_CLKS_MAX];
69 int num_clks;
70 int maxmin_clk_id;
71
72#ifdef CONFIG_RESET_CONTROLLER
73 /* Reset control for device */
74 struct reset_control *reset_control;
75#endif
76 /* valid TPC-MASK */
77 u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
78
79 /* Delay before rail gated */
80 int railgate_delay_init;
81
82 /* init value for slowdown factor */
83 u8 ldiv_slowdown_factor_init;
84
85 /* Second Level Clock Gating: true = enable false = disable */
86 bool enable_slcg;
87
88 /* Block Level Clock Gating: true = enable flase = disable */
89 bool enable_blcg;
90
91 /* Engine Level Clock Gating: true = enable flase = disable */
92 bool enable_elcg;
93
94 /* Should be populated at probe. */
95 bool can_slcg;
96
97 /* Should be populated at probe. */
98 bool can_blcg;
99
100 /* Should be populated at probe. */
101 bool can_elcg;
102
103 /* Engine Level Power Gating: true = enable flase = disable */
104 bool enable_elpg;
105
106 /* Adaptative ELPG: true = enable flase = disable */
107 bool enable_aelpg;
108
109 /* PMU Perfmon: true = enable false = disable */
110 bool enable_perfmon;
111
112 /* Memory System Clock Gating: true = enable flase = disable*/
113 bool enable_mscg;
114
115 /* Timeout for per-channel watchdog (in mS) */
116 u32 ch_wdt_timeout_ms;
117
118 /* Disable big page support */
119 bool disable_bigpage;
120
121 /*
122 * gk20a_do_idle() API can take GPU either into rail gate or CAR reset
123 * This flag can be used to force CAR reset case instead of rail gate
124 */
125 bool force_reset_in_do_idle;
126
127 /* guest/vm id, needed for IPA to PA transation */
128 int vmid;
129
130 /* Initialize the platform interface of the gk20a driver.
131 *
132 * The platform implementation of this function must
133 * - set the power and clocks of the gk20a device to a known
134 * state, and
135 * - populate the gk20a_platform structure (a pointer to the
136 * structure can be obtained by calling gk20a_get_platform).
137 *
138 * After this function is finished, the driver will initialise
139 * pm runtime and genpd based on the platform configuration.
140 */
141 int (*probe)(struct device *dev);
142
143 /* Second stage initialisation - called once all power management
144 * initialisations are done.
145 */
146 int (*late_probe)(struct device *dev);
147
148 /* Remove device after power management has been done
149 */
150 int (*remove)(struct device *dev);
151
152 /* Poweron platform dependencies */
153 int (*busy)(struct device *dev);
154
155 /* Powerdown platform dependencies */
156 void (*idle)(struct device *dev);
157
158 /* Preallocated VPR buffer for kernel */
159 size_t secure_buffer_size;
160 struct secure_page_buffer secure_buffer;
161
162 /* Device is going to be suspended */
163 int (*suspend)(struct device *);
164
165 /* Device is going to be resumed */
166 int (*resume)(struct device *);
167
168 /* Called to turn off the device */
169 int (*railgate)(struct device *dev);
170
171 /* Called to turn on the device */
172 int (*unrailgate)(struct device *dev);
173 struct nvgpu_mutex railgate_lock;
174
175 /* Called to check state of device */
176 bool (*is_railgated)(struct device *dev);
177
178 /* get supported frequency list */
179 int (*get_clk_freqs)(struct device *pdev,
180 unsigned long **freqs, int *num_freqs);
181
182 /* clk related supported functions */
183 long (*clk_round_rate)(struct device *dev,
184 unsigned long rate);
185
186 /* Called to register GPCPLL with common clk framework */
187 int (*clk_register)(struct gk20a *g);
188
189 /* platform specific scale init quirks */
190 void (*initscale)(struct device *dev);
191
192 /* Postscale callback is called after frequency change */
193 void (*postscale)(struct device *dev,
194 unsigned long freq);
195
196 /* Pre callback is called before frequency change */
197 void (*prescale)(struct device *dev);
198
199 /* Set TPC_PG_MASK during probe */
200 void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_pg_mask);
201
202 /* Devfreq governor name. If scaling is enabled, we request
203 * this governor to be used in scaling */
204 const char *devfreq_governor;
205
206 /* Quality of service notifier callback. If this is set, the scaling
207 * routines will register a callback to Qos. Each time we receive
208 * a new value, this callback gets called. */
209 int (*qos_notify)(struct notifier_block *nb,
210 unsigned long n, void *p);
211
212 /* Called as part of debug dump. If the gpu gets hung, this function
213 * is responsible for delivering all necessary debug data of other
214 * hw units which may interact with the gpu without direct supervision
215 * of the CPU.
216 */
217 void (*dump_platform_dependencies)(struct device *dev);
218
219 /* Defined when SMMU stage-2 is enabled, and we need to use physical
220 * addresses (not IPA). This is the case for GV100 nvlink in HV+L
221 * configuration, when dGPU is in pass-through mode.
222 */
223 u64 (*phys_addr)(struct gk20a *g, u64 ipa);
224
225 /* Callbacks to assert/deassert GPU reset */
226 int (*reset_assert)(struct device *dev);
227 int (*reset_deassert)(struct device *dev);
228 struct clk *clk_reset;
229 struct dvfs_rail *gpu_rail;
230
231 bool virtual_dev;
232#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
233 void *vgpu_priv;
234#endif
235 /* source frequency for ptimer in hz */
236 u32 ptimer_src_freq;
237
238#ifdef CONFIG_NVGPU_SUPPORT_CDE
239 bool has_cde;
240#endif
241
242 /* soc name for finding firmware files */
243 const char *soc_name;
244
245 /* false if vidmem aperture actually points to sysmem */
246 bool honors_aperture;
247 /* unified or split memory with separate vidmem? */
248 bool unified_memory;
249 /* WAR for gm20b chips. */
250 bool force_128K_pmu_vm;
251
252 /*
253 * DMA mask for Linux (both coh and non-coh). If not set defaults to
254 * 0x3ffffffff (i.e a 34 bit mask).
255 */
256 u64 dma_mask;
257
258 /* minimum supported VBIOS version */
259 u32 vbios_min_version;
260
261 /* true if we run preos microcode on this board */
262 bool run_preos;
263
264 /* true if we need to program sw threshold for
265 * power limits
266 */
267 bool hardcode_sw_threshold;
268
269 /* i2c device index, port and address for INA3221 */
270 u32 ina3221_dcb_index;
271 u32 ina3221_i2c_address;
272 u32 ina3221_i2c_port;
273
274 /* stream id to use */
275 u32 ltc_streamid;
276
277 /* synchronized access to platform->clk_get_freqs */
278 struct nvgpu_mutex clk_get_freq_lock;
279};
280
281static inline struct gk20a_platform *gk20a_get_platform(
282 struct device *dev)
283{
284 return (struct gk20a_platform *)dev_get_drvdata(dev);
285}
286
287#ifdef CONFIG_TEGRA_GK20A
288extern struct gk20a_platform gm20b_tegra_platform;
289extern struct gk20a_platform gp10b_tegra_platform;
290extern struct gk20a_platform gv11b_tegra_platform;
291#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
292extern struct gk20a_platform vgpu_tegra_platform;
293extern struct gk20a_platform gv11b_vgpu_tegra_platform;
294#endif
295#endif
296
297int gk20a_tegra_busy(struct device *dev);
298void gk20a_tegra_idle(struct device *dev);
299void gk20a_tegra_debug_dump(struct device *pdev);
300
301static inline struct gk20a *get_gk20a(struct device *dev)
302{
303 return gk20a_get_platform(dev)->g;
304}
305static inline struct gk20a *gk20a_from_dev(struct device *dev)
306{
307 if (!dev)
308 return NULL;
309
310 return ((struct gk20a_platform *)dev_get_drvdata(dev))->g;
311}
312static inline bool gk20a_gpu_is_virtual(struct device *dev)
313{
314 struct gk20a_platform *platform = dev_get_drvdata(dev);
315
316 return platform->virtual_dev;
317}
318
319static inline int support_gk20a_pmu(struct device *dev)
320{
321 if (IS_ENABLED(CONFIG_GK20A_PMU)) {
322 /* gPMU is not supported for vgpu */
323 return !gk20a_gpu_is_virtual(dev);
324 }
325
326 return 0;
327}
328
329#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 16:24:31 -0400