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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/os/linux/fuse.c
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/os/linux/fuse.c')
-rw-r--r--include/os/linux/fuse.c55
1 files changed, 0 insertions, 55 deletions
diff --git a/include/os/linux/fuse.c b/include/os/linux/fuse.c
deleted file mode 100644
index 27851f9..0000000
--- a/include/os/linux/fuse.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <soc/tegra/fuse.h>
15
16#include <nvgpu/fuse.h>
17
18int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
19{
20 return tegra_sku_info.gpu_speedo_id;
21}
22
23/*
24 * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
25 * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
26 */
27void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
28{
29 tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
30}
31
32void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
33{
34 tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
35}
36
37void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
38{
39 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
40}
41
42void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
43{
44 tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
45}
46
47int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
48{
49 return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
50}
51
52int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
53{
54 return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
55}