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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/tsg.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/tsg.h')
-rw-r--r--include/nvgpu/tsg.h132
1 files changed, 0 insertions, 132 deletions
diff --git a/include/nvgpu/tsg.h b/include/nvgpu/tsg.h
deleted file mode 100644
index f5391e7..0000000
--- a/include/nvgpu/tsg.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef TSG_GK20A_H
23#define TSG_GK20A_H
24
25#include <nvgpu/lock.h>
26#include <nvgpu/kref.h>
27#include <nvgpu/rwsem.h>
28
29#include "gk20a/gr_gk20a.h"
30
31#define NVGPU_INVALID_TSG_ID (U32_MAX)
32
33struct channel_gk20a;
34
35struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid);
36void gk20a_tsg_release(struct nvgpu_ref *ref);
37
38int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);
39struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch);
40
41struct nvgpu_tsg_sm_error_state {
42 u32 hww_global_esr;
43 u32 hww_warp_esr;
44 u64 hww_warp_esr_pc;
45 u32 hww_global_esr_report_mask;
46 u32 hww_warp_esr_report_mask;
47};
48
49struct tsg_gk20a {
50 struct gk20a *g;
51
52 struct vm_gk20a *vm;
53 struct nvgpu_mem *eng_method_buffers;
54
55
56 struct nvgpu_gr_ctx gr_ctx;
57 struct nvgpu_ref refcount;
58
59 struct nvgpu_list_node ch_list;
60 struct nvgpu_list_node event_id_list;
61 struct nvgpu_rwsem ch_list_lock;
62 struct nvgpu_mutex event_id_list_lock;
63 int num_active_channels;
64
65 unsigned int timeslice_us;
66 unsigned int timeslice_timeout;
67 unsigned int timeslice_scale;
68
69 u32 interleave_level;
70 u32 tsgid;
71
72 u32 runlist_id;
73 pid_t tgid;
74 u32 num_active_tpcs;
75 u8 tpc_pg_enabled;
76 bool tpc_num_initialized;
77 bool in_use;
78
79 /* MMU debug mode enabled if mmu_debug_mode_refcnt > 0 */
80 u32 mmu_debug_mode_refcnt;
81
82 struct nvgpu_tsg_sm_error_state *sm_error_states;
83
84#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U)
85#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0)
86 u32 sm_exception_mask_type;
87};
88
89int gk20a_enable_tsg(struct tsg_gk20a *tsg);
90int gk20a_disable_tsg(struct tsg_gk20a *tsg);
91int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
92 struct channel_gk20a *ch);
93int gk20a_tsg_unbind_channel(struct channel_gk20a *ch, bool force);
94
95void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
96 int event_id);
97int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level);
98int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
99u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg);
100int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
101 u32 priority);
102int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g,
103 struct tsg_gk20a *tsg,
104 u32 num_sm);
105void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg,
106 u32 sm_id,
107 struct nvgpu_tsg_sm_error_state *sm_error_state);
108
109struct gk20a_event_id_data {
110 struct gk20a *g;
111
112 int id; /* ch or tsg */
113 int pid;
114 u32 event_id;
115
116 bool event_posted;
117
118 struct nvgpu_cond event_id_wq;
119 struct nvgpu_mutex lock;
120 struct nvgpu_list_node event_id_node;
121};
122
123static inline struct gk20a_event_id_data *
124gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node)
125{
126 return (struct gk20a_event_id_data *)
127 ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node));
128};
129
130int nvgpu_tsg_set_mmu_debug_mode(struct channel_gk20a *ch, bool enable);
131
132#endif /* TSG_GK20A_H */