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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/sec2if/sec2_if_cmn.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/sec2if/sec2_if_cmn.h')
-rw-r--r--include/nvgpu/sec2if/sec2_if_cmn.h73
1 files changed, 0 insertions, 73 deletions
diff --git a/include/nvgpu/sec2if/sec2_if_cmn.h b/include/nvgpu/sec2if/sec2_if_cmn.h
deleted file mode 100644
index a40f8f9..0000000
--- a/include/nvgpu/sec2if/sec2_if_cmn.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_IF_CMN_H
24#define NVGPU_SEC2_IF_CMN_H
25
26/*
27 * Define the maximum number of command sequences that can be in flight at
28 * any given time. This is dictated by the width of the sequence number
29 * id ('seqNumId') stored in each sequence packet (currently 8-bits).
30 */
31#define NV_SEC2_MAX_NUM_SEQUENCES 256U
32
33/*
34 * Compares an unit id against the values in the unit_id enumeration and
35 * verifies that the id is valid. It is expected that the id is specified
36 * as an unsigned integer.
37 */
38#define NV_SEC2_UNITID_IS_VALID(id) (((id) < NV_SEC2_UNIT_END))
39
40/*
41 * Defines the size of the surface/buffer that will be allocated to store
42 * debug spew from the SEC2 ucode application when falcon-trace is enabled.
43 */
44#define NV_SEC2_DEBUG_SURFACE_SIZE (32U*1024U)
45
46/*
47 * SEC2's frame-buffer interface block has several slots/indices which can
48 * be bound to support DMA to various surfaces in memory. This is an
49 * enumeration that gives name to each index based on type of memory-aperture
50 * the index is used to access.
51 *
52 * Pre-Turing, NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND.
53 * From Turing, engine context is stored in GPA, requiring a separate aperture.
54 *
55 * Traditionally, video falcons have used the 6th index for ucode, and we will
56 * continue to use that to allow legacy ucode to work seamlessly.
57 *
58 * Note: DO NOT CHANGE THE VALUE OF NV_SEC2_DMAIDX_UCODE. That value is used by
59 * both the legacy SEC2 ucode, which assumes that it will use index 6, and by
60 * SEC2 RTOS. Changing it will break legacy SEC2 ucode, unless it is updated to
61 * reflect the new value.
62 */
63
64#define NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND 0U
65#define NV_SEC2_DMAIDX_VIRT 1U
66#define NV_SEC2_DMAIDX_PHYS_VID_FN0 2U
67#define NV_SEC2_DMAIDX_PHYS_SYS_COH_FN0 3U
68#define NV_SEC2_DMAIDX_PHYS_SYS_NCOH_FN0 4U
69#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_COH_BOUND 5U
70#define NV_SEC2_DMAIDX_UCODE 6U
71#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND 7U
72
73#endif /* NVGPU_SEC2_IF_CMN_H */