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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/sec2.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/sec2.h')
-rw-r--r--include/nvgpu/sec2.h97
1 files changed, 0 insertions, 97 deletions
diff --git a/include/nvgpu/sec2.h b/include/nvgpu/sec2.h
deleted file mode 100644
index 7c75584..0000000
--- a/include/nvgpu/sec2.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_H
24#define NVGPU_SEC2_H
25
26#include <nvgpu/kmem.h>
27#include <nvgpu/dma.h>
28#include <nvgpu/nvgpu_mem.h>
29#include <nvgpu/allocator.h>
30#include <nvgpu/lock.h>
31#include <nvgpu/flcnif_cmn.h>
32#include <nvgpu/falcon.h>
33
34#include <nvgpu/sec2if/sec2_cmd_if.h>
35#include <nvgpu/sec2if/sec2_if_sec2.h>
36
37#define NVGPU_SEC2_TRACE_BUFSIZE (32U*1024U)
38
39#define SEC2_MAX_NUM_SEQUENCES (256U)
40#define SEC2_SEQ_BIT_SHIFT (5U)
41#define SEC2_SEQ_TBL_SIZE \
42 (SEC2_MAX_NUM_SEQUENCES >> SEC2_SEQ_BIT_SHIFT)
43
44#define SEC2_INVALID_SEQ_DESC (~0U)
45
46enum {
47 SEC2_SEQ_STATE_FREE = 0U,
48 SEC2_SEQ_STATE_PENDING,
49 SEC2_SEQ_STATE_USED,
50 SEC2_SEQ_STATE_CANCELLED
51};
52
53typedef void (*sec2_callback)(struct gk20a *, struct nv_flcn_msg_sec2 *,
54 void *, u32, u32);
55
56struct sec2_sequence {
57 u8 id;
58 u32 state;
59 u32 desc;
60 struct nv_flcn_msg_sec2 *msg;
61 u8 *out_payload;
62 sec2_callback callback;
63 void *cb_params;
64};
65
66struct nvgpu_sec2 {
67 struct gk20a *g;
68 struct nvgpu_falcon *flcn;
69 u32 falcon_id;
70
71 struct nvgpu_falcon_queue queue[SEC2_QUEUE_NUM];
72
73 struct sec2_sequence *seq;
74 unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE];
75 u32 next_seq_desc;
76 struct nvgpu_mutex sec2_seq_lock;
77
78 bool isr_enabled;
79 struct nvgpu_mutex isr_mutex;
80
81 struct nvgpu_allocator dmem;
82
83 /* set to true once init received */
84 bool sec2_ready;
85
86 struct nvgpu_mem trace_buf;
87
88 void (*remove_support)(struct nvgpu_sec2 *sec2);
89
90 u32 command_ack;
91};
92
93/* sec2 init */
94int nvgpu_init_sec2_support(struct gk20a *g);
95int nvgpu_sec2_destroy(struct gk20a *g);
96
97#endif /* NVGPU_SEC2_H */