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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/hw/gv100/hw_ram_gv100.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/hw/gv100/hw_ram_gv100.h')
-rw-r--r--include/nvgpu/hw/gv100/hw_ram_gv100.h791
1 files changed, 0 insertions, 791 deletions
diff --git a/include/nvgpu/hw/gv100/hw_ram_gv100.h b/include/nvgpu/hw/gv100/hw_ram_gv100.h
deleted file mode 100644
index 55aa25f..0000000
--- a/include/nvgpu/hw/gv100/hw_ram_gv100.h
+++ /dev/null
@@ -1,791 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ram_gv100_h_
57#define _hw_ram_gv100_h_
58
59static inline u32 ram_in_ramfc_s(void)
60{
61 return 4096U;
62}
63static inline u32 ram_in_ramfc_w(void)
64{
65 return 0U;
66}
67static inline u32 ram_in_page_dir_base_target_f(u32 v)
68{
69 return (v & 0x3U) << 0U;
70}
71static inline u32 ram_in_page_dir_base_target_w(void)
72{
73 return 128U;
74}
75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
76{
77 return 0x0U;
78}
79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
80{
81 return 0x2U;
82}
83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
84{
85 return 0x3U;
86}
87static inline u32 ram_in_page_dir_base_vol_w(void)
88{
89 return 128U;
90}
91static inline u32 ram_in_page_dir_base_vol_true_f(void)
92{
93 return 0x4U;
94}
95static inline u32 ram_in_page_dir_base_vol_false_f(void)
96{
97 return 0x0U;
98}
99static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
100{
101 return (v & 0x1U) << 4U;
102}
103static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
104{
105 return 0x1U << 4U;
106}
107static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
108{
109 return 128U;
110}
111static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
112{
113 return 0x10U;
114}
115static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
116{
117 return (v & 0x1U) << 5U;
118}
119static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
120{
121 return 0x1U << 5U;
122}
123static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
124{
125 return 128U;
126}
127static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
128{
129 return 0x20U;
130}
131static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
132{
133 return (v & 0x1U) << 10U;
134}
135static inline u32 ram_in_use_ver2_pt_format_m(void)
136{
137 return 0x1U << 10U;
138}
139static inline u32 ram_in_use_ver2_pt_format_w(void)
140{
141 return 128U;
142}
143static inline u32 ram_in_use_ver2_pt_format_true_f(void)
144{
145 return 0x400U;
146}
147static inline u32 ram_in_use_ver2_pt_format_false_f(void)
148{
149 return 0x0U;
150}
151static inline u32 ram_in_big_page_size_f(u32 v)
152{
153 return (v & 0x1U) << 11U;
154}
155static inline u32 ram_in_big_page_size_m(void)
156{
157 return 0x1U << 11U;
158}
159static inline u32 ram_in_big_page_size_w(void)
160{
161 return 128U;
162}
163static inline u32 ram_in_big_page_size_128kb_f(void)
164{
165 return 0x0U;
166}
167static inline u32 ram_in_big_page_size_64kb_f(void)
168{
169 return 0x800U;
170}
171static inline u32 ram_in_page_dir_base_lo_f(u32 v)
172{
173 return (v & 0xfffffU) << 12U;
174}
175static inline u32 ram_in_page_dir_base_lo_w(void)
176{
177 return 128U;
178}
179static inline u32 ram_in_page_dir_base_hi_f(u32 v)
180{
181 return (v & 0xffffffffU) << 0U;
182}
183static inline u32 ram_in_page_dir_base_hi_w(void)
184{
185 return 129U;
186}
187static inline u32 ram_in_engine_cs_w(void)
188{
189 return 132U;
190}
191static inline u32 ram_in_engine_cs_wfi_v(void)
192{
193 return 0x00000000U;
194}
195static inline u32 ram_in_engine_cs_wfi_f(void)
196{
197 return 0x0U;
198}
199static inline u32 ram_in_engine_cs_fg_v(void)
200{
201 return 0x00000001U;
202}
203static inline u32 ram_in_engine_cs_fg_f(void)
204{
205 return 0x8U;
206}
207static inline u32 ram_in_engine_wfi_mode_f(u32 v)
208{
209 return (v & 0x1U) << 2U;
210}
211static inline u32 ram_in_engine_wfi_mode_w(void)
212{
213 return 132U;
214}
215static inline u32 ram_in_engine_wfi_mode_physical_v(void)
216{
217 return 0x00000000U;
218}
219static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
220{
221 return 0x00000001U;
222}
223static inline u32 ram_in_engine_wfi_target_f(u32 v)
224{
225 return (v & 0x3U) << 0U;
226}
227static inline u32 ram_in_engine_wfi_target_w(void)
228{
229 return 132U;
230}
231static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
232{
233 return 0x00000002U;
234}
235static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void)
236{
237 return 0x00000003U;
238}
239static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
240{
241 return 0x00000000U;
242}
243static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
244{
245 return (v & 0xfffffU) << 12U;
246}
247static inline u32 ram_in_engine_wfi_ptr_lo_w(void)
248{
249 return 132U;
250}
251static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v)
252{
253 return (v & 0xffU) << 0U;
254}
255static inline u32 ram_in_engine_wfi_ptr_hi_w(void)
256{
257 return 133U;
258}
259static inline u32 ram_in_engine_wfi_veid_f(u32 v)
260{
261 return (v & 0x3fU) << 0U;
262}
263static inline u32 ram_in_engine_wfi_veid_w(void)
264{
265 return 134U;
266}
267static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v)
268{
269 return (v & 0xffffffffU) << 0U;
270}
271static inline u32 ram_in_eng_method_buffer_addr_lo_w(void)
272{
273 return 136U;
274}
275static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v)
276{
277 return (v & 0x1ffffU) << 0U;
278}
279static inline u32 ram_in_eng_method_buffer_addr_hi_w(void)
280{
281 return 137U;
282}
283static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i)
284{
285 return (v & 0x3U) << (0U + i*0U);
286}
287static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void)
288{
289 return 0x00000040U;
290}
291static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void)
292{
293 return 0x00000000U;
294}
295static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void)
296{
297 return 0x00000001U;
298}
299static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void)
300{
301 return 0x00000002U;
302}
303static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void)
304{
305 return 0x00000003U;
306}
307static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i)
308{
309 return (v & 0x1U) << (2U + i*0U);
310}
311static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void)
312{
313 return 0x00000040U;
314}
315static inline u32 ram_in_sc_page_dir_base_vol_true_v(void)
316{
317 return 0x00000001U;
318}
319static inline u32 ram_in_sc_page_dir_base_vol_false_v(void)
320{
321 return 0x00000000U;
322}
323static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i)
324{
325 return (v & 0x1U) << (4U + i*0U);
326}
327static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void)
328{
329 return 0x00000040U;
330}
331static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void)
332{
333 return 0x00000001U;
334}
335static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void)
336{
337 return 0x00000000U;
338}
339static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i)
340{
341 return (v & 0x1U) << (5U + i*0U);
342}
343static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void)
344{
345 return 0x00000040U;
346}
347static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void)
348{
349 return 0x00000001U;
350}
351static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void)
352{
353 return 0x00000000U;
354}
355static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i)
356{
357 return (v & 0x1U) << (10U + i*0U);
358}
359static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void)
360{
361 return 0x00000040U;
362}
363static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void)
364{
365 return 0x00000000U;
366}
367static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void)
368{
369 return 0x00000001U;
370}
371static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i)
372{
373 return (v & 0x1U) << (11U + i*0U);
374}
375static inline u32 ram_in_sc_big_page_size__size_1_v(void)
376{
377 return 0x00000040U;
378}
379static inline u32 ram_in_sc_big_page_size_64kb_v(void)
380{
381 return 0x00000001U;
382}
383static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i)
384{
385 return (v & 0xfffffU) << (12U + i*0U);
386}
387static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void)
388{
389 return 0x00000040U;
390}
391static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i)
392{
393 return (v & 0xffffffffU) << (0U + i*0U);
394}
395static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void)
396{
397 return 0x00000040U;
398}
399static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v)
400{
401 return (v & 0x3U) << 0U;
402}
403static inline u32 ram_in_sc_page_dir_base_target_0_w(void)
404{
405 return 168U;
406}
407static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v)
408{
409 return (v & 0x1U) << 2U;
410}
411static inline u32 ram_in_sc_page_dir_base_vol_0_w(void)
412{
413 return 168U;
414}
415static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v)
416{
417 return (v & 0x1U) << 4U;
418}
419static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void)
420{
421 return 168U;
422}
423static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v)
424{
425 return (v & 0x1U) << 5U;
426}
427static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void)
428{
429 return 168U;
430}
431static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v)
432{
433 return (v & 0x1U) << 10U;
434}
435static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void)
436{
437 return 168U;
438}
439static inline u32 ram_in_sc_big_page_size_0_f(u32 v)
440{
441 return (v & 0x1U) << 11U;
442}
443static inline u32 ram_in_sc_big_page_size_0_w(void)
444{
445 return 168U;
446}
447static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v)
448{
449 return (v & 0xfffffU) << 12U;
450}
451static inline u32 ram_in_sc_page_dir_base_lo_0_w(void)
452{
453 return 168U;
454}
455static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v)
456{
457 return (v & 0xffffffffU) << 0U;
458}
459static inline u32 ram_in_sc_page_dir_base_hi_0_w(void)
460{
461 return 169U;
462}
463static inline u32 ram_in_base_shift_v(void)
464{
465 return 0x0000000cU;
466}
467static inline u32 ram_in_alloc_size_v(void)
468{
469 return 0x00001000U;
470}
471static inline u32 ram_fc_size_val_v(void)
472{
473 return 0x00000200U;
474}
475static inline u32 ram_fc_gp_put_w(void)
476{
477 return 0U;
478}
479static inline u32 ram_fc_userd_w(void)
480{
481 return 2U;
482}
483static inline u32 ram_fc_userd_hi_w(void)
484{
485 return 3U;
486}
487static inline u32 ram_fc_signature_w(void)
488{
489 return 4U;
490}
491static inline u32 ram_fc_gp_get_w(void)
492{
493 return 5U;
494}
495static inline u32 ram_fc_pb_get_w(void)
496{
497 return 6U;
498}
499static inline u32 ram_fc_pb_get_hi_w(void)
500{
501 return 7U;
502}
503static inline u32 ram_fc_pb_top_level_get_w(void)
504{
505 return 8U;
506}
507static inline u32 ram_fc_pb_top_level_get_hi_w(void)
508{
509 return 9U;
510}
511static inline u32 ram_fc_acquire_w(void)
512{
513 return 12U;
514}
515static inline u32 ram_fc_sem_addr_hi_w(void)
516{
517 return 14U;
518}
519static inline u32 ram_fc_sem_addr_lo_w(void)
520{
521 return 15U;
522}
523static inline u32 ram_fc_sem_payload_lo_w(void)
524{
525 return 16U;
526}
527static inline u32 ram_fc_sem_payload_hi_w(void)
528{
529 return 39U;
530}
531static inline u32 ram_fc_sem_execute_w(void)
532{
533 return 17U;
534}
535static inline u32 ram_fc_gp_base_w(void)
536{
537 return 18U;
538}
539static inline u32 ram_fc_gp_base_hi_w(void)
540{
541 return 19U;
542}
543static inline u32 ram_fc_gp_fetch_w(void)
544{
545 return 20U;
546}
547static inline u32 ram_fc_pb_fetch_w(void)
548{
549 return 21U;
550}
551static inline u32 ram_fc_pb_fetch_hi_w(void)
552{
553 return 22U;
554}
555static inline u32 ram_fc_pb_put_w(void)
556{
557 return 23U;
558}
559static inline u32 ram_fc_pb_put_hi_w(void)
560{
561 return 24U;
562}
563static inline u32 ram_fc_pb_header_w(void)
564{
565 return 33U;
566}
567static inline u32 ram_fc_pb_count_w(void)
568{
569 return 34U;
570}
571static inline u32 ram_fc_subdevice_w(void)
572{
573 return 37U;
574}
575static inline u32 ram_fc_target_w(void)
576{
577 return 43U;
578}
579static inline u32 ram_fc_hce_ctrl_w(void)
580{
581 return 57U;
582}
583static inline u32 ram_fc_chid_w(void)
584{
585 return 58U;
586}
587static inline u32 ram_fc_chid_id_f(u32 v)
588{
589 return (v & 0xfffU) << 0U;
590}
591static inline u32 ram_fc_chid_id_w(void)
592{
593 return 0U;
594}
595static inline u32 ram_fc_config_w(void)
596{
597 return 61U;
598}
599static inline u32 ram_fc_runlist_timeslice_w(void)
600{
601 return 62U;
602}
603static inline u32 ram_fc_set_channel_info_w(void)
604{
605 return 63U;
606}
607static inline u32 ram_userd_base_shift_v(void)
608{
609 return 0x00000009U;
610}
611static inline u32 ram_userd_chan_size_v(void)
612{
613 return 0x00000200U;
614}
615static inline u32 ram_userd_put_w(void)
616{
617 return 16U;
618}
619static inline u32 ram_userd_get_w(void)
620{
621 return 17U;
622}
623static inline u32 ram_userd_ref_w(void)
624{
625 return 18U;
626}
627static inline u32 ram_userd_put_hi_w(void)
628{
629 return 19U;
630}
631static inline u32 ram_userd_ref_threshold_w(void)
632{
633 return 20U;
634}
635static inline u32 ram_userd_top_level_get_w(void)
636{
637 return 22U;
638}
639static inline u32 ram_userd_top_level_get_hi_w(void)
640{
641 return 23U;
642}
643static inline u32 ram_userd_get_hi_w(void)
644{
645 return 24U;
646}
647static inline u32 ram_userd_gp_get_w(void)
648{
649 return 34U;
650}
651static inline u32 ram_userd_gp_put_w(void)
652{
653 return 35U;
654}
655static inline u32 ram_userd_gp_top_level_get_w(void)
656{
657 return 22U;
658}
659static inline u32 ram_userd_gp_top_level_get_hi_w(void)
660{
661 return 23U;
662}
663static inline u32 ram_rl_entry_size_v(void)
664{
665 return 0x00000010U;
666}
667static inline u32 ram_rl_entry_type_f(u32 v)
668{
669 return (v & 0x1U) << 0U;
670}
671static inline u32 ram_rl_entry_type_channel_v(void)
672{
673 return 0x00000000U;
674}
675static inline u32 ram_rl_entry_type_tsg_v(void)
676{
677 return 0x00000001U;
678}
679static inline u32 ram_rl_entry_id_f(u32 v)
680{
681 return (v & 0xfffU) << 0U;
682}
683static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
684{
685 return (v & 0x1U) << 1U;
686}
687static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
688{
689 return (v & 0x3U) << 4U;
690}
691static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void)
692{
693 return 0x00000003U;
694}
695static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void)
696{
697 return 0x00000002U;
698}
699static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void)
700{
701 return 0x00000000U;
702}
703static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
704{
705 return (v & 0x3U) << 6U;
706}
707static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void)
708{
709 return 0x00000000U;
710}
711static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void)
712{
713 return 0x00000001U;
714}
715static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void)
716{
717 return 0x00000002U;
718}
719static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void)
720{
721 return 0x00000003U;
722}
723static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
724{
725 return (v & 0xffffffU) << 8U;
726}
727static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
728{
729 return (v & 0xffffffffU) << 0U;
730}
731static inline u32 ram_rl_entry_chid_f(u32 v)
732{
733 return (v & 0xfffU) << 0U;
734}
735static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
736{
737 return (v & 0xfffffU) << 12U;
738}
739static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
740{
741 return (v & 0xffffffffU) << 0U;
742}
743static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
744{
745 return (v & 0xfU) << 16U;
746}
747static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void)
748{
749 return 0x00000003U;
750}
751static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
752{
753 return (v & 0xffU) << 24U;
754}
755static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void)
756{
757 return 0x00000080U;
758}
759static inline u32 ram_rl_entry_tsg_length_f(u32 v)
760{
761 return (v & 0xffU) << 0U;
762}
763static inline u32 ram_rl_entry_tsg_length_init_v(void)
764{
765 return 0x00000000U;
766}
767static inline u32 ram_rl_entry_tsg_length_min_v(void)
768{
769 return 0x00000001U;
770}
771static inline u32 ram_rl_entry_tsg_length_max_v(void)
772{
773 return 0x00000080U;
774}
775static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
776{
777 return (v & 0xfffU) << 0U;
778}
779static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
780{
781 return 0x00000008U;
782}
783static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
784{
785 return 0x00000008U;
786}
787static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
788{
789 return 0x0000000cU;
790}
791#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 06:16:48 -0400