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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/hw/gv100/hw_nvl_gv100.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/hw/gv100/hw_nvl_gv100.h')
-rw-r--r--include/nvgpu/hw/gv100/hw_nvl_gv100.h1571
1 files changed, 0 insertions, 1571 deletions
diff --git a/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/include/nvgpu/hw/gv100/hw_nvl_gv100.h
deleted file mode 100644
index 2e4ec16..0000000
--- a/include/nvgpu/hw/gv100/hw_nvl_gv100.h
+++ /dev/null
@@ -1,1571 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_nvl_gv100_h_
57#define _hw_nvl_gv100_h_
58
59static inline u32 nvl_link_state_r(void)
60{
61 return 0x00000000U;
62}
63static inline u32 nvl_link_state_state_f(u32 v)
64{
65 return (v & 0xffU) << 0U;
66}
67static inline u32 nvl_link_state_state_m(void)
68{
69 return 0xffU << 0U;
70}
71static inline u32 nvl_link_state_state_v(u32 r)
72{
73 return (r >> 0U) & 0xffU;
74}
75static inline u32 nvl_link_state_state_init_v(void)
76{
77 return 0x00000000U;
78}
79static inline u32 nvl_link_state_state_init_f(void)
80{
81 return 0x0U;
82}
83static inline u32 nvl_link_state_state_hwcfg_v(void)
84{
85 return 0x00000001U;
86}
87static inline u32 nvl_link_state_state_hwcfg_f(void)
88{
89 return 0x1U;
90}
91static inline u32 nvl_link_state_state_swcfg_v(void)
92{
93 return 0x00000002U;
94}
95static inline u32 nvl_link_state_state_swcfg_f(void)
96{
97 return 0x2U;
98}
99static inline u32 nvl_link_state_state_active_v(void)
100{
101 return 0x00000003U;
102}
103static inline u32 nvl_link_state_state_active_f(void)
104{
105 return 0x3U;
106}
107static inline u32 nvl_link_state_state_fault_v(void)
108{
109 return 0x00000004U;
110}
111static inline u32 nvl_link_state_state_fault_f(void)
112{
113 return 0x4U;
114}
115static inline u32 nvl_link_state_state_rcvy_ac_v(void)
116{
117 return 0x00000008U;
118}
119static inline u32 nvl_link_state_state_rcvy_ac_f(void)
120{
121 return 0x8U;
122}
123static inline u32 nvl_link_state_state_rcvy_sw_v(void)
124{
125 return 0x00000009U;
126}
127static inline u32 nvl_link_state_state_rcvy_sw_f(void)
128{
129 return 0x9U;
130}
131static inline u32 nvl_link_state_state_rcvy_rx_v(void)
132{
133 return 0x0000000aU;
134}
135static inline u32 nvl_link_state_state_rcvy_rx_f(void)
136{
137 return 0xaU;
138}
139static inline u32 nvl_link_state_an0_busy_f(u32 v)
140{
141 return (v & 0x1U) << 12U;
142}
143static inline u32 nvl_link_state_an0_busy_m(void)
144{
145 return 0x1U << 12U;
146}
147static inline u32 nvl_link_state_an0_busy_v(u32 r)
148{
149 return (r >> 12U) & 0x1U;
150}
151static inline u32 nvl_link_state_tl_busy_f(u32 v)
152{
153 return (v & 0x1U) << 13U;
154}
155static inline u32 nvl_link_state_tl_busy_m(void)
156{
157 return 0x1U << 13U;
158}
159static inline u32 nvl_link_state_tl_busy_v(u32 r)
160{
161 return (r >> 13U) & 0x1U;
162}
163static inline u32 nvl_link_state_dbg_substate_f(u32 v)
164{
165 return (v & 0xffffU) << 16U;
166}
167static inline u32 nvl_link_state_dbg_substate_m(void)
168{
169 return 0xffffU << 16U;
170}
171static inline u32 nvl_link_state_dbg_substate_v(u32 r)
172{
173 return (r >> 16U) & 0xffffU;
174}
175static inline u32 nvl_link_activity_r(void)
176{
177 return 0x0000000cU;
178}
179static inline u32 nvl_link_activity_blkact_f(u32 v)
180{
181 return (v & 0x7U) << 0U;
182}
183static inline u32 nvl_link_activity_blkact_m(void)
184{
185 return 0x7U << 0U;
186}
187static inline u32 nvl_link_activity_blkact_v(u32 r)
188{
189 return (r >> 0U) & 0x7U;
190}
191static inline u32 nvl_sublink_activity_r(u32 i)
192{
193 return 0x00000010U + i*4U;
194}
195static inline u32 nvl_sublink_activity_blkact0_f(u32 v)
196{
197 return (v & 0x7U) << 0U;
198}
199static inline u32 nvl_sublink_activity_blkact0_m(void)
200{
201 return 0x7U << 0U;
202}
203static inline u32 nvl_sublink_activity_blkact0_v(u32 r)
204{
205 return (r >> 0U) & 0x7U;
206}
207static inline u32 nvl_sublink_activity_blkact1_f(u32 v)
208{
209 return (v & 0x7U) << 8U;
210}
211static inline u32 nvl_sublink_activity_blkact1_m(void)
212{
213 return 0x7U << 8U;
214}
215static inline u32 nvl_sublink_activity_blkact1_v(u32 r)
216{
217 return (r >> 8U) & 0x7U;
218}
219static inline u32 nvl_link_config_r(void)
220{
221 return 0x00000018U;
222}
223static inline u32 nvl_link_config_ac_safe_en_f(u32 v)
224{
225 return (v & 0x1U) << 30U;
226}
227static inline u32 nvl_link_config_ac_safe_en_m(void)
228{
229 return 0x1U << 30U;
230}
231static inline u32 nvl_link_config_ac_safe_en_v(u32 r)
232{
233 return (r >> 30U) & 0x1U;
234}
235static inline u32 nvl_link_config_ac_safe_en_on_v(void)
236{
237 return 0x00000001U;
238}
239static inline u32 nvl_link_config_ac_safe_en_on_f(void)
240{
241 return 0x40000000U;
242}
243static inline u32 nvl_link_config_link_en_f(u32 v)
244{
245 return (v & 0x1U) << 31U;
246}
247static inline u32 nvl_link_config_link_en_m(void)
248{
249 return 0x1U << 31U;
250}
251static inline u32 nvl_link_config_link_en_v(u32 r)
252{
253 return (r >> 31U) & 0x1U;
254}
255static inline u32 nvl_link_config_link_en_on_v(void)
256{
257 return 0x00000001U;
258}
259static inline u32 nvl_link_config_link_en_on_f(void)
260{
261 return 0x80000000U;
262}
263static inline u32 nvl_link_change_r(void)
264{
265 return 0x00000040U;
266}
267static inline u32 nvl_link_change_oldstate_mask_f(u32 v)
268{
269 return (v & 0xfU) << 16U;
270}
271static inline u32 nvl_link_change_oldstate_mask_m(void)
272{
273 return 0xfU << 16U;
274}
275static inline u32 nvl_link_change_oldstate_mask_v(u32 r)
276{
277 return (r >> 16U) & 0xfU;
278}
279static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void)
280{
281 return 0x0000000fU;
282}
283static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void)
284{
285 return 0xf0000U;
286}
287static inline u32 nvl_link_change_newstate_f(u32 v)
288{
289 return (v & 0xfU) << 4U;
290}
291static inline u32 nvl_link_change_newstate_m(void)
292{
293 return 0xfU << 4U;
294}
295static inline u32 nvl_link_change_newstate_v(u32 r)
296{
297 return (r >> 4U) & 0xfU;
298}
299static inline u32 nvl_link_change_newstate_hwcfg_v(void)
300{
301 return 0x00000001U;
302}
303static inline u32 nvl_link_change_newstate_hwcfg_f(void)
304{
305 return 0x10U;
306}
307static inline u32 nvl_link_change_newstate_swcfg_v(void)
308{
309 return 0x00000002U;
310}
311static inline u32 nvl_link_change_newstate_swcfg_f(void)
312{
313 return 0x20U;
314}
315static inline u32 nvl_link_change_newstate_active_v(void)
316{
317 return 0x00000003U;
318}
319static inline u32 nvl_link_change_newstate_active_f(void)
320{
321 return 0x30U;
322}
323static inline u32 nvl_link_change_action_f(u32 v)
324{
325 return (v & 0x3U) << 2U;
326}
327static inline u32 nvl_link_change_action_m(void)
328{
329 return 0x3U << 2U;
330}
331static inline u32 nvl_link_change_action_v(u32 r)
332{
333 return (r >> 2U) & 0x3U;
334}
335static inline u32 nvl_link_change_action_ltssm_change_v(void)
336{
337 return 0x00000001U;
338}
339static inline u32 nvl_link_change_action_ltssm_change_f(void)
340{
341 return 0x4U;
342}
343static inline u32 nvl_link_change_status_f(u32 v)
344{
345 return (v & 0x3U) << 0U;
346}
347static inline u32 nvl_link_change_status_m(void)
348{
349 return 0x3U << 0U;
350}
351static inline u32 nvl_link_change_status_v(u32 r)
352{
353 return (r >> 0U) & 0x3U;
354}
355static inline u32 nvl_link_change_status_done_v(void)
356{
357 return 0x00000000U;
358}
359static inline u32 nvl_link_change_status_done_f(void)
360{
361 return 0x0U;
362}
363static inline u32 nvl_link_change_status_busy_v(void)
364{
365 return 0x00000001U;
366}
367static inline u32 nvl_link_change_status_busy_f(void)
368{
369 return 0x1U;
370}
371static inline u32 nvl_link_change_status_fault_v(void)
372{
373 return 0x00000002U;
374}
375static inline u32 nvl_link_change_status_fault_f(void)
376{
377 return 0x2U;
378}
379static inline u32 nvl_sublink_change_r(void)
380{
381 return 0x00000044U;
382}
383static inline u32 nvl_sublink_change_countdown_f(u32 v)
384{
385 return (v & 0xfffU) << 20U;
386}
387static inline u32 nvl_sublink_change_countdown_m(void)
388{
389 return 0xfffU << 20U;
390}
391static inline u32 nvl_sublink_change_countdown_v(u32 r)
392{
393 return (r >> 20U) & 0xfffU;
394}
395static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v)
396{
397 return (v & 0xfU) << 16U;
398}
399static inline u32 nvl_sublink_change_oldstate_mask_m(void)
400{
401 return 0xfU << 16U;
402}
403static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r)
404{
405 return (r >> 16U) & 0xfU;
406}
407static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void)
408{
409 return 0x0000000fU;
410}
411static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void)
412{
413 return 0xf0000U;
414}
415static inline u32 nvl_sublink_change_sublink_f(u32 v)
416{
417 return (v & 0xfU) << 12U;
418}
419static inline u32 nvl_sublink_change_sublink_m(void)
420{
421 return 0xfU << 12U;
422}
423static inline u32 nvl_sublink_change_sublink_v(u32 r)
424{
425 return (r >> 12U) & 0xfU;
426}
427static inline u32 nvl_sublink_change_sublink_tx_v(void)
428{
429 return 0x00000000U;
430}
431static inline u32 nvl_sublink_change_sublink_tx_f(void)
432{
433 return 0x0U;
434}
435static inline u32 nvl_sublink_change_sublink_rx_v(void)
436{
437 return 0x00000001U;
438}
439static inline u32 nvl_sublink_change_sublink_rx_f(void)
440{
441 return 0x1000U;
442}
443static inline u32 nvl_sublink_change_newstate_f(u32 v)
444{
445 return (v & 0xfU) << 4U;
446}
447static inline u32 nvl_sublink_change_newstate_m(void)
448{
449 return 0xfU << 4U;
450}
451static inline u32 nvl_sublink_change_newstate_v(u32 r)
452{
453 return (r >> 4U) & 0xfU;
454}
455static inline u32 nvl_sublink_change_newstate_hs_v(void)
456{
457 return 0x00000000U;
458}
459static inline u32 nvl_sublink_change_newstate_hs_f(void)
460{
461 return 0x0U;
462}
463static inline u32 nvl_sublink_change_newstate_eighth_v(void)
464{
465 return 0x00000004U;
466}
467static inline u32 nvl_sublink_change_newstate_eighth_f(void)
468{
469 return 0x40U;
470}
471static inline u32 nvl_sublink_change_newstate_train_v(void)
472{
473 return 0x00000005U;
474}
475static inline u32 nvl_sublink_change_newstate_train_f(void)
476{
477 return 0x50U;
478}
479static inline u32 nvl_sublink_change_newstate_safe_v(void)
480{
481 return 0x00000006U;
482}
483static inline u32 nvl_sublink_change_newstate_safe_f(void)
484{
485 return 0x60U;
486}
487static inline u32 nvl_sublink_change_newstate_off_v(void)
488{
489 return 0x00000007U;
490}
491static inline u32 nvl_sublink_change_newstate_off_f(void)
492{
493 return 0x70U;
494}
495static inline u32 nvl_sublink_change_action_f(u32 v)
496{
497 return (v & 0x3U) << 2U;
498}
499static inline u32 nvl_sublink_change_action_m(void)
500{
501 return 0x3U << 2U;
502}
503static inline u32 nvl_sublink_change_action_v(u32 r)
504{
505 return (r >> 2U) & 0x3U;
506}
507static inline u32 nvl_sublink_change_action_slsm_change_v(void)
508{
509 return 0x00000001U;
510}
511static inline u32 nvl_sublink_change_action_slsm_change_f(void)
512{
513 return 0x4U;
514}
515static inline u32 nvl_sublink_change_status_f(u32 v)
516{
517 return (v & 0x3U) << 0U;
518}
519static inline u32 nvl_sublink_change_status_m(void)
520{
521 return 0x3U << 0U;
522}
523static inline u32 nvl_sublink_change_status_v(u32 r)
524{
525 return (r >> 0U) & 0x3U;
526}
527static inline u32 nvl_sublink_change_status_done_v(void)
528{
529 return 0x00000000U;
530}
531static inline u32 nvl_sublink_change_status_done_f(void)
532{
533 return 0x0U;
534}
535static inline u32 nvl_sublink_change_status_busy_v(void)
536{
537 return 0x00000001U;
538}
539static inline u32 nvl_sublink_change_status_busy_f(void)
540{
541 return 0x1U;
542}
543static inline u32 nvl_sublink_change_status_fault_v(void)
544{
545 return 0x00000002U;
546}
547static inline u32 nvl_sublink_change_status_fault_f(void)
548{
549 return 0x2U;
550}
551static inline u32 nvl_link_test_r(void)
552{
553 return 0x00000048U;
554}
555static inline u32 nvl_link_test_mode_f(u32 v)
556{
557 return (v & 0x1U) << 0U;
558}
559static inline u32 nvl_link_test_mode_m(void)
560{
561 return 0x1U << 0U;
562}
563static inline u32 nvl_link_test_mode_v(u32 r)
564{
565 return (r >> 0U) & 0x1U;
566}
567static inline u32 nvl_link_test_mode_enable_v(void)
568{
569 return 0x00000001U;
570}
571static inline u32 nvl_link_test_mode_enable_f(void)
572{
573 return 0x1U;
574}
575static inline u32 nvl_link_test_auto_hwcfg_f(u32 v)
576{
577 return (v & 0x1U) << 30U;
578}
579static inline u32 nvl_link_test_auto_hwcfg_m(void)
580{
581 return 0x1U << 30U;
582}
583static inline u32 nvl_link_test_auto_hwcfg_v(u32 r)
584{
585 return (r >> 30U) & 0x1U;
586}
587static inline u32 nvl_link_test_auto_hwcfg_enable_v(void)
588{
589 return 0x00000001U;
590}
591static inline u32 nvl_link_test_auto_hwcfg_enable_f(void)
592{
593 return 0x40000000U;
594}
595static inline u32 nvl_link_test_auto_nvhs_f(u32 v)
596{
597 return (v & 0x1U) << 31U;
598}
599static inline u32 nvl_link_test_auto_nvhs_m(void)
600{
601 return 0x1U << 31U;
602}
603static inline u32 nvl_link_test_auto_nvhs_v(u32 r)
604{
605 return (r >> 31U) & 0x1U;
606}
607static inline u32 nvl_link_test_auto_nvhs_enable_v(void)
608{
609 return 0x00000001U;
610}
611static inline u32 nvl_link_test_auto_nvhs_enable_f(void)
612{
613 return 0x80000000U;
614}
615static inline u32 nvl_sl0_slsm_status_tx_r(void)
616{
617 return 0x00002024U;
618}
619static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v)
620{
621 return (v & 0xfU) << 0U;
622}
623static inline u32 nvl_sl0_slsm_status_tx_substate_m(void)
624{
625 return 0xfU << 0U;
626}
627static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r)
628{
629 return (r >> 0U) & 0xfU;
630}
631static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v)
632{
633 return (v & 0xfU) << 4U;
634}
635static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void)
636{
637 return 0xfU << 4U;
638}
639static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r)
640{
641 return (r >> 4U) & 0xfU;
642}
643static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void)
644{
645 return 0x00000000U;
646}
647static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void)
648{
649 return 0x0U;
650}
651static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void)
652{
653 return 0x00000004U;
654}
655static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void)
656{
657 return 0x40U;
658}
659static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void)
660{
661 return 0x00000005U;
662}
663static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void)
664{
665 return 0x50U;
666}
667static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void)
668{
669 return 0x00000007U;
670}
671static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void)
672{
673 return 0x70U;
674}
675static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void)
676{
677 return 0x00000006U;
678}
679static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void)
680{
681 return 0x60U;
682}
683static inline u32 nvl_sl1_slsm_status_rx_r(void)
684{
685 return 0x00003014U;
686}
687static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v)
688{
689 return (v & 0xfU) << 0U;
690}
691static inline u32 nvl_sl1_slsm_status_rx_substate_m(void)
692{
693 return 0xfU << 0U;
694}
695static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r)
696{
697 return (r >> 0U) & 0xfU;
698}
699static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v)
700{
701 return (v & 0xfU) << 4U;
702}
703static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void)
704{
705 return 0xfU << 4U;
706}
707static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r)
708{
709 return (r >> 4U) & 0xfU;
710}
711static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void)
712{
713 return 0x00000000U;
714}
715static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void)
716{
717 return 0x0U;
718}
719static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void)
720{
721 return 0x00000004U;
722}
723static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void)
724{
725 return 0x40U;
726}
727static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void)
728{
729 return 0x00000005U;
730}
731static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void)
732{
733 return 0x50U;
734}
735static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void)
736{
737 return 0x00000007U;
738}
739static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void)
740{
741 return 0x70U;
742}
743static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void)
744{
745 return 0x00000006U;
746}
747static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void)
748{
749 return 0x60U;
750}
751static inline u32 nvl_sl0_safe_ctrl2_tx_r(void)
752{
753 return 0x00002008U;
754}
755static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v)
756{
757 return (v & 0x7ffU) << 0U;
758}
759static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void)
760{
761 return 0x7ffU << 0U;
762}
763static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r)
764{
765 return (r >> 0U) & 0x7ffU;
766}
767static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void)
768{
769 return 0x00000728U;
770}
771static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void)
772{
773 return 0x728U;
774}
775static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v)
776{
777 return (v & 0x1fU) << 11U;
778}
779static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void)
780{
781 return 0x1fU << 11U;
782}
783static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r)
784{
785 return (r >> 11U) & 0x1fU;
786}
787static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void)
788{
789 return 0x0000000fU;
790}
791static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void)
792{
793 return 0x7800U;
794}
795static inline u32 nvl_sl1_error_rate_ctrl_r(void)
796{
797 return 0x00003284U;
798}
799static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v)
800{
801 return (v & 0x7U) << 0U;
802}
803static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void)
804{
805 return 0x7U << 0U;
806}
807static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r)
808{
809 return (r >> 0U) & 0x7U;
810}
811static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v)
812{
813 return (v & 0x7U) << 16U;
814}
815static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void)
816{
817 return 0x7U << 16U;
818}
819static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r)
820{
821 return (r >> 16U) & 0x7U;
822}
823static inline u32 nvl_sl1_rxslsm_timeout_2_r(void)
824{
825 return 0x00003034U;
826}
827static inline u32 nvl_txiobist_configreg_r(void)
828{
829 return 0x00002e14U;
830}
831static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v)
832{
833 return (v & 0x1U) << 17U;
834}
835static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void)
836{
837 return 0x1U << 17U;
838}
839static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r)
840{
841 return (r >> 17U) & 0x1U;
842}
843static inline u32 nvl_txiobist_config_r(void)
844{
845 return 0x00002e10U;
846}
847static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v)
848{
849 return (v & 0x1U) << 2U;
850}
851static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void)
852{
853 return 0x1U << 2U;
854}
855static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r)
856{
857 return (r >> 2U) & 0x1U;
858}
859static inline u32 nvl_intr_r(void)
860{
861 return 0x00000050U;
862}
863static inline u32 nvl_intr_tx_replay_f(u32 v)
864{
865 return (v & 0x1U) << 0U;
866}
867static inline u32 nvl_intr_tx_replay_m(void)
868{
869 return 0x1U << 0U;
870}
871static inline u32 nvl_intr_tx_replay_v(u32 r)
872{
873 return (r >> 0U) & 0x1U;
874}
875static inline u32 nvl_intr_tx_recovery_short_f(u32 v)
876{
877 return (v & 0x1U) << 1U;
878}
879static inline u32 nvl_intr_tx_recovery_short_m(void)
880{
881 return 0x1U << 1U;
882}
883static inline u32 nvl_intr_tx_recovery_short_v(u32 r)
884{
885 return (r >> 1U) & 0x1U;
886}
887static inline u32 nvl_intr_tx_recovery_long_f(u32 v)
888{
889 return (v & 0x1U) << 2U;
890}
891static inline u32 nvl_intr_tx_recovery_long_m(void)
892{
893 return 0x1U << 2U;
894}
895static inline u32 nvl_intr_tx_recovery_long_v(u32 r)
896{
897 return (r >> 2U) & 0x1U;
898}
899static inline u32 nvl_intr_tx_fault_ram_f(u32 v)
900{
901 return (v & 0x1U) << 4U;
902}
903static inline u32 nvl_intr_tx_fault_ram_m(void)
904{
905 return 0x1U << 4U;
906}
907static inline u32 nvl_intr_tx_fault_ram_v(u32 r)
908{
909 return (r >> 4U) & 0x1U;
910}
911static inline u32 nvl_intr_tx_fault_interface_f(u32 v)
912{
913 return (v & 0x1U) << 5U;
914}
915static inline u32 nvl_intr_tx_fault_interface_m(void)
916{
917 return 0x1U << 5U;
918}
919static inline u32 nvl_intr_tx_fault_interface_v(u32 r)
920{
921 return (r >> 5U) & 0x1U;
922}
923static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v)
924{
925 return (v & 0x1U) << 8U;
926}
927static inline u32 nvl_intr_tx_fault_sublink_change_m(void)
928{
929 return 0x1U << 8U;
930}
931static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r)
932{
933 return (r >> 8U) & 0x1U;
934}
935static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v)
936{
937 return (v & 0x1U) << 16U;
938}
939static inline u32 nvl_intr_rx_fault_sublink_change_m(void)
940{
941 return 0x1U << 16U;
942}
943static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r)
944{
945 return (r >> 16U) & 0x1U;
946}
947static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v)
948{
949 return (v & 0x1U) << 20U;
950}
951static inline u32 nvl_intr_rx_fault_dl_protocol_m(void)
952{
953 return 0x1U << 20U;
954}
955static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r)
956{
957 return (r >> 20U) & 0x1U;
958}
959static inline u32 nvl_intr_rx_short_error_rate_f(u32 v)
960{
961 return (v & 0x1U) << 21U;
962}
963static inline u32 nvl_intr_rx_short_error_rate_m(void)
964{
965 return 0x1U << 21U;
966}
967static inline u32 nvl_intr_rx_short_error_rate_v(u32 r)
968{
969 return (r >> 21U) & 0x1U;
970}
971static inline u32 nvl_intr_rx_long_error_rate_f(u32 v)
972{
973 return (v & 0x1U) << 22U;
974}
975static inline u32 nvl_intr_rx_long_error_rate_m(void)
976{
977 return 0x1U << 22U;
978}
979static inline u32 nvl_intr_rx_long_error_rate_v(u32 r)
980{
981 return (r >> 22U) & 0x1U;
982}
983static inline u32 nvl_intr_rx_ila_trigger_f(u32 v)
984{
985 return (v & 0x1U) << 23U;
986}
987static inline u32 nvl_intr_rx_ila_trigger_m(void)
988{
989 return 0x1U << 23U;
990}
991static inline u32 nvl_intr_rx_ila_trigger_v(u32 r)
992{
993 return (r >> 23U) & 0x1U;
994}
995static inline u32 nvl_intr_rx_crc_counter_f(u32 v)
996{
997 return (v & 0x1U) << 24U;
998}
999static inline u32 nvl_intr_rx_crc_counter_m(void)
1000{
1001 return 0x1U << 24U;
1002}
1003static inline u32 nvl_intr_rx_crc_counter_v(u32 r)
1004{
1005 return (r >> 24U) & 0x1U;
1006}
1007static inline u32 nvl_intr_ltssm_fault_f(u32 v)
1008{
1009 return (v & 0x1U) << 28U;
1010}
1011static inline u32 nvl_intr_ltssm_fault_m(void)
1012{
1013 return 0x1U << 28U;
1014}
1015static inline u32 nvl_intr_ltssm_fault_v(u32 r)
1016{
1017 return (r >> 28U) & 0x1U;
1018}
1019static inline u32 nvl_intr_ltssm_protocol_f(u32 v)
1020{
1021 return (v & 0x1U) << 29U;
1022}
1023static inline u32 nvl_intr_ltssm_protocol_m(void)
1024{
1025 return 0x1U << 29U;
1026}
1027static inline u32 nvl_intr_ltssm_protocol_v(u32 r)
1028{
1029 return (r >> 29U) & 0x1U;
1030}
1031static inline u32 nvl_intr_minion_request_f(u32 v)
1032{
1033 return (v & 0x1U) << 30U;
1034}
1035static inline u32 nvl_intr_minion_request_m(void)
1036{
1037 return 0x1U << 30U;
1038}
1039static inline u32 nvl_intr_minion_request_v(u32 r)
1040{
1041 return (r >> 30U) & 0x1U;
1042}
1043static inline u32 nvl_intr_sw2_r(void)
1044{
1045 return 0x00000054U;
1046}
1047static inline u32 nvl_intr_minion_r(void)
1048{
1049 return 0x00000060U;
1050}
1051static inline u32 nvl_intr_minion_tx_replay_f(u32 v)
1052{
1053 return (v & 0x1U) << 0U;
1054}
1055static inline u32 nvl_intr_minion_tx_replay_m(void)
1056{
1057 return 0x1U << 0U;
1058}
1059static inline u32 nvl_intr_minion_tx_replay_v(u32 r)
1060{
1061 return (r >> 0U) & 0x1U;
1062}
1063static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v)
1064{
1065 return (v & 0x1U) << 1U;
1066}
1067static inline u32 nvl_intr_minion_tx_recovery_short_m(void)
1068{
1069 return 0x1U << 1U;
1070}
1071static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r)
1072{
1073 return (r >> 1U) & 0x1U;
1074}
1075static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v)
1076{
1077 return (v & 0x1U) << 2U;
1078}
1079static inline u32 nvl_intr_minion_tx_recovery_long_m(void)
1080{
1081 return 0x1U << 2U;
1082}
1083static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r)
1084{
1085 return (r >> 2U) & 0x1U;
1086}
1087static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v)
1088{
1089 return (v & 0x1U) << 4U;
1090}
1091static inline u32 nvl_intr_minion_tx_fault_ram_m(void)
1092{
1093 return 0x1U << 4U;
1094}
1095static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r)
1096{
1097 return (r >> 4U) & 0x1U;
1098}
1099static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v)
1100{
1101 return (v & 0x1U) << 5U;
1102}
1103static inline u32 nvl_intr_minion_tx_fault_interface_m(void)
1104{
1105 return 0x1U << 5U;
1106}
1107static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r)
1108{
1109 return (r >> 5U) & 0x1U;
1110}
1111static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v)
1112{
1113 return (v & 0x1U) << 8U;
1114}
1115static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void)
1116{
1117 return 0x1U << 8U;
1118}
1119static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r)
1120{
1121 return (r >> 8U) & 0x1U;
1122}
1123static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v)
1124{
1125 return (v & 0x1U) << 16U;
1126}
1127static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void)
1128{
1129 return 0x1U << 16U;
1130}
1131static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r)
1132{
1133 return (r >> 16U) & 0x1U;
1134}
1135static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v)
1136{
1137 return (v & 0x1U) << 20U;
1138}
1139static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void)
1140{
1141 return 0x1U << 20U;
1142}
1143static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r)
1144{
1145 return (r >> 20U) & 0x1U;
1146}
1147static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v)
1148{
1149 return (v & 0x1U) << 21U;
1150}
1151static inline u32 nvl_intr_minion_rx_short_error_rate_m(void)
1152{
1153 return 0x1U << 21U;
1154}
1155static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r)
1156{
1157 return (r >> 21U) & 0x1U;
1158}
1159static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v)
1160{
1161 return (v & 0x1U) << 22U;
1162}
1163static inline u32 nvl_intr_minion_rx_long_error_rate_m(void)
1164{
1165 return 0x1U << 22U;
1166}
1167static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r)
1168{
1169 return (r >> 22U) & 0x1U;
1170}
1171static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v)
1172{
1173 return (v & 0x1U) << 23U;
1174}
1175static inline u32 nvl_intr_minion_rx_ila_trigger_m(void)
1176{
1177 return 0x1U << 23U;
1178}
1179static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r)
1180{
1181 return (r >> 23U) & 0x1U;
1182}
1183static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v)
1184{
1185 return (v & 0x1U) << 24U;
1186}
1187static inline u32 nvl_intr_minion_rx_crc_counter_m(void)
1188{
1189 return 0x1U << 24U;
1190}
1191static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r)
1192{
1193 return (r >> 24U) & 0x1U;
1194}
1195static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v)
1196{
1197 return (v & 0x1U) << 28U;
1198}
1199static inline u32 nvl_intr_minion_ltssm_fault_m(void)
1200{
1201 return 0x1U << 28U;
1202}
1203static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r)
1204{
1205 return (r >> 28U) & 0x1U;
1206}
1207static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v)
1208{
1209 return (v & 0x1U) << 29U;
1210}
1211static inline u32 nvl_intr_minion_ltssm_protocol_m(void)
1212{
1213 return 0x1U << 29U;
1214}
1215static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r)
1216{
1217 return (r >> 29U) & 0x1U;
1218}
1219static inline u32 nvl_intr_minion_minion_request_f(u32 v)
1220{
1221 return (v & 0x1U) << 30U;
1222}
1223static inline u32 nvl_intr_minion_minion_request_m(void)
1224{
1225 return 0x1U << 30U;
1226}
1227static inline u32 nvl_intr_minion_minion_request_v(u32 r)
1228{
1229 return (r >> 30U) & 0x1U;
1230}
1231static inline u32 nvl_intr_nonstall_en_r(void)
1232{
1233 return 0x0000005cU;
1234}
1235static inline u32 nvl_intr_stall_en_r(void)
1236{
1237 return 0x00000058U;
1238}
1239static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v)
1240{
1241 return (v & 0x1U) << 0U;
1242}
1243static inline u32 nvl_intr_stall_en_tx_replay_m(void)
1244{
1245 return 0x1U << 0U;
1246}
1247static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r)
1248{
1249 return (r >> 0U) & 0x1U;
1250}
1251static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v)
1252{
1253 return (v & 0x1U) << 1U;
1254}
1255static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void)
1256{
1257 return 0x1U << 1U;
1258}
1259static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r)
1260{
1261 return (r >> 1U) & 0x1U;
1262}
1263static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void)
1264{
1265 return 0x00000001U;
1266}
1267static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void)
1268{
1269 return 0x2U;
1270}
1271static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v)
1272{
1273 return (v & 0x1U) << 2U;
1274}
1275static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void)
1276{
1277 return 0x1U << 2U;
1278}
1279static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r)
1280{
1281 return (r >> 2U) & 0x1U;
1282}
1283static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void)
1284{
1285 return 0x00000001U;
1286}
1287static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void)
1288{
1289 return 0x4U;
1290}
1291static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v)
1292{
1293 return (v & 0x1U) << 4U;
1294}
1295static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void)
1296{
1297 return 0x1U << 4U;
1298}
1299static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r)
1300{
1301 return (r >> 4U) & 0x1U;
1302}
1303static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void)
1304{
1305 return 0x00000001U;
1306}
1307static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void)
1308{
1309 return 0x10U;
1310}
1311static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v)
1312{
1313 return (v & 0x1U) << 5U;
1314}
1315static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void)
1316{
1317 return 0x1U << 5U;
1318}
1319static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r)
1320{
1321 return (r >> 5U) & 0x1U;
1322}
1323static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void)
1324{
1325 return 0x00000001U;
1326}
1327static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void)
1328{
1329 return 0x20U;
1330}
1331static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v)
1332{
1333 return (v & 0x1U) << 8U;
1334}
1335static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void)
1336{
1337 return 0x1U << 8U;
1338}
1339static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r)
1340{
1341 return (r >> 8U) & 0x1U;
1342}
1343static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void)
1344{
1345 return 0x00000001U;
1346}
1347static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void)
1348{
1349 return 0x100U;
1350}
1351static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v)
1352{
1353 return (v & 0x1U) << 16U;
1354}
1355static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void)
1356{
1357 return 0x1U << 16U;
1358}
1359static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r)
1360{
1361 return (r >> 16U) & 0x1U;
1362}
1363static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void)
1364{
1365 return 0x00000001U;
1366}
1367static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void)
1368{
1369 return 0x10000U;
1370}
1371static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v)
1372{
1373 return (v & 0x1U) << 20U;
1374}
1375static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void)
1376{
1377 return 0x1U << 20U;
1378}
1379static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r)
1380{
1381 return (r >> 20U) & 0x1U;
1382}
1383static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void)
1384{
1385 return 0x00000001U;
1386}
1387static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void)
1388{
1389 return 0x100000U;
1390}
1391static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v)
1392{
1393 return (v & 0x1U) << 21U;
1394}
1395static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void)
1396{
1397 return 0x1U << 21U;
1398}
1399static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r)
1400{
1401 return (r >> 21U) & 0x1U;
1402}
1403static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void)
1404{
1405 return 0x00000001U;
1406}
1407static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void)
1408{
1409 return 0x200000U;
1410}
1411static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v)
1412{
1413 return (v & 0x1U) << 22U;
1414}
1415static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void)
1416{
1417 return 0x1U << 22U;
1418}
1419static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r)
1420{
1421 return (r >> 22U) & 0x1U;
1422}
1423static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void)
1424{
1425 return 0x00000001U;
1426}
1427static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void)
1428{
1429 return 0x400000U;
1430}
1431static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v)
1432{
1433 return (v & 0x1U) << 23U;
1434}
1435static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void)
1436{
1437 return 0x1U << 23U;
1438}
1439static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r)
1440{
1441 return (r >> 23U) & 0x1U;
1442}
1443static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void)
1444{
1445 return 0x00000001U;
1446}
1447static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void)
1448{
1449 return 0x800000U;
1450}
1451static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v)
1452{
1453 return (v & 0x1U) << 24U;
1454}
1455static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void)
1456{
1457 return 0x1U << 24U;
1458}
1459static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r)
1460{
1461 return (r >> 24U) & 0x1U;
1462}
1463static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void)
1464{
1465 return 0x00000001U;
1466}
1467static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void)
1468{
1469 return 0x1000000U;
1470}
1471static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v)
1472{
1473 return (v & 0x1U) << 28U;
1474}
1475static inline u32 nvl_intr_stall_en_ltssm_fault_m(void)
1476{
1477 return 0x1U << 28U;
1478}
1479static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r)
1480{
1481 return (r >> 28U) & 0x1U;
1482}
1483static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void)
1484{
1485 return 0x00000001U;
1486}
1487static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void)
1488{
1489 return 0x10000000U;
1490}
1491static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v)
1492{
1493 return (v & 0x1U) << 29U;
1494}
1495static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void)
1496{
1497 return 0x1U << 29U;
1498}
1499static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r)
1500{
1501 return (r >> 29U) & 0x1U;
1502}
1503static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void)
1504{
1505 return 0x00000001U;
1506}
1507static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void)
1508{
1509 return 0x20000000U;
1510}
1511static inline u32 nvl_intr_stall_en_minion_request_f(u32 v)
1512{
1513 return (v & 0x1U) << 30U;
1514}
1515static inline u32 nvl_intr_stall_en_minion_request_m(void)
1516{
1517 return 0x1U << 30U;
1518}
1519static inline u32 nvl_intr_stall_en_minion_request_v(u32 r)
1520{
1521 return (r >> 30U) & 0x1U;
1522}
1523static inline u32 nvl_intr_stall_en_minion_request_enable_v(void)
1524{
1525 return 0x00000001U;
1526}
1527static inline u32 nvl_intr_stall_en_minion_request_enable_f(void)
1528{
1529 return 0x40000000U;
1530}
1531static inline u32 nvl_br0_cfg_cal_r(void)
1532{
1533 return 0x0000281cU;
1534}
1535static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v)
1536{
1537 return (v & 0x1U) << 0U;
1538}
1539static inline u32 nvl_br0_cfg_cal_rxcal_m(void)
1540{
1541 return 0x1U << 0U;
1542}
1543static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r)
1544{
1545 return (r >> 0U) & 0x1U;
1546}
1547static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void)
1548{
1549 return 0x00000001U;
1550}
1551static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void)
1552{
1553 return 0x1U;
1554}
1555static inline u32 nvl_br0_cfg_status_cal_r(void)
1556{
1557 return 0x00002838U;
1558}
1559static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v)
1560{
1561 return (v & 0x1U) << 2U;
1562}
1563static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void)
1564{
1565 return 0x1U << 2U;
1566}
1567static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r)
1568{
1569 return (r >> 2U) & 0x1U;
1570}
1571#endif
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