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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/hw/gk20a/hw_fifo_gk20a.h')
-rw-r--r--include/nvgpu/hw/gk20a/hw_fifo_gk20a.h619
1 files changed, 0 insertions, 619 deletions
diff --git a/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h b/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
deleted file mode 100644
index e61e386..0000000
--- a/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
+++ /dev/null
@@ -1,619 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_fifo_gk20a_h_
57#define _hw_fifo_gk20a_h_
58
59static inline u32 fifo_bar1_base_r(void)
60{
61 return 0x00002254U;
62}
63static inline u32 fifo_bar1_base_ptr_f(u32 v)
64{
65 return (v & 0xfffffffU) << 0U;
66}
67static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
68{
69 return 0x0000000cU;
70}
71static inline u32 fifo_bar1_base_valid_false_f(void)
72{
73 return 0x0U;
74}
75static inline u32 fifo_bar1_base_valid_true_f(void)
76{
77 return 0x10000000U;
78}
79static inline u32 fifo_runlist_base_r(void)
80{
81 return 0x00002270U;
82}
83static inline u32 fifo_runlist_base_ptr_f(u32 v)
84{
85 return (v & 0xfffffffU) << 0U;
86}
87static inline u32 fifo_runlist_base_target_vid_mem_f(void)
88{
89 return 0x0U;
90}
91static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
92{
93 return 0x20000000U;
94}
95static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
96{
97 return 0x30000000U;
98}
99static inline u32 fifo_runlist_r(void)
100{
101 return 0x00002274U;
102}
103static inline u32 fifo_runlist_engine_f(u32 v)
104{
105 return (v & 0xfU) << 20U;
106}
107static inline u32 fifo_eng_runlist_base_r(u32 i)
108{
109 return 0x00002280U + i*8U;
110}
111static inline u32 fifo_eng_runlist_base__size_1_v(void)
112{
113 return 0x00000001U;
114}
115static inline u32 fifo_eng_runlist_r(u32 i)
116{
117 return 0x00002284U + i*8U;
118}
119static inline u32 fifo_eng_runlist__size_1_v(void)
120{
121 return 0x00000001U;
122}
123static inline u32 fifo_eng_runlist_length_f(u32 v)
124{
125 return (v & 0xffffU) << 0U;
126}
127static inline u32 fifo_eng_runlist_length_max_v(void)
128{
129 return 0x0000ffffU;
130}
131static inline u32 fifo_eng_runlist_pending_true_f(void)
132{
133 return 0x100000U;
134}
135static inline u32 fifo_runlist_timeslice_r(u32 i)
136{
137 return 0x00002310U + i*4U;
138}
139static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
140{
141 return 0x80U;
142}
143static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
144{
145 return 0x3000U;
146}
147static inline u32 fifo_runlist_timeslice_enable_true_f(void)
148{
149 return 0x10000000U;
150}
151static inline u32 fifo_eng_timeout_r(void)
152{
153 return 0x00002a0cU;
154}
155static inline u32 fifo_eng_timeout_period_max_f(void)
156{
157 return 0x7fffffffU;
158}
159static inline u32 fifo_eng_timeout_detection_enabled_f(void)
160{
161 return 0x80000000U;
162}
163static inline u32 fifo_eng_timeout_detection_disabled_f(void)
164{
165 return 0x0U;
166}
167static inline u32 fifo_pb_timeslice_r(u32 i)
168{
169 return 0x00002350U + i*4U;
170}
171static inline u32 fifo_pb_timeslice_timeout_16_f(void)
172{
173 return 0x10U;
174}
175static inline u32 fifo_pb_timeslice_timescale_0_f(void)
176{
177 return 0x0U;
178}
179static inline u32 fifo_pb_timeslice_enable_true_f(void)
180{
181 return 0x10000000U;
182}
183static inline u32 fifo_pbdma_map_r(u32 i)
184{
185 return 0x00002390U + i*4U;
186}
187static inline u32 fifo_intr_0_r(void)
188{
189 return 0x00002100U;
190}
191static inline u32 fifo_intr_0_bind_error_pending_f(void)
192{
193 return 0x1U;
194}
195static inline u32 fifo_intr_0_bind_error_reset_f(void)
196{
197 return 0x1U;
198}
199static inline u32 fifo_intr_0_pio_error_pending_f(void)
200{
201 return 0x10U;
202}
203static inline u32 fifo_intr_0_pio_error_reset_f(void)
204{
205 return 0x10U;
206}
207static inline u32 fifo_intr_0_sched_error_pending_f(void)
208{
209 return 0x100U;
210}
211static inline u32 fifo_intr_0_sched_error_reset_f(void)
212{
213 return 0x100U;
214}
215static inline u32 fifo_intr_0_chsw_error_pending_f(void)
216{
217 return 0x10000U;
218}
219static inline u32 fifo_intr_0_chsw_error_reset_f(void)
220{
221 return 0x10000U;
222}
223static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
224{
225 return 0x800000U;
226}
227static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
228{
229 return 0x800000U;
230}
231static inline u32 fifo_intr_0_lb_error_pending_f(void)
232{
233 return 0x1000000U;
234}
235static inline u32 fifo_intr_0_lb_error_reset_f(void)
236{
237 return 0x1000000U;
238}
239static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
240{
241 return 0x8000000U;
242}
243static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
244{
245 return 0x8000000U;
246}
247static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
248{
249 return 0x10000000U;
250}
251static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
252{
253 return 0x20000000U;
254}
255static inline u32 fifo_intr_0_runlist_event_pending_f(void)
256{
257 return 0x40000000U;
258}
259static inline u32 fifo_intr_0_channel_intr_pending_f(void)
260{
261 return 0x80000000U;
262}
263static inline u32 fifo_intr_en_0_r(void)
264{
265 return 0x00002140U;
266}
267static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
268{
269 return (v & 0x1U) << 8U;
270}
271static inline u32 fifo_intr_en_0_sched_error_m(void)
272{
273 return 0x1U << 8U;
274}
275static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
276{
277 return (v & 0x1U) << 28U;
278}
279static inline u32 fifo_intr_en_0_mmu_fault_m(void)
280{
281 return 0x1U << 28U;
282}
283static inline u32 fifo_intr_en_1_r(void)
284{
285 return 0x00002528U;
286}
287static inline u32 fifo_intr_bind_error_r(void)
288{
289 return 0x0000252cU;
290}
291static inline u32 fifo_intr_sched_error_r(void)
292{
293 return 0x0000254cU;
294}
295static inline u32 fifo_intr_sched_error_code_f(u32 v)
296{
297 return (v & 0xffU) << 0U;
298}
299static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
300{
301 return 0x0000000aU;
302}
303static inline u32 fifo_intr_chsw_error_r(void)
304{
305 return 0x0000256cU;
306}
307static inline u32 fifo_intr_mmu_fault_id_r(void)
308{
309 return 0x0000259cU;
310}
311static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
312{
313 return 0x00000000U;
314}
315static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
316{
317 return 0x0U;
318}
319static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
320{
321 return 0x00002800U + i*16U;
322}
323static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
324{
325 return (r >> 0U) & 0xfffffffU;
326}
327static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
328{
329 return 0x0000000cU;
330}
331static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
332{
333 return 0x00002804U + i*16U;
334}
335static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
336{
337 return 0x00002808U + i*16U;
338}
339static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
340{
341 return 0x0000280cU + i*16U;
342}
343static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
344{
345 return (r >> 0U) & 0xfU;
346}
347static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
348{
349 return (r >> 7U) & 0x1U;
350}
351static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
352{
353 return (r >> 6U) & 0x1U;
354}
355static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
356{
357 return 0x00000000U;
358}
359static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
360{
361 return 0x00000001U;
362}
363static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
364{
365 return (r >> 8U) & 0x1fU;
366}
367static inline u32 fifo_intr_pbdma_id_r(void)
368{
369 return 0x000025a0U;
370}
371static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
372{
373 return (v & 0x1U) << (0U + i*1U);
374}
375static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
376{
377 return (r >> (0U + i*1U)) & 0x1U;
378}
379static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
380{
381 return 0x00000001U;
382}
383static inline u32 fifo_intr_runlist_r(void)
384{
385 return 0x00002a00U;
386}
387static inline u32 fifo_fb_timeout_r(void)
388{
389 return 0x00002a04U;
390}
391static inline u32 fifo_fb_timeout_period_m(void)
392{
393 return 0x3fffffffU << 0U;
394}
395static inline u32 fifo_fb_timeout_period_max_f(void)
396{
397 return 0x3fffffffU;
398}
399static inline u32 fifo_pb_timeout_r(void)
400{
401 return 0x00002a08U;
402}
403static inline u32 fifo_pb_timeout_detection_enabled_f(void)
404{
405 return 0x80000000U;
406}
407static inline u32 fifo_error_sched_disable_r(void)
408{
409 return 0x0000262cU;
410}
411static inline u32 fifo_sched_disable_r(void)
412{
413 return 0x00002630U;
414}
415static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
416{
417 return (v & 0x1U) << (0U + i*1U);
418}
419static inline u32 fifo_sched_disable_runlist_m(u32 i)
420{
421 return 0x1U << (0U + i*1U);
422}
423static inline u32 fifo_sched_disable_true_v(void)
424{
425 return 0x00000001U;
426}
427static inline u32 fifo_preempt_r(void)
428{
429 return 0x00002634U;
430}
431static inline u32 fifo_preempt_pending_true_f(void)
432{
433 return 0x100000U;
434}
435static inline u32 fifo_preempt_type_channel_f(void)
436{
437 return 0x0U;
438}
439static inline u32 fifo_preempt_type_tsg_f(void)
440{
441 return 0x1000000U;
442}
443static inline u32 fifo_preempt_chid_f(u32 v)
444{
445 return (v & 0xfffU) << 0U;
446}
447static inline u32 fifo_preempt_id_f(u32 v)
448{
449 return (v & 0xfffU) << 0U;
450}
451static inline u32 fifo_trigger_mmu_fault_r(u32 i)
452{
453 return 0x00002a30U + i*4U;
454}
455static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
456{
457 return (v & 0x1fU) << 0U;
458}
459static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
460{
461 return (v & 0x1U) << 8U;
462}
463static inline u32 fifo_engine_status_r(u32 i)
464{
465 return 0x00002640U + i*8U;
466}
467static inline u32 fifo_engine_status__size_1_v(void)
468{
469 return 0x00000002U;
470}
471static inline u32 fifo_engine_status_id_v(u32 r)
472{
473 return (r >> 0U) & 0xfffU;
474}
475static inline u32 fifo_engine_status_id_type_v(u32 r)
476{
477 return (r >> 12U) & 0x1U;
478}
479static inline u32 fifo_engine_status_id_type_chid_v(void)
480{
481 return 0x00000000U;
482}
483static inline u32 fifo_engine_status_id_type_tsgid_v(void)
484{
485 return 0x00000001U;
486}
487static inline u32 fifo_engine_status_ctx_status_v(u32 r)
488{
489 return (r >> 13U) & 0x7U;
490}
491static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
492{
493 return 0x00000000U;
494}
495static inline u32 fifo_engine_status_ctx_status_valid_v(void)
496{
497 return 0x00000001U;
498}
499static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
500{
501 return 0x00000005U;
502}
503static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
504{
505 return 0x00000006U;
506}
507static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
508{
509 return 0x00000007U;
510}
511static inline u32 fifo_engine_status_next_id_v(u32 r)
512{
513 return (r >> 16U) & 0xfffU;
514}
515static inline u32 fifo_engine_status_next_id_type_v(u32 r)
516{
517 return (r >> 28U) & 0x1U;
518}
519static inline u32 fifo_engine_status_next_id_type_chid_v(void)
520{
521 return 0x00000000U;
522}
523static inline u32 fifo_engine_status_faulted_v(u32 r)
524{
525 return (r >> 30U) & 0x1U;
526}
527static inline u32 fifo_engine_status_faulted_true_v(void)
528{
529 return 0x00000001U;
530}
531static inline u32 fifo_engine_status_engine_v(u32 r)
532{
533 return (r >> 31U) & 0x1U;
534}
535static inline u32 fifo_engine_status_engine_idle_v(void)
536{
537 return 0x00000000U;
538}
539static inline u32 fifo_engine_status_engine_busy_v(void)
540{
541 return 0x00000001U;
542}
543static inline u32 fifo_engine_status_ctxsw_v(u32 r)
544{
545 return (r >> 15U) & 0x1U;
546}
547static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
548{
549 return 0x00000001U;
550}
551static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
552{
553 return 0x8000U;
554}
555static inline u32 fifo_pbdma_status_r(u32 i)
556{
557 return 0x00003080U + i*4U;
558}
559static inline u32 fifo_pbdma_status__size_1_v(void)
560{
561 return 0x00000001U;
562}
563static inline u32 fifo_pbdma_status_id_v(u32 r)
564{
565 return (r >> 0U) & 0xfffU;
566}
567static inline u32 fifo_pbdma_status_id_type_v(u32 r)
568{
569 return (r >> 12U) & 0x1U;
570}
571static inline u32 fifo_pbdma_status_id_type_chid_v(void)
572{
573 return 0x00000000U;
574}
575static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
576{
577 return 0x00000001U;
578}
579static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
580{
581 return (r >> 13U) & 0x7U;
582}
583static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
584{
585 return 0x00000001U;
586}
587static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
588{
589 return 0x00000005U;
590}
591static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
592{
593 return 0x00000006U;
594}
595static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
596{
597 return 0x00000007U;
598}
599static inline u32 fifo_pbdma_status_next_id_v(u32 r)
600{
601 return (r >> 16U) & 0xfffU;
602}
603static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
604{
605 return (r >> 28U) & 0x1U;
606}
607static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
608{
609 return 0x00000000U;
610}
611static inline u32 fifo_pbdma_status_chsw_v(u32 r)
612{
613 return (r >> 15U) & 0x1U;
614}
615static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
616{
617 return 0x00000001U;
618}
619#endif
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