diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
commit | f347fde22f1297e4f022600d201780d5ead78114 (patch) | |
tree | 76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/acr/nvgpu_acr.h | |
parent | 8340d234d78a7d0f46c11a584de538148b78b7cb (diff) |
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/acr/nvgpu_acr.h')
-rw-r--r-- | include/nvgpu/acr/nvgpu_acr.h | 192 |
1 files changed, 0 insertions, 192 deletions
diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h deleted file mode 100644 index cdb7bb8..0000000 --- a/include/nvgpu/acr/nvgpu_acr.h +++ /dev/null | |||
@@ -1,192 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_ACR_H | ||
24 | #define NVGPU_ACR_H | ||
25 | |||
26 | #include <nvgpu/falcon.h> | ||
27 | |||
28 | #include "gk20a/mm_gk20a.h" | ||
29 | |||
30 | #include "acr_lsfm.h" | ||
31 | #include "acr_flcnbl.h" | ||
32 | #include "acr_objlsfm.h" | ||
33 | #include "acr_objflcn.h" | ||
34 | |||
35 | struct nvgpu_firmware; | ||
36 | struct gk20a; | ||
37 | struct hs_acr_ops; | ||
38 | struct hs_acr; | ||
39 | struct nvgpu_acr; | ||
40 | |||
41 | #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" | ||
42 | #define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin" | ||
43 | #define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin" | ||
44 | #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" | ||
45 | #define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin" | ||
46 | #define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin" | ||
47 | #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" | ||
48 | #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" | ||
49 | #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" | ||
50 | #define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin" | ||
51 | |||
52 | #define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" | ||
53 | #define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" | ||
54 | #define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" | ||
55 | |||
56 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ | ||
57 | |||
58 | #define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ | ||
59 | |||
60 | #define PMU_SECURE_MODE (0x1) | ||
61 | #define PMU_LSFM_MANAGED (0x2) | ||
62 | |||
63 | struct bin_hdr { | ||
64 | /* 0x10de */ | ||
65 | u32 bin_magic; | ||
66 | /* versioning of bin format */ | ||
67 | u32 bin_ver; | ||
68 | /* Entire image size including this header */ | ||
69 | u32 bin_size; | ||
70 | /* | ||
71 | * Header offset of executable binary metadata, | ||
72 | * start @ offset- 0x100 * | ||
73 | */ | ||
74 | u32 header_offset; | ||
75 | /* | ||
76 | * Start of executable binary data, start @ | ||
77 | * offset- 0x200 | ||
78 | */ | ||
79 | u32 data_offset; | ||
80 | /* Size of executable binary */ | ||
81 | u32 data_size; | ||
82 | }; | ||
83 | |||
84 | struct acr_fw_header { | ||
85 | u32 sig_dbg_offset; | ||
86 | u32 sig_dbg_size; | ||
87 | u32 sig_prod_offset; | ||
88 | u32 sig_prod_size; | ||
89 | u32 patch_loc; | ||
90 | u32 patch_sig; | ||
91 | u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ | ||
92 | u32 hdr_size; /* Size of above header */ | ||
93 | }; | ||
94 | |||
95 | struct wpr_carveout_info { | ||
96 | u64 wpr_base; | ||
97 | u64 nonwpr_base; | ||
98 | u64 size; | ||
99 | }; | ||
100 | |||
101 | /* ACR interfaces */ | ||
102 | |||
103 | struct hs_flcn_bl { | ||
104 | char *bl_fw_name; | ||
105 | struct nvgpu_firmware *hs_bl_fw; | ||
106 | struct hsflcn_bl_desc *hs_bl_desc; | ||
107 | struct bin_hdr *hs_bl_bin_hdr; | ||
108 | struct nvgpu_mem hs_bl_ucode; | ||
109 | }; | ||
110 | |||
111 | struct hs_acr { | ||
112 | u32 acr_type; | ||
113 | |||
114 | /* HS bootloader to validate & load ACR ucode */ | ||
115 | struct hs_flcn_bl acr_hs_bl; | ||
116 | |||
117 | /* ACR ucode */ | ||
118 | char *acr_fw_name; | ||
119 | struct nvgpu_firmware *acr_fw; | ||
120 | struct nvgpu_mem acr_ucode; | ||
121 | |||
122 | union { | ||
123 | struct flcn_bl_dmem_desc bl_dmem_desc; | ||
124 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | ||
125 | }; | ||
126 | |||
127 | void *ptr_bl_dmem_desc; | ||
128 | u32 bl_dmem_desc_size; | ||
129 | |||
130 | union{ | ||
131 | struct flcn_acr_desc *acr_dmem_desc; | ||
132 | struct flcn_acr_desc_v1 *acr_dmem_desc_v1; | ||
133 | }; | ||
134 | |||
135 | /* Falcon used to execute ACR ucode */ | ||
136 | struct nvgpu_falcon *acr_flcn; | ||
137 | |||
138 | int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g, | ||
139 | struct hs_acr *acr_desc, | ||
140 | struct nvgpu_falcon_bl_info *bl_info); | ||
141 | }; | ||
142 | |||
143 | #define ACR_DEFAULT 0U | ||
144 | #define ACR_AHESASC 1U | ||
145 | #define ACR_ASB 2U | ||
146 | |||
147 | struct nvgpu_acr { | ||
148 | struct gk20a *g; | ||
149 | |||
150 | u32 bootstrap_owner; | ||
151 | u32 max_supported_lsfm; | ||
152 | u32 capabilities; | ||
153 | |||
154 | /* | ||
155 | * non-wpr space to hold LSF ucodes, | ||
156 | * ACR does copy ucode from non-wpr to wpr | ||
157 | */ | ||
158 | struct nvgpu_mem ucode_blob; | ||
159 | /* | ||
160 | * Even though this mem_desc wouldn't be used, | ||
161 | * the wpr region needs to be reserved in the | ||
162 | * allocator in dGPU case. | ||
163 | */ | ||
164 | struct nvgpu_mem wpr_dummy; | ||
165 | |||
166 | /* ACR member for different types of ucode */ | ||
167 | /* For older dgpu/tegra ACR cuode */ | ||
168 | struct hs_acr acr; | ||
169 | /* ACR load split feature support */ | ||
170 | struct hs_acr acr_ahesasc; | ||
171 | struct hs_acr acr_asb; | ||
172 | |||
173 | u32 pmu_args; | ||
174 | struct nvgpu_firmware *pmu_fw; | ||
175 | struct nvgpu_firmware *pmu_desc; | ||
176 | |||
177 | int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr); | ||
178 | void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); | ||
179 | int (*alloc_blob_space)(struct gk20a *g, size_t size, | ||
180 | struct nvgpu_mem *mem); | ||
181 | int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr, | ||
182 | struct hs_acr *acr_desc, bool is_recovery); | ||
183 | int (*acr_fill_bl_dmem_desc)(struct gk20a *g, | ||
184 | struct nvgpu_acr *acr, struct hs_acr *acr_desc, | ||
185 | u32 *acr_ucode_header); | ||
186 | int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr, | ||
187 | struct hs_acr *acr_desc); | ||
188 | |||
189 | void (*remove_support)(struct nvgpu_acr *acr); | ||
190 | }; | ||
191 | #endif /* NVGPU_ACR_H */ | ||
192 | |||