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authorJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
commit01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch)
tree4ef34501728a087be24f4ba0af90f91486bf780b /include/gk20a/hw_bus_gk20a.h
parent306a03d18b305e4e573be3b2931978fa10679eb9 (diff)
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/gk20a/hw_bus_gk20a.h')
-rw-r--r--include/gk20a/hw_bus_gk20a.h171
1 files changed, 171 insertions, 0 deletions
diff --git a/include/gk20a/hw_bus_gk20a.h b/include/gk20a/hw_bus_gk20a.h
new file mode 100644
index 0000000..d3bb9e9
--- /dev/null
+++ b/include/gk20a/hw_bus_gk20a.h
@@ -0,0 +1,171 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_bus_gk20a_h_
57#define _hw_bus_gk20a_h_
58
59static inline u32 bus_bar0_window_r(void)
60{
61 return 0x00001700U;
62}
63static inline u32 bus_bar0_window_base_f(u32 v)
64{
65 return (v & 0xffffffU) << 0U;
66}
67static inline u32 bus_bar0_window_target_vid_mem_f(void)
68{
69 return 0x0U;
70}
71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
72{
73 return 0x2000000U;
74}
75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
76{
77 return 0x3000000U;
78}
79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
80{
81 return 0x00000010U;
82}
83static inline u32 bus_bar1_block_r(void)
84{
85 return 0x00001704U;
86}
87static inline u32 bus_bar1_block_ptr_f(u32 v)
88{
89 return (v & 0xfffffffU) << 0U;
90}
91static inline u32 bus_bar1_block_target_vid_mem_f(void)
92{
93 return 0x0U;
94}
95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
96{
97 return 0x20000000U;
98}
99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
100{
101 return 0x30000000U;
102}
103static inline u32 bus_bar1_block_mode_virtual_f(void)
104{
105 return 0x80000000U;
106}
107static inline u32 bus_bar2_block_r(void)
108{
109 return 0x00001714U;
110}
111static inline u32 bus_bar2_block_ptr_f(u32 v)
112{
113 return (v & 0xfffffffU) << 0U;
114}
115static inline u32 bus_bar2_block_target_vid_mem_f(void)
116{
117 return 0x0U;
118}
119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
120{
121 return 0x20000000U;
122}
123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
124{
125 return 0x30000000U;
126}
127static inline u32 bus_bar2_block_mode_virtual_f(void)
128{
129 return 0x80000000U;
130}
131static inline u32 bus_bar1_block_ptr_shift_v(void)
132{
133 return 0x0000000cU;
134}
135static inline u32 bus_bar2_block_ptr_shift_v(void)
136{
137 return 0x0000000cU;
138}
139static inline u32 bus_intr_0_r(void)
140{
141 return 0x00001100U;
142}
143static inline u32 bus_intr_0_pri_squash_m(void)
144{
145 return 0x1U << 1U;
146}
147static inline u32 bus_intr_0_pri_fecserr_m(void)
148{
149 return 0x1U << 2U;
150}
151static inline u32 bus_intr_0_pri_timeout_m(void)
152{
153 return 0x1U << 3U;
154}
155static inline u32 bus_intr_en_0_r(void)
156{
157 return 0x00001140U;
158}
159static inline u32 bus_intr_en_0_pri_squash_m(void)
160{
161 return 0x1U << 1U;
162}
163static inline u32 bus_intr_en_0_pri_fecserr_m(void)
164{
165 return 0x1U << 2U;
166}
167static inline u32 bus_intr_en_0_pri_timeout_m(void)
168{
169 return 0x1U << 3U;
170}
171#endif