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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/ctrl
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/ctrl')
-rw-r--r--include/ctrl/ctrlboardobj.h89
-rw-r--r--include/ctrl/ctrlclk.h212
-rw-r--r--include/ctrl/ctrlclkavfs.h112
-rw-r--r--include/ctrl/ctrlperf.h103
-rw-r--r--include/ctrl/ctrlpmgr.h98
-rw-r--r--include/ctrl/ctrltherm.h33
-rw-r--r--include/ctrl/ctrlvolt.h143
7 files changed, 0 insertions, 790 deletions
diff --git a/include/ctrl/ctrlboardobj.h b/include/ctrl/ctrlboardobj.h
deleted file mode 100644
index 8f57e88..0000000
--- a/include/ctrl/ctrlboardobj.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_CTRLBOARDOBJ_H
24#define NVGPU_CTRLBOARDOBJ_H
25
26struct ctrl_boardobj {
27 u8 type;
28};
29
30#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U
31#define CTRL_BOARDOBJGRP_TYPE_E32 0x01U
32#define CTRL_BOARDOBJGRP_TYPE_E255 0x02U
33
34#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U
35
36#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U
37
38#define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \
39 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
40
41#define CTRL_BOARDOBJ_IDX_INVALID 255U
42
43#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U
44
45#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \
46 ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
47
48#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \
49 ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
50
51#define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \
52 (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U)
53
54
55#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U
56#define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \
57 (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \
58 CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)
59
60struct ctrl_boardobjgrp_mask {
61 u32 data[1];
62};
63
64struct ctrl_boardobjgrp_mask_e32 {
65 struct ctrl_boardobjgrp_mask super;
66};
67
68struct ctrl_boardobjgrp_mask_e255 {
69 struct ctrl_boardobjgrp_mask super;
70 u32 data_e255[7];
71};
72
73struct ctrl_boardobjgrp_super {
74 struct ctrl_boardobjgrp_mask obj_mask;
75};
76
77struct ctrl_boardobjgrp_e32 {
78 struct ctrl_boardobjgrp_mask_e32 obj_mask;
79};
80
81struct CTRL_boardobjgrp_e255 {
82 struct ctrl_boardobjgrp_mask_e255 obj_mask;
83};
84
85struct ctrl_boardobjgrp {
86 u32 obj_mask;
87};
88
89#endif /* NVGPU_CTRLBOARDOBJ_H */
diff --git a/include/ctrl/ctrlclk.h b/include/ctrl/ctrlclk.h
deleted file mode 100644
index fbd5677..0000000
--- a/include/ctrl/ctrlclk.h
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLCLK_H
25#define NVGPU_CTRLCLK_H
26
27#include "ctrlboardobj.h"
28#include "ctrlclkavfs.h"
29#include "ctrlvolt.h"
30
31#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4
32
33/* valid clock domain values */
34#define CTRL_CLK_DOMAIN_MCLK (0x00000010)
35#define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020)
36#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040)
37#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000)
38#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000)
39#define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000)
40#define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000)
41#define CTRL_CLK_DOMAIN_PWRCLK (0x00080000)
42#define CTRL_CLK_DOMAIN_NVDCLK (0x00100000)
43#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000)
44
45#define CTRL_CLK_DOMAIN_GPCCLK (0x00000001)
46#define CTRL_CLK_DOMAIN_XBARCLK (0x00000002)
47#define CTRL_CLK_DOMAIN_SYSCLK (0x00000004)
48#define CTRL_CLK_DOMAIN_HUBCLK (0x00000008)
49
50#define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01
51#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02
52#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03
53#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04
54#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05
55#define CTRL_CLK_CLK_DOMAIN_TYPE_30_PROG 0x06
56#define CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER 0x07
57#define CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE 0x08
58#define CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG 0x09
59
60#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF
61#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF
62
63#define CTRL_CLK_CLK_PROG_TYPE_1X 0x01
64#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02
65#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03
66#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04
67#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255
68
69/*!
70 * Enumeration of CLK_PROG source types.
71 */
72#define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00
73#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01
74#define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02
75#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255
76
77#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4
78#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6
79
80#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255
81
82#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x01
83#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x02
84#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255
85
86struct ctrl_clk_clk_prog_1x_master_source_fll {
87 u32 base_vfsmooth_volt_uv;
88 u32 max_vf_ramprate;
89 u32 max_freq_stepsize_mhz;
90};
91
92union ctrl_clk_clk_prog_1x_master_source_data {
93 struct ctrl_clk_clk_prog_1x_master_source_fll fll;
94};
95
96struct ctrl_clk_clk_vf_point_info_freq {
97 u16 freq_mhz;
98};
99
100struct ctrl_clk_clk_vf_point_info_volt {
101 u32 sourceVoltageuV;
102 u8 vfGainVfeEquIdx;
103 u8 clkDomainIdx;
104};
105
106struct ctrl_clk_clk_prog_1x_master_vf_entry {
107 u8 vfe_idx;
108 u8 gain_vfe_idx;
109 u8 vf_point_idx_first;
110 u8 vf_point_idx_last;
111};
112
113struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
114 u8 clk_dom_idx;
115 u8 ratio;
116};
117
118struct ctrl_clk_clk_prog_1x_master_table_slave_entry {
119 u8 clk_dom_idx;
120 u16 freq_mhz;
121};
122
123struct ctrl_clk_clk_prog_1x_source_pll {
124 u8 pll_idx;
125 u8 freq_step_size_mhz;
126};
127
128union ctrl_clk_freq_delta_data {
129 s32 delta_khz;
130 s16 delta_percent;
131};
132struct ctrl_clk_freq_delta {
133 u8 type;
134 union ctrl_clk_freq_delta_data data;
135};
136
137struct ctrl_clk_clk_delta {
138 struct ctrl_clk_freq_delta freq_delta;
139 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
140};
141
142struct ctrl_clk_vin_v10 {
143 u32 slope;
144 u32 intercept;
145};
146
147struct ctrl_clk_vin_v20 {
148 s8 offset;
149 s8 gain;
150};
151
152union ctrl_clk_vin_data_v20 {
153 struct ctrl_clk_vin_v10 cal_v10;
154 struct ctrl_clk_vin_v20 cal_v20;
155};
156
157struct ctrl_clk_vin_device_info_data_v10 {
158 struct ctrl_clk_vin_v10 vin_cal;
159};
160
161struct ctrl_clk_vin_device_info_data_v20 {
162 u8 cal_type;
163 union ctrl_clk_vin_data_v20 vin_cal;
164};
165
166union ctrl_clk_clk_prog_1x_source_data {
167 struct ctrl_clk_clk_prog_1x_source_pll pll;
168};
169
170struct ctrl_clk_vf_pair {
171 u16 freq_mhz;
172 u32 voltage_uv;
173};
174
175struct ctrl_clk_clk_domain_list_item {
176 u32 clk_domain;
177 u32 clk_freq_khz;
178 u32 clk_flags;
179 u8 current_regime_id;
180 u8 target_regime_id;
181};
182
183struct ctrl_clk_clk_domain_list_item_v1 {
184 u32 clk_domain;
185 u32 clk_freq_khz;
186 u8 regime_id;
187 u8 source;
188};
189
190struct ctrl_clk_clk_domain_list {
191 u8 num_domains;
192 struct ctrl_clk_clk_domain_list_item_v1
193 clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
194};
195
196#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \
197 ((pvfpair)->freq_mhz)
198
199#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \
200 ((pvfpair)->voltage_uv)
201
202#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
203 (((pvfpair)->freq_mhz) = (_freqmhz))
204
205#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
206 (((pvfpair)->freq_mhz) = (_freqmhz))
207
208
209#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \
210 (((pvfpair)->voltage_uv) = (_voltageuv))
211
212#endif /* NVGPU_CTRLCLK_H */
diff --git a/include/ctrl/ctrlclkavfs.h b/include/ctrl/ctrlclkavfs.h
deleted file mode 100644
index 676ae7e..0000000
--- a/include/ctrl/ctrlclkavfs.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_CTRLCLKAVFS_H
24#define NVGPU_CTRLCLKAVFS_H
25
26#include "ctrlboardobj.h"
27/*!
28 * Valid global VIN ID values
29 */
30#define CTRL_CLK_VIN_ID_SYS 0x00000000
31#define CTRL_CLK_VIN_ID_LTC 0x00000001
32#define CTRL_CLK_VIN_ID_XBAR 0x00000002
33#define CTRL_CLK_VIN_ID_GPC0 0x00000003
34#define CTRL_CLK_VIN_ID_GPC1 0x00000004
35#define CTRL_CLK_VIN_ID_GPC2 0x00000005
36#define CTRL_CLK_VIN_ID_GPC3 0x00000006
37#define CTRL_CLK_VIN_ID_GPC4 0x00000007
38#define CTRL_CLK_VIN_ID_GPC5 0x00000008
39#define CTRL_CLK_VIN_ID_GPCS 0x00000009
40#define CTRL_CLK_VIN_ID_SRAM 0x0000000A
41#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF
42
43#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000
44#define CTRL_CLK_VIN_TYPE_V10 0x00000001
45#define CTRL_CLK_VIN_TYPE_V20 0x00000002
46
47/*!
48 * Various types of VIN calibration that the GPU can support
49 */
50#define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000)
51#define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001)
52
53/*!
54 * Mask of all GPC VIN IDs supported by RM
55 */
56#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \
57 BIT(CTRL_CLK_VIN_ID_GPC1) | \
58 BIT(CTRL_CLK_VIN_ID_GPC2) | \
59 BIT(CTRL_CLK_VIN_ID_GPC3) | \
60 BIT(CTRL_CLK_VIN_ID_GPC4) | \
61 BIT(CTRL_CLK_VIN_ID_GPC5))
62#define CTRL_CLK_LUT_NUM_ENTRIES_MAX (128)
63#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128)
64#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100)
65#define CTRL_CLK_VIN_STEP_SIZE_UV (10000)
66#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000)
67#define CTRL_CLK_FLL_TYPE_DISABLED 0
68
69#define CTRL_CLK_FLL_ID_SYS (0x00000000)
70#define CTRL_CLK_FLL_ID_LTC (0x00000001)
71#define CTRL_CLK_FLL_ID_XBAR (0x00000002)
72#define CTRL_CLK_FLL_ID_GPC0 (0x00000003)
73#define CTRL_CLK_FLL_ID_GPC1 (0x00000004)
74#define CTRL_CLK_FLL_ID_GPC2 (0x00000005)
75#define CTRL_CLK_FLL_ID_GPC3 (0x00000006)
76#define CTRL_CLK_FLL_ID_GPC4 (0x00000007)
77#define CTRL_CLK_FLL_ID_GPC5 (0x00000008)
78#define CTRL_CLK_FLL_ID_GPCS (0x00000009)
79#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF)
80#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000)
81
82/*!
83 * Mask of all GPC FLL IDs supported by RM
84 */
85#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \
86 BIT(CTRL_CLK_FLL_ID_GPC1) | \
87 BIT(CTRL_CLK_FLL_ID_GPC2) | \
88 BIT(CTRL_CLK_FLL_ID_GPC3) | \
89 BIT(CTRL_CLK_FLL_ID_GPC4) | \
90 BIT(CTRL_CLK_FLL_ID_GPC5))
91/*!
92 * Mask of all FLL IDs supported by Nvgpu driver
93 */
94#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \
95 BIT(CTRL_CLK_FLL_ID_LTC) | \
96 BIT(CTRL_CLK_FLL_ID_XBAR) | \
97 BIT(CTRL_CLK_FLL_ID_GPC0) | \
98 BIT(CTRL_CLK_FLL_ID_GPC1) | \
99 BIT(CTRL_CLK_FLL_ID_GPC2) | \
100 BIT(CTRL_CLK_FLL_ID_GPC3) | \
101 BIT(CTRL_CLK_FLL_ID_GPC4) | \
102 BIT(CTRL_CLK_FLL_ID_GPC5) | \
103 BIT(CTRL_CLK_FLL_ID_GPCS))
104
105#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000)
106#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001)
107#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002)
108
109#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000)
110#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001)
111#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002)
112#endif /* NVGPU_CTRLCLKAVFS_H */
diff --git a/include/ctrl/ctrlperf.h b/include/ctrl/ctrlperf.h
deleted file mode 100644
index 2928cad..0000000
--- a/include/ctrl/ctrlperf.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLPERF_H
25#define NVGPU_CTRLPERF_H
26
27struct ctrl_perf_volt_rail_list_item {
28 u8 volt_domain;
29 u32 voltage_uv;
30 u32 voltage_min_noise_unaware_uv;
31};
32
33struct ctrl_perf_volt_rail_list {
34 u8 num_rails;
35 struct ctrl_perf_volt_rail_list_item
36 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
37};
38
39union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
40 int signed_value;
41 u32 unsigned_value;
42};
43
44struct ctrl_perf_vfe_var_single_sensed_fuse_value {
45 bool b_signed;
46 union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
47};
48
49struct ctrl_bios_vfield_register_segment_super {
50 u8 low_bit;
51 u8 high_bit;
52};
53
54struct ctrl_bios_vfield_register_segment_reg {
55 struct ctrl_bios_vfield_register_segment_super super;
56 u32 addr;
57};
58
59struct ctrl_bios_vfield_register_segment_index_reg {
60 struct ctrl_bios_vfield_register_segment_super super;
61 u32 addr;
62 u32 reg_index;
63 u32 index;
64};
65
66union ctrl_bios_vfield_register_segment_data {
67 struct ctrl_bios_vfield_register_segment_reg reg;
68 struct ctrl_bios_vfield_register_segment_index_reg index_reg;
69};
70
71struct ctrl_bios_vfield_register_segment {
72 u8 type;
73 union ctrl_bios_vfield_register_segment_data data;
74};
75
76#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1
77
78struct ctrl_perf_vfe_var_single_sensed_fuse_info {
79 u8 segment_count;
80 struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
81};
82
83struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
84 u32 fuse_val_override;
85 u8 b_fuse_regkey_override;
86};
87
88struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
89 struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
90 u32 fuse_val_default;
91 u32 hw_correction_scale;
92 int hw_correction_offset;
93 u8 v_field_id;
94};
95
96struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
97 struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
98 u8 ver_expected;
99 bool b_ver_check;
100 bool b_use_default_on_ver_check_fail;
101 u8 v_field_id_ver;
102};
103#endif /* NVGPU_CTRLPERF_H */
diff --git a/include/ctrl/ctrlpmgr.h b/include/ctrl/ctrlpmgr.h
deleted file mode 100644
index 90f6501..0000000
--- a/include/ctrl/ctrlpmgr.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * Control pmgr state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLPMGR_H
25#define NVGPU_CTRLPMGR_H
26
27#include "ctrlboardobj.h"
28
29/* valid power domain values */
30#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32U
31#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06U
32
33#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4EU
34
35#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFFU
36#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08U
37
38#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30U
39#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04U
40#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0CU
41
42#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8U
43#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08U
44#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFFU
45#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFEU
46#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFFU)
47
48struct ctrl_pmgr_pwr_device_info_rshunt {
49 bool use_fxp8_8;
50 u16 rshunt_value;
51};
52
53struct ctrl_pmgr_pwr_policy_info_integral {
54 u8 past_sample_count;
55 u8 next_sample_count;
56 u16 ratio_limit_min;
57 u16 ratio_limit_max;
58};
59
60enum ctrl_pmgr_pwr_policy_filter_type {
61 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0,
62 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK,
63 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE,
64 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR
65};
66
67struct ctrl_pmgr_pwr_policy_filter_param_block {
68 u32 block_size;
69};
70
71struct ctrl_pmgr_pwr_policy_filter_param_moving_average {
72 u32 window_size;
73};
74
75struct ctrl_pmgr_pwr_policy_filter_param_iir {
76 u32 divisor;
77};
78
79union ctrl_pmgr_pwr_policy_filter_param {
80 struct ctrl_pmgr_pwr_policy_filter_param_block block;
81 struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg;
82 struct ctrl_pmgr_pwr_policy_filter_param_iir iir;
83};
84
85struct ctrl_pmgr_pwr_policy_limit_input {
86 u8 pwr_policy_idx;
87 u32 limit_value;
88};
89
90struct ctrl_pmgr_pwr_policy_limit_arbitration {
91 bool b_arb_max;
92 u8 num_inputs;
93 u32 output;
94 struct ctrl_pmgr_pwr_policy_limit_input
95 inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS];
96};
97
98#endif /* NVGPU_CTRLPMGR_H */
diff --git a/include/ctrl/ctrltherm.h b/include/ctrl/ctrltherm.h
deleted file mode 100644
index 27af7b0..0000000
--- a/include/ctrl/ctrltherm.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Control thermal infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLTHERM_H
25#define NVGPU_CTRLTHERM_H
26
27#include "ctrlboardobj.h"
28
29#define CTRL_THERMAL_THERM_DEVICE_CLASS_GPU 0x01
30
31#define CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE 0x01
32
33#endif /* NVGPU_CTRLTHERM_H */
diff --git a/include/ctrl/ctrlvolt.h b/include/ctrl/ctrlvolt.h
deleted file mode 100644
index 84994eb..0000000
--- a/include/ctrl/ctrlvolt.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLVOLT_H
25#define NVGPU_CTRLVOLT_H
26
27#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
28 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
29
30#include "ctrlperf.h"
31#include "ctrlboardobj.h"
32
33#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
34#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U)
35#define CTRL_VOLT_DOMAIN_INVALID 0x00U
36#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
37#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
38#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
39
40/*
41 * Macros for Voltage Domain HAL.
42 */
43#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
44#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U
45
46/*
47 * Macros for Voltage Domains.
48 */
49#define CTRL_VOLT_DOMAIN_INVALID 0x00U
50#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
51#define CTRL_VOLT_DOMAIN_SRAM 0x02U
52
53/*!
54 * Special value corresponding to an invalid Voltage Rail Index.
55 */
56#define CTRL_VOLT_RAIL_INDEX_INVALID \
57 CTRL_BOARDOBJ_IDX_INVALID
58
59/*!
60 * Special value corresponding to an invalid Voltage Device Index.
61 */
62#define CTRL_VOLT_DEVICE_INDEX_INVALID \
63 CTRL_BOARDOBJ_IDX_INVALID
64
65/*!
66 * Special value corresponding to an invalid Voltage Policy Index.
67 */
68#define CTRL_VOLT_POLICY_INDEX_INVALID \
69 CTRL_BOARDOBJ_IDX_INVALID
70
71enum nv_pmu_pmgr_pwm_source {
72 NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
73 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
74 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
75 NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
76 NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
77};
78
79/*!
80 * Macros for Voltage Device Types.
81 */
82#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
83#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
84
85/*
86 * Macros for Volt Device Operation types.
87 */
88#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
89#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
90#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U
91#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U
92#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
93
94/*!
95 * Macros for Voltage Domains.
96 */
97#define CTRL_VOLT_DOMAIN_INVALID 0x00U
98#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
99#define CTRL_VOLT_DOMAIN_SRAM 0x02U
100
101/*!
102 * Macros for Volt Policy types.
103 *
104 * Virtual VOLT_POLICY types are indexed starting from 0xFF.
105 */
106#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
107#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
108#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
109#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
110#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
111#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
112#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
113
114/*!
115 * Macros for Volt Policy Client types.
116 */
117#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
118#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
119
120struct ctrl_volt_volt_rail_list_item {
121 u8 rail_idx;
122 u32 voltage_uv;
123};
124
125struct ctrl_volt_volt_rail_list {
126 u8 num_rails;
127 struct ctrl_volt_volt_rail_list_item
128 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
129};
130
131struct ctrl_volt_volt_rail_list_item_v1 {
132 u8 rail_idx;
133 u32 voltage_uv;
134 u32 voltage_min_noise_unaware_uv;
135};
136
137struct ctrl_volt_volt_rail_list_v1 {
138 u8 num_rails;
139 struct ctrl_volt_volt_rail_list_item_v1
140 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
141};
142
143#endif /* NVGPU_CTRLVOLT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 06:17:48 -0400