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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/clk/clk_mclk.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/clk/clk_mclk.h')
-rw-r--r--include/clk/clk_mclk.h60
1 files changed, 0 insertions, 60 deletions
diff --git a/include/clk/clk_mclk.h b/include/clk/clk_mclk.h
deleted file mode 100644
index 47c81d1..0000000
--- a/include/clk/clk_mclk.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_CLK_MCLK_H
24#define NVGPU_CLK_MCLK_H
25
26#include <nvgpu/lock.h>
27
28#define GP106_MCLK_LOW_SPEED 0U
29#define GP106_MCLK_MID_SPEED 1U
30#define GP106_MCLK_HIGH_SPEED 2U
31#define GP106_MCLK_NUM_SPEED 3U
32
33enum gk20a_mclk_speed {
34 gk20a_mclk_low_speed,
35 gk20a_mclk_mid_speed,
36 gk20a_mclk_high_speed,
37};
38
39struct clk_mclk_state {
40 u32 speed;
41 struct nvgpu_mutex mclk_lock;
42 struct nvgpu_mutex data_lock;
43
44 u16 p5_min;
45 u16 p0_min;
46
47 void *vreg_buf;
48 bool init;
49
50#ifdef CONFIG_DEBUG_FS
51 s64 switch_max;
52 s64 switch_min;
53 u64 switch_num;
54 s64 switch_avg;
55 s64 switch_std;
56 bool debugfs_set;
57#endif
58};
59
60#endif /* NVGPU_CLK_MCLK_H */