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authorJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2023-06-28 18:24:25 -0400
commit01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch)
tree4ef34501728a087be24f4ba0af90f91486bf780b /include/boardobj
parent306a03d18b305e4e573be3b2931978fa10679eb9 (diff)
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time being. Only a couple structs are required, so it should be fairly easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/boardobj')
-rw-r--r--include/boardobj/boardobj.c102
-rw-r--r--include/boardobj/boardobj.h104
-rw-r--r--include/boardobj/boardobjgrp.c1046
-rw-r--r--include/boardobj/boardobjgrp.h441
-rw-r--r--include/boardobj/boardobjgrp_e255.c91
-rw-r--r--include/boardobj/boardobjgrp_e255.h51
-rw-r--r--include/boardobj/boardobjgrp_e32.c89
-rw-r--r--include/boardobj/boardobjgrp_e32.h66
-rw-r--r--include/boardobj/boardobjgrpmask.c411
-rw-r--r--include/boardobj/boardobjgrpmask.h119
10 files changed, 2520 insertions, 0 deletions
diff --git a/include/boardobj/boardobj.c b/include/boardobj/boardobj.c
new file mode 100644
index 0000000..2044b5b
--- /dev/null
+++ b/include/boardobj/boardobj.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/kmem.h>
24#include <nvgpu/gk20a.h>
25
26#include "boardobj.h"
27#include "ctrl/ctrlboardobj.h"
28
29int boardobj_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
30 u16 size, void *args)
31{
32 struct boardobj *pboardobj = NULL;
33 struct boardobj *devtmp = (struct boardobj *)args;
34
35 nvgpu_log_info(g, " ");
36
37 if (devtmp == NULL) {
38 return -EINVAL;
39 }
40
41 if (*ppboardobj == NULL) {
42 *ppboardobj = nvgpu_kzalloc(g, size);
43 if (*ppboardobj == NULL) {
44 return -ENOMEM;
45 }
46 (*ppboardobj)->allocated = true;
47 }
48
49 pboardobj = *ppboardobj;
50 pboardobj->g = g;
51 pboardobj->type = devtmp->type;
52 pboardobj->idx = CTRL_BOARDOBJ_IDX_INVALID;
53 pboardobj->type_mask = BIT(pboardobj->type) | devtmp->type_mask;
54
55 pboardobj->implements = boardobj_implements_super;
56 pboardobj->destruct = boardobj_destruct_super;
57 pboardobj->pmudatainit = boardobj_pmudatainit_super;
58
59 nvgpu_list_add(&pboardobj->node, &g->boardobj_head);
60
61 return 0;
62}
63
64int boardobj_destruct_super(struct boardobj *pboardobj)
65{
66 struct gk20a *g = pboardobj->g;
67
68 nvgpu_log_info(g, " ");
69 if (pboardobj == NULL) {
70 return -EINVAL;
71 }
72
73 nvgpu_list_del(&pboardobj->node);
74 if (pboardobj->allocated) {
75 nvgpu_kfree(pboardobj->g, pboardobj);
76 }
77
78 return 0;
79}
80
81bool boardobj_implements_super(struct gk20a *g, struct boardobj *pboardobj,
82 u8 type)
83{
84 nvgpu_log_info(g, " ");
85
86 return (0 != (pboardobj->type_mask & BIT(type)));
87}
88
89int boardobj_pmudatainit_super(struct gk20a *g, struct boardobj *pboardobj,
90 struct nv_pmu_boardobj *pmudata)
91{
92 nvgpu_log_info(g, " ");
93 if (pboardobj == NULL) {
94 return -EINVAL;
95 }
96 if (pmudata == NULL) {
97 return -EINVAL;
98 }
99 pmudata->type = pboardobj->type;
100 nvgpu_log_info(g, " Done");
101 return 0;
102}
diff --git a/include/boardobj/boardobj.h b/include/boardobj/boardobj.h
new file mode 100644
index 0000000..b1be9bd
--- /dev/null
+++ b/include/boardobj/boardobj.h
@@ -0,0 +1,104 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_BOARDOBJ_H
24#define NVGPU_BOARDOBJ_H
25
26#include <nvgpu/list.h>
27#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
28
29#include "ctrl/ctrlboardobj.h"
30
31struct boardobj;
32struct nvgpu_list_node;
33
34/*
35* check whether the specified BOARDOBJ object implements the queried
36* type/class enumeration.
37*/
38typedef bool boardobj_implements(struct gk20a *g, struct boardobj *pboardobj,
39 u8 type);
40
41/*
42* Fills out the appropriate the nv_pmu_xxxx_device_desc_<xyz> driver->PMU
43* description structure, describing this BOARDOBJ board device to the PMU.
44*
45*/
46typedef int boardobj_pmudatainit(struct gk20a *g, struct boardobj *pboardobj,
47 struct nv_pmu_boardobj *pmudata);
48
49/*
50* Constructor for the base Board Object. Called by each device-specific
51* implementation of the BOARDOBJ interface to initialize the board object.
52*/
53typedef int boardobj_construct(struct gk20a *g, struct boardobj **pboardobj,
54 u16 size, void *args);
55
56/*
57* Destructor for the base board object. Called by each device-Specific
58* implementation of the BOARDOBJ interface to destroy the board object.
59* This has to be explicitly set by each device that extends from the
60* board object.
61*/
62typedef int boardobj_destruct(struct boardobj *pboardobj);
63
64/*
65* Base Class for all physical or logical device on the PCB.
66* Contains fields common to all devices on the board. Specific types of
67* devices may extend this object adding any details specific to that
68* device or device-type.
69*/
70
71struct boardobj {
72 struct gk20a *g;
73
74 u8 type; /*type of the device*/
75 u8 idx; /*index of boardobj within in its group*/
76 /* true if allocated in constructor. destructor should free */
77 u8 allocated;
78 u32 type_mask; /*mask of types this boardobjimplements*/
79 boardobj_implements *implements;
80 boardobj_destruct *destruct;
81 /*
82 * Access interface apis which will be overridden by the devices
83 * that inherit from BOARDOBJ
84 */
85 boardobj_pmudatainit *pmudatainit;
86 struct nvgpu_list_node node;
87};
88
89boardobj_construct boardobj_construct_super;
90boardobj_destruct boardobj_destruct_super;
91boardobj_implements boardobj_implements_super;
92boardobj_pmudatainit boardobj_pmudatainit_super;
93
94#define BOARDOBJ_GET_TYPE(pobj) (((struct boardobj *)(pobj))->type)
95#define BOARDOBJ_GET_IDX(pobj) (((struct boardobj *)(pobj))->idx)
96
97static inline struct boardobj *
98boardobj_from_node(struct nvgpu_list_node *node)
99{
100 return (struct boardobj *)
101 ((uintptr_t)node - offsetof(struct boardobj, node));
102};
103
104#endif /* NVGPU_BOARDOBJ_H */
diff --git a/include/boardobj/boardobjgrp.c b/include/boardobj/boardobjgrp.c
new file mode 100644
index 0000000..6832070
--- /dev/null
+++ b/include/boardobj/boardobjgrp.c
@@ -0,0 +1,1046 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#include <nvgpu/bug.h>
23#include <nvgpu/gk20a.h>
24
25#include "boardobjgrp.h"
26#include "ctrl/ctrlboardobj.h"
27#include "boardobj.h"
28
29static boardobjgrp_objinsert boardobjgrp_objinsert_final;
30static boardobjgrp_objgetbyidx boardobjgrp_objgetbyidx_final;
31static boardobjgrp_objgetnext boardobjgrp_objgetnext_final;
32static boardobjgrp_objremoveanddestroy boardobjgrp_objremoveanddestroy_final;
33static boardobjgrp_pmudatainstget boardobjgrp_pmudatainstget_stub;
34static boardobjgrp_pmustatusinstget boardobjgrp_pmustatusinstget_stub;
35static int boardobjgrp_pmucmdsend(struct gk20a *g,
36 struct boardobjgrp *pboardobjgrp,
37 struct boardobjgrp_pmu_cmd *pcmd);
38static int boardobjgrp_pmucmdsend_rpc(struct gk20a *g,
39 struct boardobjgrp *pboardobjgrp,
40 struct boardobjgrp_pmu_cmd *pcmd,
41 bool copy_out);
42struct boardobjgrp_pmucmdhandler_params {
43 /* Pointer to the BOARDOBJGRP associated with this CMD */
44 struct boardobjgrp *pboardobjgrp;
45 /* Pointer to structure representing this NV_PMU_BOARDOBJ_CMD_GRP */
46 struct boardobjgrp_pmu_cmd *pcmd;
47 /* Boolean indicating whether the PMU successfully handled the CMD */
48 u32 success;
49};
50
51int boardobjgrp_construct_super(struct gk20a *g,
52 struct boardobjgrp *pboardobjgrp)
53{
54 nvgpu_log_info(g, " ");
55
56 if (pboardobjgrp == NULL) {
57 return -EINVAL;
58 }
59
60 if (pboardobjgrp->ppobjects == NULL) {
61 return -EINVAL;
62 }
63
64 if (pboardobjgrp->mask == NULL) {
65 return -EINVAL;
66 }
67
68 pboardobjgrp->g = g;
69 pboardobjgrp->objmask = 0;
70
71 pboardobjgrp->classid = 0;
72 pboardobjgrp->pmu.unitid = BOARDOBJGRP_UNIT_ID_INVALID;
73 pboardobjgrp->pmu.classid = BOARDOBJGRP_GRP_CLASS_ID_INVALID;
74 pboardobjgrp->pmu.bset = false;
75 pboardobjgrp->pmu.rpc_func_id = BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID;
76 pboardobjgrp->pmu.set.id = BOARDOBJGRP_GRP_CMD_ID_INVALID;
77 pboardobjgrp->pmu.getstatus.id = BOARDOBJGRP_GRP_CMD_ID_INVALID;
78
79 /* Initialize basic interfaces */
80 pboardobjgrp->destruct = boardobjgrp_destruct_super;
81 pboardobjgrp->objinsert = boardobjgrp_objinsert_final;
82 pboardobjgrp->objgetbyidx = boardobjgrp_objgetbyidx_final;
83 pboardobjgrp->objgetnext = boardobjgrp_objgetnext_final;
84 pboardobjgrp->objremoveanddestroy =
85 boardobjgrp_objremoveanddestroy_final;
86
87 pboardobjgrp->pmuinithandle = boardobjgrp_pmuinithandle_impl;
88 pboardobjgrp->pmuhdrdatainit = boardobjgrp_pmuhdrdatainit_super;
89 pboardobjgrp->pmudatainit = boardobjgrp_pmudatainit_super;
90 pboardobjgrp->pmuset =
91 g->ops.pmu_ver.boardobj.boardobjgrp_pmuset_impl;
92 pboardobjgrp->pmugetstatus =
93 g->ops.pmu_ver.boardobj.boardobjgrp_pmugetstatus_impl;
94
95 pboardobjgrp->pmudatainstget = boardobjgrp_pmudatainstget_stub;
96 pboardobjgrp->pmustatusinstget = boardobjgrp_pmustatusinstget_stub;
97
98 pboardobjgrp->objmaxidx = CTRL_BOARDOBJ_IDX_INVALID;
99 pboardobjgrp->bconstructed = true;
100
101 nvgpu_list_add(&pboardobjgrp->node, &g->boardobjgrp_head);
102
103 return 0;
104}
105
106int boardobjgrp_destruct_impl(struct boardobjgrp *pboardobjgrp)
107{
108 struct gk20a *g = pboardobjgrp->g;
109
110 nvgpu_log_info(g, " ");
111
112 if (pboardobjgrp == NULL) {
113 return -EINVAL;
114 }
115
116 if (!pboardobjgrp->bconstructed) {
117 return 0;
118 }
119
120 return pboardobjgrp->destruct(pboardobjgrp);
121}
122
123int boardobjgrp_destruct_super(struct boardobjgrp *pboardobjgrp)
124{
125 struct boardobj *pboardobj;
126 struct gk20a *g = pboardobjgrp->g;
127 int status = 0;
128 int stat;
129 u8 index;
130
131 nvgpu_log_info(g, " ");
132
133 if (pboardobjgrp->mask == NULL) {
134 return -EINVAL;
135 }
136 if (pboardobjgrp->ppobjects == NULL) {
137 return -EINVAL;
138 }
139
140 BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
141 stat = pboardobjgrp->objremoveanddestroy(pboardobjgrp, index);
142 if (status == 0) {
143 status = stat;
144 }
145
146 pboardobjgrp->ppobjects[index] = NULL;
147 pboardobjgrp->objmask &= ~BIT(index);
148 }
149
150 pboardobjgrp->objmask = 0;
151
152 if (pboardobjgrp->objmaxidx != CTRL_BOARDOBJ_IDX_INVALID) {
153 if (status == 0) {
154 status = -EINVAL;
155 }
156
157 WARN_ON(true);
158 }
159
160 /* Destroy the PMU CMD data */
161 stat = boardobjgrp_pmucmd_destroy_impl(g, &pboardobjgrp->pmu.set);
162 if (status == 0) {
163 status = stat;
164 }
165
166 stat = boardobjgrp_pmucmd_destroy_impl(g, &pboardobjgrp->pmu.getstatus);
167 if (status == 0) {
168 status = stat;
169 }
170
171 nvgpu_list_del(&pboardobjgrp->node);
172
173 pboardobjgrp->bconstructed = false;
174
175 return status;
176}
177
178int boardobjgrp_pmucmd_construct_impl(struct gk20a *g, struct boardobjgrp
179 *pboardobjgrp, struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid,
180 u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset, u8 rpc_func_id)
181{
182 nvgpu_log_info(g, " ");
183
184 /* Copy the parameters into the CMD*/
185 cmd->id = id;
186 cmd->msgid = msgid;
187 cmd->hdrsize = (u8) hdrsize;
188 cmd->entrysize = (u8) entrysize;
189 cmd->fbsize = fbsize;
190
191 return 0;
192}
193
194int boardobjgrp_pmucmd_construct_impl_v1(struct gk20a *g, struct boardobjgrp
195 *pboardobjgrp, struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid,
196 u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset, u8 rpc_func_id)
197{
198 nvgpu_log_fn(g, " ");
199
200 /* Copy the parameters into the CMD*/
201 cmd->dmem_buffer_size = ((hdrsize > entrysize) ? hdrsize : entrysize);
202 cmd->super_surface_offset = ss_offset;
203 pboardobjgrp->pmu.rpc_func_id = rpc_func_id;
204 cmd->fbsize = fbsize;
205
206 nvgpu_log_fn(g, "DONE");
207 return 0;
208}
209
210int boardobjgrp_pmucmd_destroy_impl(struct gk20a *g,
211 struct boardobjgrp_pmu_cmd *cmd)
212{
213 struct nvgpu_mem *mem = &cmd->surf.sysmem_desc;
214
215 nvgpu_pmu_surface_free(g, mem);
216 return 0;
217}
218
219int is_boardobjgrp_pmucmd_id_valid_v0(struct gk20a *g,
220 struct boardobjgrp *pboardobjgrp,
221 struct boardobjgrp_pmu_cmd *pcmd)
222{
223 int err = 0;
224
225 if (pcmd->id == BOARDOBJGRP_GRP_CMD_ID_INVALID) {
226 err = -EINVAL;
227 }
228
229 return err;
230}
231
232int is_boardobjgrp_pmucmd_id_valid_v1(struct gk20a *g,
233 struct boardobjgrp *pboardobjgrp,
234 struct boardobjgrp_pmu_cmd *cmd)
235{
236 int err = 0;
237
238 if (pboardobjgrp->pmu.rpc_func_id ==
239 BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID) {
240 err = -EINVAL;
241 }
242
243 return err;
244}
245
246int boardobjgrp_pmucmd_pmuinithandle_impl(struct gk20a *g,
247 struct boardobjgrp *pboardobjgrp,
248 struct boardobjgrp_pmu_cmd *pcmd)
249{
250 int status = 0;
251 struct nvgpu_mem *sysmem_desc = &pcmd->surf.sysmem_desc;
252
253 nvgpu_log_info(g, " ");
254
255 if (g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid(g,
256 pboardobjgrp, pcmd)) {
257 goto boardobjgrp_pmucmd_pmuinithandle_exit;
258 }
259
260 if (!pcmd->fbsize) {
261 goto boardobjgrp_pmucmd_pmuinithandle_exit;
262 }
263
264 nvgpu_pmu_sysmem_surface_alloc(g, sysmem_desc, pcmd->fbsize);
265 /* we only have got sysmem later this will get copied to vidmem
266 surface*/
267 pcmd->surf.vidmem_desc.size = 0;
268
269 pcmd->buf = (struct nv_pmu_boardobjgrp_super *)sysmem_desc->cpu_va;
270
271boardobjgrp_pmucmd_pmuinithandle_exit:
272 return status;
273}
274
275int boardobjgrp_pmuinithandle_impl(struct gk20a *g,
276 struct boardobjgrp *pboardobjgrp)
277{
278 int status = 0;
279
280 nvgpu_log_info(g, " ");
281
282 status = boardobjgrp_pmucmd_pmuinithandle_impl(g, pboardobjgrp,
283 &pboardobjgrp->pmu.set);
284 if (status) {
285 nvgpu_err(g, "failed to init pmu set cmd");
286 goto boardobjgrp_pmuinithandle_exit;
287 }
288
289 status = boardobjgrp_pmucmd_pmuinithandle_impl(g, pboardobjgrp,
290 &pboardobjgrp->pmu.getstatus);
291 if (status) {
292 nvgpu_err(g, "failed to init get status command");
293 goto boardobjgrp_pmuinithandle_exit;
294 }
295
296 /* If the GRP_SET CMD has not been allocated, nothing left to do. */
297 if ((g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid(g,
298 pboardobjgrp, &pboardobjgrp->pmu.set))||
299 (BOARDOBJGRP_IS_EMPTY(pboardobjgrp))) {
300 goto boardobjgrp_pmuinithandle_exit;
301 }
302
303 /* Send the BOARDOBJGRP to the pmu via RM_PMU_BOARDOBJ_CMD_GRP. */
304 status = pboardobjgrp->pmuset(g, pboardobjgrp);
305 if (status) {
306 nvgpu_err(g, "failed to send boardobg grp to PMU");
307 }
308
309boardobjgrp_pmuinithandle_exit:
310 return status;
311}
312
313
314int boardobjgrp_pmuhdrdatainit_super(struct gk20a *g, struct boardobjgrp
315 *pboardobjgrp, struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
316 struct boardobjgrpmask *mask)
317{
318 nvgpu_log_info(g, " ");
319
320 if (pboardobjgrp == NULL) {
321 return -EINVAL;
322 }
323 if (pboardobjgrppmu == NULL) {
324 return -EINVAL;
325 }
326 pboardobjgrppmu->type = pboardobjgrp->type;
327 pboardobjgrppmu->class_id = pboardobjgrp->classid;
328 pboardobjgrppmu->obj_slots = BOARDOBJGRP_PMU_SLOTS_GET(pboardobjgrp);
329 pboardobjgrppmu->flags = 0;
330
331 nvgpu_log_info(g, " Done");
332 return 0;
333}
334
335static int boardobjgrp_pmudatainstget_stub(struct gk20a *g,
336 struct nv_pmu_boardobjgrp *boardobjgrppmu,
337 struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
338{
339 nvgpu_log_info(g, " ");
340 return -EINVAL;
341}
342
343
344static int boardobjgrp_pmustatusinstget_stub(struct gk20a *g,
345 void *pboardobjgrppmu,
346 struct nv_pmu_boardobj_query **ppBoardobjpmustatus, u8 idx)
347{
348 nvgpu_log_info(g, " ");
349 return -EINVAL;
350}
351
352int boardobjgrp_pmudatainit_legacy(struct gk20a *g,
353 struct boardobjgrp *pboardobjgrp,
354 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
355{
356 int status = 0;
357 struct boardobj *pboardobj = NULL;
358 struct nv_pmu_boardobj *ppmudata = NULL;
359 u8 index;
360
361 nvgpu_log_info(g, " ");
362
363 if (pboardobjgrp == NULL) {
364 return -EINVAL;
365 }
366 if (pboardobjgrppmu == NULL) {
367 return -EINVAL;
368 }
369
370 boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
371 pboardobjgrp->objmask);
372
373 BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(32, index, pboardobjgrp->objmask) {
374 /* Obtain pointer to the current instance of the Object from the Group */
375 pboardobj = pboardobjgrp->objgetbyidx(pboardobjgrp, index);
376 if (NULL == pboardobj) {
377 nvgpu_err(g, "could not get object instance");
378 status = -EINVAL;
379 goto boardobjgrppmudatainit_legacy_done;
380 }
381
382 status = pboardobjgrp->pmudatainstget(g,
383 (struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
384 &ppmudata, index);
385 if (status) {
386 nvgpu_err(g, "could not get object instance");
387 goto boardobjgrppmudatainit_legacy_done;
388 }
389
390 /* Initialize the PMU Data */
391 status = pboardobj->pmudatainit(g, pboardobj, ppmudata);
392 if (status) {
393 nvgpu_err(g,
394 "could not parse pmu for device %d", index);
395 goto boardobjgrppmudatainit_legacy_done;
396 }
397 }
398 BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK_END
399
400boardobjgrppmudatainit_legacy_done:
401 nvgpu_log_info(g, " Done");
402 return status;
403}
404
405int boardobjgrp_pmudatainit_super(struct gk20a *g, struct boardobjgrp
406 *pboardobjgrp, struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
407{
408 int status = 0;
409 struct boardobj *pboardobj = NULL;
410 struct nv_pmu_boardobj *ppmudata = NULL;
411 u8 index;
412
413 nvgpu_log_info(g, " ");
414
415 if (pboardobjgrp == NULL) {
416 return -EINVAL;
417 }
418 if (pboardobjgrppmu == NULL) {
419 return -EINVAL;
420 }
421
422 /* Initialize the PMU HDR data.*/
423 status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp, pboardobjgrppmu,
424 pboardobjgrp->mask);
425 if (status) {
426 nvgpu_err(g, "unable to init boardobjgrp pmuhdr data");
427 goto boardobjgrppmudatainit_super_done;
428 }
429
430 BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
431 status = pboardobjgrp->pmudatainstget(g,
432 (struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
433 &ppmudata, index);
434 if (status) {
435 nvgpu_err(g, "could not get object instance");
436 goto boardobjgrppmudatainit_super_done;
437 }
438
439 /* Initialize the PMU Data and send to PMU */
440 status = pboardobj->pmudatainit(g, pboardobj, ppmudata);
441 if (status) {
442 nvgpu_err(g,
443 "could not parse pmu for device %d", index);
444 goto boardobjgrppmudatainit_super_done;
445 }
446 }
447
448boardobjgrppmudatainit_super_done:
449 nvgpu_log_info(g, " Done");
450 return status;
451}
452
453static int check_boardobjgrp_param(struct gk20a *g,
454 struct boardobjgrp *pboardobjgrp)
455{
456 if (pboardobjgrp == NULL) {
457 return -EINVAL;
458 }
459
460 if (!pboardobjgrp->bconstructed) {
461 return -EINVAL;
462 }
463
464 if (pboardobjgrp->pmu.unitid == BOARDOBJGRP_UNIT_ID_INVALID) {
465 return -EINVAL;
466 }
467
468 if (pboardobjgrp->pmu.classid == BOARDOBJGRP_GRP_CLASS_ID_INVALID) {
469 return -EINVAL;
470 }
471
472 /* If no objects in the group, return early */
473 if (BOARDOBJGRP_IS_EMPTY(pboardobjgrp)) {
474 return -EINVAL;
475 }
476
477 return 0;
478}
479
480int boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp)
481{
482 int status = 0;
483 struct boardobjgrp_pmu_cmd *pcmd =
484 (struct boardobjgrp_pmu_cmd *)(&pboardobjgrp->pmu.set);
485
486 nvgpu_log_info(g, " ");
487
488 if (check_boardobjgrp_param(g, pboardobjgrp)) {
489 return -EINVAL;
490 }
491
492 if (pboardobjgrp->pmu.set.id == BOARDOBJGRP_GRP_CMD_ID_INVALID) {
493 return -EINVAL;
494 }
495
496 if ((pcmd->hdrsize == 0) ||
497 (pcmd->entrysize == 0) ||
498 (pcmd->buf == NULL)) {
499 return -EINVAL;
500 }
501
502 /* Initialize PMU buffer with BOARDOBJGRP data. */
503 memset(pcmd->buf, 0x0, pcmd->fbsize);
504 status = pboardobjgrp->pmudatainit(g, pboardobjgrp,
505 pcmd->buf);
506 if (status) {
507 nvgpu_err(g, "could not parse pmu data");
508 goto boardobjgrp_pmuset_exit;
509 }
510
511 /*
512 * Reset the boolean that indicates set status for most recent
513 * instance of BOARDOBJGRP.
514 */
515 pboardobjgrp->pmu.bset = false;
516
517 /*
518 * alloc mem in vidmem & copy constructed pmu boardobjgrp data from
519 * sysmem to vidmem
520 */
521 if (pcmd->surf.vidmem_desc.size == 0) {
522 nvgpu_pmu_vidmem_surface_alloc(g, &pcmd->surf.vidmem_desc,
523 pcmd->fbsize);
524 }
525 nvgpu_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize);
526
527 /* Send the SET PMU CMD to the PMU */
528 status = boardobjgrp_pmucmdsend(g, pboardobjgrp,
529 pcmd);
530 if (status) {
531 nvgpu_err(g, "could not send SET CMD to PMU");
532 goto boardobjgrp_pmuset_exit;
533 }
534
535 pboardobjgrp->pmu.bset = true;
536
537boardobjgrp_pmuset_exit:
538 return status;
539}
540
541int boardobjgrp_pmuset_impl_v1(struct gk20a *g,
542 struct boardobjgrp *pboardobjgrp)
543{
544 struct nvgpu_pmu *pmu = &g->pmu;
545 int status = 0;
546 struct boardobjgrp_pmu_cmd *pcmd =
547 (struct boardobjgrp_pmu_cmd *)(&pboardobjgrp->pmu.set);
548
549 nvgpu_log_info(g, " ");
550
551 if (check_boardobjgrp_param(g, pboardobjgrp)) {
552 return -EINVAL;
553 }
554
555 if ((pcmd->buf == NULL) &&
556 (pboardobjgrp->pmu.rpc_func_id ==
557 BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID)) {
558 return -EINVAL;
559 }
560
561 /* Initialize PMU buffer with BOARDOBJGRP data. */
562 memset(pcmd->buf, 0x0, pcmd->fbsize);
563 status = pboardobjgrp->pmudatainit(g, pboardobjgrp,
564 pcmd->buf);
565 if (status) {
566 nvgpu_err(g, "could not parse pmu data");
567 goto boardobjgrp_pmuset_exit;
568 }
569
570 /*
571 * Reset the boolean that indicates set status
572 * for most recent instance of BOARDOBJGRP.
573 */
574 pboardobjgrp->pmu.bset = false;
575
576 /*
577 * copy constructed pmu boardobjgrp data from
578 * sysmem to pmu super surface present in FB
579 */
580 nvgpu_mem_wr_n(g, &pmu->super_surface_buf,
581 pcmd->super_surface_offset, pcmd->buf,
582 pcmd->fbsize);
583
584 /* Send the SET PMU CMD to the PMU using RPC*/
585 status = boardobjgrp_pmucmdsend_rpc(g, pboardobjgrp,
586 pcmd, false);
587 if (status) {
588 nvgpu_err(g, "could not send SET CMD to PMU");
589 goto boardobjgrp_pmuset_exit;
590 }
591
592 pboardobjgrp->pmu.bset = true;
593
594boardobjgrp_pmuset_exit:
595 return status;
596}
597
598int
599boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp,
600 struct boardobjgrpmask *mask)
601{
602 int status = 0;
603 struct boardobjgrp_pmu_cmd *pcmd =
604 (struct boardobjgrp_pmu_cmd *)(&pboardobjgrp->pmu.getstatus);
605 struct boardobjgrp_pmu_cmd *pset =
606 (struct boardobjgrp_pmu_cmd *)(&pboardobjgrp->pmu.set);
607
608 nvgpu_log_info(g, " ");
609
610 if (check_boardobjgrp_param(g, pboardobjgrp)) {
611 return -EINVAL;
612 }
613
614 if (pset->id == BOARDOBJGRP_GRP_CMD_ID_INVALID) {
615 return -EINVAL;
616 }
617
618 if ((pcmd->hdrsize == 0) ||
619 (pcmd->entrysize == 0) ||
620 (pcmd->buf == NULL)) {
621 return -EINVAL;
622 }
623
624 /*
625 * Can only GET_STATUS if the BOARDOBJGRP has been previously SET to the
626 * PMU
627 */
628 if (!pboardobjgrp->pmu.bset) {
629 return -EINVAL;
630 }
631
632 /*
633 * alloc mem in vidmem & copy constructed pmu boardobjgrp data from
634 * sysmem to vidmem
635 */
636 if (pcmd->surf.vidmem_desc.size == 0) {
637 nvgpu_pmu_vidmem_surface_alloc(g, &pcmd->surf.vidmem_desc,
638 pcmd->fbsize);
639 }
640
641 /*
642 * Initialize PMU buffer with the mask of BOARDOBJGRPs for which to
643 * retrieve status
644 */
645
646 memset(pcmd->buf, 0x0, pcmd->fbsize);
647 status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp,
648 pcmd->buf, mask);
649 if (status) {
650 nvgpu_err(g, "could not init PMU HDR data");
651 goto boardobjgrp_pmugetstatus_exit;
652 }
653
654 nvgpu_mem_wr_n(g, &pcmd->surf.vidmem_desc, 0, pset->buf, pset->hdrsize);
655 /* Send the GET_STATUS PMU CMD to the PMU */
656 status = boardobjgrp_pmucmdsend(g, pboardobjgrp,
657 &pboardobjgrp->pmu.getstatus);
658 if (status) {
659 nvgpu_err(g, "could not send GET_STATUS cmd to PMU");
660 goto boardobjgrp_pmugetstatus_exit;
661 }
662
663 /*copy the data back to sysmem buffer that belongs to command*/
664 nvgpu_mem_rd_n(g, &pcmd->surf.vidmem_desc, 0, pcmd->buf, pcmd->fbsize);
665
666boardobjgrp_pmugetstatus_exit:
667 return status;
668}
669
670int
671boardobjgrp_pmugetstatus_impl_v1(struct gk20a *g, struct boardobjgrp *pboardobjgrp,
672 struct boardobjgrpmask *mask)
673{
674 struct nvgpu_pmu *pmu = &g->pmu;
675 int status = 0;
676 struct boardobjgrp_pmu_cmd *pcmd =
677 (struct boardobjgrp_pmu_cmd *)(&pboardobjgrp->pmu.getstatus);
678
679 nvgpu_log_info(g, " ");
680
681 if (check_boardobjgrp_param(g, pboardobjgrp)) {
682 return -EINVAL;
683 }
684
685 if ((pcmd->buf == NULL) &&
686 (pboardobjgrp->pmu.rpc_func_id ==
687 BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID)) {
688 return -EINVAL;
689 }
690
691 /*
692 * Can only GET_STATUS if the BOARDOBJGRP has been
693 * previously SET to the PMU
694 */
695 if (!pboardobjgrp->pmu.bset) {
696 return -EINVAL;
697 }
698
699 /*
700 * Initialize PMU buffer with the mask of
701 * BOARDOBJGRPs for which to retrieve status
702 */
703 memset(pcmd->buf, 0x0, pcmd->fbsize);
704 status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp,
705 pcmd->buf, mask);
706 if (status) {
707 nvgpu_err(g, "could not init PMU HDR data");
708 goto boardobjgrp_pmugetstatus_exit;
709 }
710
711 /*
712 * copy constructed pmu boardobjgrp data from
713 * sysmem to pmu super surface present in FB
714 */
715 nvgpu_mem_wr_n(g, &pmu->super_surface_buf, pcmd->super_surface_offset,
716 pcmd->buf, pcmd->fbsize);
717 /* Send the GET_STATUS PMU CMD to the PMU */
718 status = boardobjgrp_pmucmdsend_rpc(g, pboardobjgrp,
719 pcmd, true);
720 if (status) {
721 nvgpu_err(g, "could not send GET_STATUS cmd to PMU");
722 goto boardobjgrp_pmugetstatus_exit;
723 }
724
725 /*copy the data back to sysmem buffer that belongs to command*/
726 nvgpu_mem_rd_n(g, &pmu->super_surface_buf,pcmd->super_surface_offset,
727 pcmd->buf, pcmd->fbsize);
728
729boardobjgrp_pmugetstatus_exit:
730 return status;
731}
732
733static int
734boardobjgrp_objinsert_final(struct boardobjgrp *pboardobjgrp,
735 struct boardobj *pboardobj, u8 index)
736{
737 struct gk20a *g = pboardobjgrp->g;
738
739 nvgpu_log_info(g, " ");
740
741 if (pboardobjgrp == NULL) {
742 return -EINVAL;
743 }
744
745 if (pboardobj == NULL) {
746 return -EINVAL;
747 }
748
749 if (index > pboardobjgrp->objslots) {
750 return -EINVAL;
751 }
752
753 if (pboardobjgrp->ppobjects[index] != NULL) {
754 return -EINVAL;
755 }
756
757 /*
758 * Check that this BOARDOBJ has not already been added to a
759 * BOARDOBJGRP
760 */
761 if (pboardobj->idx != CTRL_BOARDOBJ_IDX_INVALID) {
762 return -EINVAL;
763 }
764
765 pboardobjgrp->ppobjects[index] = pboardobj;
766 pboardobjgrp->objmaxidx = (u8)(BOARDOBJGRP_IS_EMPTY(pboardobjgrp) ?
767 index : max(pboardobjgrp->objmaxidx, index));
768 pboardobj->idx = index;
769
770 pboardobjgrp->objmask |= BIT(index);
771
772 nvgpu_log_info(g, " Done");
773
774 return boardobjgrpmask_bitset(pboardobjgrp->mask, index);
775}
776
777static struct boardobj *boardobjgrp_objgetbyidx_final(
778 struct boardobjgrp *pboardobjgrp, u8 index)
779{
780 if (!boardobjgrp_idxisvalid(pboardobjgrp, index)) {
781 return NULL;
782 }
783 return pboardobjgrp->ppobjects[index];
784}
785
786static struct boardobj *boardobjgrp_objgetnext_final(
787 struct boardobjgrp *pboardobjgrp, u8 *currentindex,
788 struct boardobjgrpmask *mask)
789{
790 struct boardobj *pboardobjnext = NULL;
791 u8 objmaxidx;
792 u8 index;
793
794 if (currentindex == NULL) {
795 return NULL;
796 }
797
798 if (pboardobjgrp == NULL) {
799 return NULL;
800 }
801
802 /* Search from next element unless first object was requested */
803 index = (*currentindex != CTRL_BOARDOBJ_IDX_INVALID) ?
804 (*currentindex + 1) : 0;
805
806 /* For the cases below in which we have to return NULL */
807 *currentindex = CTRL_BOARDOBJ_IDX_INVALID;
808
809
810 /* Validate provided mask */
811 if (mask != NULL) {
812 if (!(boardobjgrpmask_sizeeq(pboardobjgrp->mask, mask))) {
813 return NULL;
814 }
815 }
816
817 objmaxidx = pboardobjgrp->objmaxidx;
818
819 if (objmaxidx != CTRL_BOARDOBJ_IDX_INVALID) {
820 for (; index <= objmaxidx; index++) {
821 pboardobjnext = pboardobjgrp->ppobjects[index];
822 if (pboardobjnext != NULL) {
823 /* Filter results using client provided mask.*/
824 if (mask != NULL) {
825 if (!boardobjgrpmask_bitget(mask,
826 index)) {
827 pboardobjnext = NULL;
828 continue;
829 }
830 }
831 *currentindex = index;
832 break;
833 }
834 }
835 }
836
837 return pboardobjnext;
838}
839
840static int boardobjgrp_objremoveanddestroy_final(
841 struct boardobjgrp *pboardobjgrp,
842 u8 index)
843{
844 int status = 0;
845 int stat;
846 struct gk20a *g = pboardobjgrp->g;
847
848 nvgpu_log_info(g, " ");
849
850 if (!boardobjgrp_idxisvalid(pboardobjgrp, index)) {
851 return -EINVAL;
852 }
853
854 if (pboardobjgrp->objmaxidx == CTRL_BOARDOBJ_IDX_INVALID) {
855 return -EINVAL;
856 }
857
858 status = pboardobjgrp->ppobjects[index]->destruct(
859 pboardobjgrp->ppobjects[index]);
860
861 pboardobjgrp->ppobjects[index] = NULL;
862
863 pboardobjgrp->objmask &= ~BIT(index);
864
865 stat = boardobjgrpmask_bitclr(pboardobjgrp->mask, index);
866 if (stat) {
867 if (status == 0) {
868 status = stat;
869 }
870 }
871
872 /* objmaxidx requires update only if that very object was removed */
873 if (pboardobjgrp->objmaxidx == index) {
874 pboardobjgrp->objmaxidx =
875 boardobjgrpmask_bitidxhighest(pboardobjgrp->mask);
876 }
877
878 return status;
879}
880
881void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask)
882{
883 u32 slots = objmask;
884
885 HIGHESTBITIDX_32(slots);
886 slots++;
887
888 hdr->super.type = CTRL_BOARDOBJGRP_TYPE_E32;
889 hdr->super.class_id = 0;
890 hdr->super.obj_slots = (u8)slots;
891 hdr->obj_mask = objmask;
892}
893
894static void boardobjgrp_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
895 void *param, u32 handle, u32 status)
896{
897 struct nv_pmu_boardobj_msg_grp *pgrpmsg;
898 struct boardobjgrp_pmucmdhandler_params *phandlerparams =
899 (struct boardobjgrp_pmucmdhandler_params *)param;
900 struct boardobjgrp *pboardobjgrp = phandlerparams->pboardobjgrp;
901 struct boardobjgrp_pmu_cmd *pgrpcmd = phandlerparams->pcmd;
902
903 nvgpu_log_info(g, " ");
904
905 pgrpmsg = &msg->msg.boardobj.grp;
906
907 if (pgrpmsg->class_id != pboardobjgrp->pmu.classid) {
908 nvgpu_err(g,
909 "Unrecognized GRP type: unit %x class id=0x%02x cmd id %x",
910 msg->hdr.unit_id, pboardobjgrp->pmu.classid,
911 pgrpcmd->id);
912 return;
913 }
914
915 if (msg->msg.boardobj.msg_type != pgrpcmd->msgid) {
916 nvgpu_err(g,
917 "unsupported msg for unit %x class %x cmd id %x msg %x",
918 msg->hdr.unit_id, pboardobjgrp->pmu.classid,
919 pgrpcmd->id, msg->msg.boardobj.msg_type);
920 return;
921 }
922
923 if (msg->msg.boardobj.grp_set.flcn_status != 0) {
924 nvgpu_err(g,
925 "cmd abort for unit %x class %x cmd id %x status %x",
926 msg->hdr.unit_id, pboardobjgrp->pmu.classid,
927 pgrpcmd->id,
928 msg->msg.boardobj.grp_set.flcn_status);
929 return;
930 }
931
932 phandlerparams->success = pgrpmsg->b_success ? 1 : 0;
933
934 if (!pgrpmsg->b_success) {
935 nvgpu_err(g,
936 "failed GRPCMD: msgtype=0x%x, classid=0x%x, cmd id %x",
937 pgrpmsg->msg_type, pgrpmsg->class_id,
938 pgrpcmd->id);
939 return;
940 }
941}
942
943static int boardobjgrp_pmucmdsend(struct gk20a *g,
944 struct boardobjgrp *pboardobjgrp,
945 struct boardobjgrp_pmu_cmd *pcmd)
946{
947 struct boardobjgrp_pmucmdhandler_params handlerparams;
948 struct pmu_payload payload;
949 struct nv_pmu_boardobj_cmd_grp *pgrpcmd;
950 struct pmu_cmd cmd;
951 u32 seqdesc;
952 int status = 0;
953
954 nvgpu_log_info(g, " ");
955
956 memset(&payload, 0, sizeof(payload));
957 memset(&handlerparams, 0, sizeof(handlerparams));
958 memset(&cmd, 0, sizeof(struct pmu_cmd));
959 cmd.hdr.unit_id = pboardobjgrp->pmu.unitid;
960 cmd.hdr.size = sizeof(struct nv_pmu_boardobj_cmd_grp) +
961 sizeof(struct pmu_hdr);
962
963 pgrpcmd = &cmd.cmd.boardobj.grp;
964 pgrpcmd->cmd_type = pcmd->id;
965 pgrpcmd->class_id = pboardobjgrp->pmu.classid;
966 pgrpcmd->grp.hdr_size = pcmd->hdrsize;
967 pgrpcmd->grp.entry_size = pcmd->entrysize;
968
969 /*
970 * copy vidmem information to boardobj_cmd_grp
971 */
972 nvgpu_pmu_surface_describe(g, &pcmd->surf.vidmem_desc,
973 &pgrpcmd->grp.fb);
974
975 /*
976 * PMU reads command from sysmem so assigned
977 * "payload.in.buf = pcmd->buf"
978 * but PMU access pmu boardobjgrp data from vidmem copied above
979 */
980 payload.in.buf = pcmd->buf;
981 payload.in.size = max(pcmd->hdrsize, pcmd->entrysize);
982 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
983 payload.in.offset = offsetof(struct nv_pmu_boardobj_cmd_grp, grp);
984
985 /* Setup the handler params to communicate back results.*/
986 handlerparams.pboardobjgrp = pboardobjgrp;
987 handlerparams.pcmd = pcmd;
988 handlerparams.success = 0;
989
990 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
991 PMU_COMMAND_QUEUE_LPQ,
992 boardobjgrp_pmucmdhandler,
993 (void *)&handlerparams,
994 &seqdesc, ~0);
995 if (status) {
996 nvgpu_err(g,
997 "unable to post boardobj grp cmd for unit %x cmd id %x",
998 cmd.hdr.unit_id, pcmd->id);
999 goto boardobjgrp_pmucmdsend_exit;
1000 }
1001 pmu_wait_message_cond(&g->pmu,
1002 gk20a_get_gr_idle_timeout(g),
1003 &handlerparams.success, 1);
1004 if (handlerparams.success == 0) {
1005 nvgpu_err(g, "could not process cmd");
1006 status = -ETIMEDOUT;
1007 goto boardobjgrp_pmucmdsend_exit;
1008 }
1009
1010boardobjgrp_pmucmdsend_exit:
1011 return status;
1012}
1013
1014static int boardobjgrp_pmucmdsend_rpc(struct gk20a *g,
1015 struct boardobjgrp *pboardobjgrp,
1016 struct boardobjgrp_pmu_cmd *pcmd,
1017 bool copy_out)
1018{
1019 struct nvgpu_pmu *pmu = &g->pmu;
1020 struct nv_pmu_rpc_struct_board_obj_grp_cmd rpc;
1021 int status = 0;
1022
1023 nvgpu_log_fn(g, " ");
1024
1025 memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_board_obj_grp_cmd));
1026
1027 rpc.class_id = pboardobjgrp->pmu.classid;
1028 rpc.command_id = copy_out ?
1029 NV_PMU_BOARDOBJGRP_CMD_GET_STATUS :
1030 NV_PMU_BOARDOBJGRP_CMD_SET;
1031
1032 rpc.hdr.unit_id = pboardobjgrp->pmu.unitid;
1033 rpc.hdr.function = pboardobjgrp->pmu.rpc_func_id;
1034 rpc.hdr.flags = 0x0;
1035
1036 status = nvgpu_pmu_rpc_execute(pmu, &(rpc.hdr),
1037 (sizeof(rpc) - sizeof(rpc.scratch)),
1038 pcmd->dmem_buffer_size,
1039 NULL, NULL, copy_out);
1040
1041 if (status) {
1042 nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);
1043 }
1044
1045 return status;
1046}
diff --git a/include/boardobj/boardobjgrp.h b/include/boardobj/boardobjgrp.h
new file mode 100644
index 0000000..cd13b85
--- /dev/null
+++ b/include/boardobj/boardobjgrp.h
@@ -0,0 +1,441 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_BOARDOBJGRP_H
24#define NVGPU_BOARDOBJGRP_H
25
26struct boardobjgrp;
27struct gk20a;
28struct nvgpu_list_node;
29struct pmu_surface;
30
31
32/* ------------------------ Includes ----------------------------------------*/
33#include "ctrl/ctrlboardobj.h"
34#include "boardobj.h"
35#include "boardobjgrpmask.h"
36#include <nvgpu/list.h>
37#include <nvgpu/pmu.h>
38
39/*
40* Board Object Group destructor.
41*
42*/
43typedef int boardobjgrp_destruct(struct boardobjgrp *pboardobjgrp);
44
45/*
46* Inserts a previously constructed Board Object into a Board Object Group for
47* tracking. Objects are inserted in the array based on the given index.
48*/
49typedef int boardobjgrp_objinsert(struct boardobjgrp *pboardobjgrp,
50 struct boardobj *pboardobj, u8 index);
51
52/*
53* Retrieves a Board Object from a Board Object Group using the group's index.
54*
55*/
56typedef struct boardobj *boardobjgrp_objgetbyidx(
57 struct boardobjgrp *pBobrdobjgrp, u8 index);
58
59/*
60* Retrieve Board Object immediately following one pointed by @ref pcurrentindex
61* filtered out by the provided mask. If (pMask == NULL) => no filtering.
62*/
63typedef struct boardobj *boardobjgrp_objgetnext(
64 struct boardobjgrp *pboardobjgrp,
65 u8 *currentindex, struct boardobjgrpmask *mask);
66
67/*
68* Board Object Group Remover and destructor. This is used to remove and
69* destruct specific entry from the Board Object Group.
70*/
71typedef int boardobjgrp_objremoveanddestroy(struct boardobjgrp *pboardobjgrp,
72 u8 index);
73
74/*
75* BOARDOBJGRP handler for PMU_UNIT_INIT. Calls the PMU_UNIT_INIT handlers
76* for the constructed PMU CMDs, and then sets the object via the
77* PMU_BOARDOBJ_CMD_GRP interface (if constructed).
78*/
79typedef int boardobjgrp_pmuinithandle(struct gk20a *g,
80 struct boardobjgrp *pboardobjGrp);
81
82/*
83* Fills out the appropriate the PMU_BOARDOBJGRP_<xyz> driver<->PMU description
84* header structure, more specifically a mask of BOARDOBJs.
85*/
86typedef int boardobjgrp_pmuhdrdatainit(struct gk20a *g,
87 struct boardobjgrp *pboardobjgrp,
88 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
89 struct boardobjgrpmask *mask);
90
91/*
92* Fills out the appropriate the PMU_BOARDOBJGRP_<xyz> driver->PMU description
93* structure, describing the BOARDOBJGRP and all of its BOARDOBJs to the PMU.
94*/
95typedef int boardobjgrp_pmudatainit(struct gk20a *g,
96 struct boardobjgrp *pboardobjgrp,
97 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu);
98
99/*
100* Sends a BOARDOBJGRP to the PMU via the PMU_BOARDOBJ_CMD_GRP interface.
101* This interface leverages @ref boardobjgrp_pmudatainit to populate the
102* structure.
103*/
104typedef int boardobjgrp_pmuset(struct gk20a *g,
105 struct boardobjgrp *pboardobjgrp);
106
107/*
108* Gets the dynamic status of the PMU BOARDOBJGRP via the
109* PMU_BOARDOBJ_CMD_GRP GET_STATUS interface.
110*/
111typedef int boardobjgrp_pmugetstatus(struct gk20a *g,
112 struct boardobjgrp *pboardobjgrp,
113 struct boardobjgrpmask *mask);
114
115typedef int boardobjgrp_pmudatainstget(struct gk20a *g,
116 struct nv_pmu_boardobjgrp *boardobjgrppmu,
117 struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx);
118
119typedef int boardobjgrp_pmustatusinstget(struct gk20a *g, void *pboardobjgrppmu,
120 struct nv_pmu_boardobj_query **ppBoardobjpmustatus, u8 idx);
121
122/*
123* Structure describing an PMU CMD for interacting with the representaition
124* of this BOARDOBJGRP within the PMU.
125*/
126struct boardobjgrp_pmu_cmd {
127 u8 id;
128 u8 msgid;
129 u8 hdrsize;
130 u8 entrysize;
131 u16 dmem_buffer_size;
132 u32 super_surface_offset;
133 u32 fbsize;
134 struct nv_pmu_boardobjgrp_super *buf;
135 struct pmu_surface surf;
136};
137
138/*
139* Structure of state describing how to communicate with representation of this
140* BOARDOBJGRP in the PMU.
141*/
142struct boardobjgrp_pmu {
143 u8 unitid;
144 u8 classid;
145 bool bset;
146 u8 rpc_func_id;
147 struct boardobjgrp_pmu_cmd set;
148 struct boardobjgrp_pmu_cmd getstatus;
149};
150
151/*
152* Function by which a class which implements BOARDOBJGRP can construct a PMU
153* CMD. This provides the various information describing the PMU CMD including
154* the CMD and MSG ID and the size of the various sturctures in the payload.
155*/
156typedef int boardobjgrp_pmucmd_construct(struct gk20a *g,
157 struct boardobjgrp *pboardobjgrp,
158 struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid,
159 u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset, u8 rpc_func_id);
160
161/*
162* Destroys BOARDOBJGRP PMU SW state. CMD.
163*/
164typedef int boardobjgrp_pmucmd_destroy(struct gk20a *g,
165 struct boardobjgrp_pmu_cmd *cmd);
166
167/*
168* init handler for the BOARDOBJGRP PMU CMD. Allocates and maps the
169* PMU CMD payload within both the PMU and driver so that it can be referenced
170* at run-time.
171*/
172typedef int boardobjgrp_pmucmd_pmuinithandle(struct gk20a *g,
173 struct boardobjgrp *pboardobjgrp,
174 struct boardobjgrp_pmu_cmd *cmd);
175
176/*
177* Base Class Group for all physical or logical device on the PCB.
178* Contains fields common to all devices on the board. Specific types of
179* devices groups may extend this object adding any details specific to that
180* device group or device-type.
181*/
182struct boardobjgrp {
183 struct gk20a *g;
184 u32 objmask;
185 bool bconstructed;
186 u8 type;
187 u8 classid;
188 struct boardobj **ppobjects;
189 struct boardobjgrpmask *mask;
190 u8 objslots;
191 u8 objmaxidx;
192 struct boardobjgrp_pmu pmu;
193
194 /* Basic interfaces */
195 boardobjgrp_destruct *destruct;
196 boardobjgrp_objinsert *objinsert;
197 boardobjgrp_objgetbyidx *objgetbyidx;
198 boardobjgrp_objgetnext *objgetnext;
199 boardobjgrp_objremoveanddestroy *objremoveanddestroy;
200
201 /* PMU interfaces */
202 boardobjgrp_pmuinithandle *pmuinithandle;
203 boardobjgrp_pmuhdrdatainit *pmuhdrdatainit;
204 boardobjgrp_pmudatainit *pmudatainit;
205 boardobjgrp_pmuset *pmuset;
206 boardobjgrp_pmugetstatus *pmugetstatus;
207
208 boardobjgrp_pmudatainstget *pmudatainstget;
209 boardobjgrp_pmustatusinstget *pmustatusinstget;
210 struct nvgpu_list_node node;
211};
212
213/*
214* Macro test whether a specified index into the BOARDOBJGRP is valid.
215*
216*/
217#define boardobjgrp_idxisvalid(_pboardobjgrp, _idx) \
218 (((_idx) < (_pboardobjgrp)->objslots) && \
219 ((_pboardobjgrp)->ppobjects[(_idx)] != NULL))
220
221/*
222* Macro test whether a specified BOARDOBJGRP is empty.
223*/
224#define BOARDOBJGRP_IS_EMPTY(_pboardobjgrp) \
225 ((!((_pboardobjgrp)->bconstructed)) || \
226 ((_pboardobjgrp)->objmaxidx == CTRL_BOARDOBJ_IDX_INVALID))
227
228#define boardobjgrp_objinsert(_pboardobjgrp, _pboardobj, _idx) \
229 ((_pboardobjgrp)->objinsert((_pboardobjgrp), (_pboardobj), (_idx)))
230
231/*
232* Helper macro to determine the "next" open/empty index after all allocated
233* objects. This is intended to be used to find the index at which objects can
234* be inserted contiguously (i.e. w/o fear of colliding with existing objects).
235*/
236#define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp) \
237 ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \
238 ((((_pboardobjgrp)->objmaxidx + 1U) >= (_pboardobjgrp)->objslots) ? \
239 (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1U)))
240
241/*
242* Helper macro to determine the number of @ref BOARDOBJ pointers
243* that are required to be allocated in PMU @ref ppObjects.
244*/
245#define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp) \
246 ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \
247 (u8)((_pboardobjgrp)->objmaxidx + 1U))
248
249#define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx) \
250 ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx)))
251
252/*
253* macro to look-up next object while tolerating error if
254* Board Object Group is not constructed.
255*/
256
257#define boardobjgrpobjgetnextsafe(_pgrp, _pindex, _pmask) \
258 ((_pgrp)->bconstructed ? \
259 (_pgrp)->objgetnext((_pgrp), (_pindex), (_pmask)) : NULL)
260
261/*
262* Used to traverse all Board Objects stored within @ref _pgrp in the increasing
263* index order.
264* If @ref _pmask is provided only objects specified by the mask are traversed.
265*/
266#define BOARDOBJGRP_ITERATOR(_pgrp, _ptype, _pobj, _index, _pmask) \
267 for (_index = CTRL_BOARDOBJ_IDX_INVALID, \
268 _pobj = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), &_index, (_pmask));\
269 _pobj != NULL; \
270 _pobj = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), &_index, (_pmask)))
271#define BOARDOBJGRP_FOR_EACH(_pgrp, _ptype, _pobj, _index) \
272 BOARDOBJGRP_ITERATOR(_pgrp, _ptype, _pobj, _index, NULL)
273
274#define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \
275{ \
276 u##mask_width lcl_msk = (u##mask_width)(mask); \
277 for (index = 0; lcl_msk != 0U; index++, lcl_msk >>= 1U) { \
278 if (((u##mask_width)((u64)1) & lcl_msk) == 0U) { \
279 continue; \
280 }
281
282#define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK_END \
283 } \
284}
285
286
287/*!
288* Invalid UNIT_ID. Used to indicate that the implementing class has not set
289* @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are
290* not supported.
291*/
292#define BOARDOBJGRP_UNIT_ID_INVALID 255U
293
294/*!
295* Invalid UNIT_ID. Used to indicate that the implementing class has not set
296* @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are
297* not supported.
298*/
299#define BOARDOBJGRP_GRP_CLASS_ID_INVALID 255U
300
301/*!
302* Invalid UNIT_ID. Used to indicate that the implementing class has not set
303* @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces
304* are not supported.
305*/
306#define BOARDOBJGRP_GRP_CMD_ID_INVALID 255U
307#define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID 255U
308
309/*!
310* Helper macro to construct a BOARDOBJGRP's PMU SW state.
311*
312* @param[out] pboardobjgrp BOARDOBJGRP pointer
313* @param[in] _eng
314* Implementing engine/unit which manages the BOARDOBJGRP.
315* @param[in] _class
316* Class ID of BOARDOBJGRP.
317*/
318#define BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, _ENG, _CLASS) \
319do { \
320 (pboardobjgrp)->pmu.unitid = PMU_UNIT_##_ENG; \
321 (pboardobjgrp)->pmu.classid = \
322 NV_PMU_##_ENG##_BOARDOBJGRP_CLASS_ID_##_CLASS; \
323} while (0)
324
325#define BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, eng, ENG, \
326 class, CLASS) \
327 g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \
328 g, /* pgpu */ \
329 pboardobjgrp, /* pboardobjgrp */ \
330 &((pboardobjgrp)->pmu.set), /* pcmd */ \
331 NV_PMU_##ENG##_CMD_ID_BOARDOBJ_GRP_SET, /* id */ \
332 NV_PMU_##ENG##_MSG_ID_BOARDOBJ_GRP_SET, /* msgid */ \
333 (u32)sizeof(union nv_pmu_##eng##_##class##_boardobjgrp_set_header_aligned), \
334 (u32)sizeof(union nv_pmu_##eng##_##class##_boardobj_set_union_aligned), \
335 (u32)sizeof(struct nv_pmu_##eng##_##class##_boardobj_grp_set), \
336 (u32)offsetof(struct nv_pmu_super_surface, eng.class##_grp_set), \
337 NV_PMU_RPC_ID_##ENG##_BOARD_OBJ_GRP_CMD)
338
339#define BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, pboardobjgrp, \
340 eng, ENG, class, CLASS) \
341 g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \
342 g, /* pGpu */ \
343 pboardobjgrp, /* pBoardObjGrp */ \
344 &((pboardobjgrp)->pmu.getstatus), /* pCmd */ \
345 NV_PMU_##ENG##_CMD_ID_BOARDOBJ_GRP_GET_STATUS, /* id */ \
346 NV_PMU_##ENG##_MSG_ID_BOARDOBJ_GRP_GET_STATUS, /* msgid */ \
347 (u32)sizeof(union nv_pmu_##eng##_##class##_boardobjgrp_get_status_header_aligned), \
348 (u32)sizeof(union nv_pmu_##eng##_##class##_boardobj_get_status_union_aligned), \
349 (u32)sizeof(struct nv_pmu_##eng##_##class##_boardobj_grp_get_status), \
350 (u32)offsetof(struct nv_pmu_super_surface, eng.class##_grp_get_status), \
351 NV_PMU_RPC_ID_##ENG##_BOARD_OBJ_GRP_CMD)
352
353/* ------------------------ Function Prototypes ----------------------------- */
354/* Constructor and destructor */
355int boardobjgrp_construct_super(struct gk20a *g,
356 struct boardobjgrp *pboardobjgrp);
357boardobjgrp_destruct boardobjgrp_destruct_impl;
358boardobjgrp_destruct boardobjgrp_destruct_super;
359
360/* PMU_CMD interfaces */
361boardobjgrp_pmucmd_construct boardobjgrp_pmucmd_construct_impl;
362boardobjgrp_pmucmd_destroy boardobjgrp_pmucmd_destroy_impl;
363boardobjgrp_pmucmd_pmuinithandle boardobjgrp_pmucmd_pmuinithandle_impl;
364
365boardobjgrp_pmucmd_construct boardobjgrp_pmucmd_construct_impl_v1;
366
367/* BOARDOBJGRP interfaces */
368boardobjgrp_pmuinithandle boardobjgrp_pmuinithandle_impl;
369boardobjgrp_pmuhdrdatainit boardobjgrp_pmuhdrdatainit_super;
370boardobjgrp_pmudatainit boardobjgrp_pmudatainit_super;
371
372boardobjgrp_pmudatainit boardobjgrp_pmudatainit_legacy;
373boardobjgrp_pmuset boardobjgrp_pmuset_impl;
374boardobjgrp_pmugetstatus boardobjgrp_pmugetstatus_impl;
375boardobjgrp_pmuset boardobjgrp_pmuset_impl_v1;
376boardobjgrp_pmugetstatus boardobjgrp_pmugetstatus_impl_v1;
377
378void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask);
379
380#define HIGHESTBITIDX_32(n32) \
381{ \
382 u32 count = 0U; \
383 while (n32 >>= 1U) { \
384 count++; \
385 } \
386 n32 = count; \
387}
388
389#define LOWESTBIT(x) ((x) & (((x)-1U) ^ (x)))
390
391#define HIGHESTBIT(n32) \
392{ \
393 HIGHESTBITIDX_32(n32); \
394 n32 = NVBIT(n32); \
395}
396
397#define ONEBITSET(x) ((x) && (((x) & ((x)-1U)) == 0U))
398
399#define LOWESTBITIDX_32(n32) \
400{ \
401 n32 = LOWESTBIT(n32); \
402 IDX_32(n32); \
403}
404
405#define NUMSETBITS_32(n32) \
406{ \
407 n32 = n32 - ((n32 >> 1U) & 0x55555555U); \
408 n32 = (n32 & 0x33333333U) + ((n32 >> 2U) & 0x33333333U); \
409 n32 = (((n32 + (n32 >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U; \
410}
411
412#define IDX_32(n32) \
413{ \
414 u32 idx = 0U; \
415 if ((n32) & 0xFFFF0000U) \
416 idx += 16U; \
417 if ((n32) & 0xFF00FF00U) \
418 idx += 8U; \
419 if ((n32) & 0xF0F0F0F0U) \
420 idx += 4U; \
421 if ((n32) & 0xCCCCCCCCU) \
422 idx += 2U; \
423 if ((n32) & 0xAAAAAAAAU) \
424 idx += 1U; \
425 (n32) = idx; \
426}
427
428static inline struct boardobjgrp *
429boardobjgrp_from_node(struct nvgpu_list_node *node)
430{
431 return (struct boardobjgrp *)
432 ((uintptr_t)node - offsetof(struct boardobjgrp, node));
433};
434
435int is_boardobjgrp_pmucmd_id_valid_v0(struct gk20a *g,
436 struct boardobjgrp *pboardobjgrp,
437 struct boardobjgrp_pmu_cmd *cmd);
438int is_boardobjgrp_pmucmd_id_valid_v1(struct gk20a *g,
439 struct boardobjgrp *pboardobjgrp,
440 struct boardobjgrp_pmu_cmd *cmd);
441#endif /* NVGPU_BOARDOBJGRP_H */
diff --git a/include/boardobj/boardobjgrp_e255.c b/include/boardobj/boardobjgrp_e255.c
new file mode 100644
index 0000000..63546a9
--- /dev/null
+++ b/include/boardobj/boardobjgrp_e255.c
@@ -0,0 +1,91 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#include <nvgpu/gk20a.h>
24
25#include "boardobj.h"
26#include "boardobjgrp_e255.h"
27#include "ctrl/ctrlboardobj.h"
28#include "boardobjgrp.h"
29#include "boardobjgrpmask.h"
30
31int boardobjgrpconstruct_e255(struct gk20a *g,
32 struct boardobjgrp_e255 *pboardobjgrp_e255)
33{
34 int status = 0;
35 u8 objslots;
36
37 nvgpu_log_info(g, " ");
38
39 objslots = 255;
40 status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL);
41 if (status) {
42 goto boardobjgrpconstruct_e255_exit;
43 }
44
45 pboardobjgrp_e255->super.type = CTRL_BOARDOBJGRP_TYPE_E255;
46 pboardobjgrp_e255->super.ppobjects = pboardobjgrp_e255->objects;
47 pboardobjgrp_e255->super.objslots = objslots;
48 pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super);
49
50 status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
51 if (status) {
52 goto boardobjgrpconstruct_e255_exit;
53 }
54
55 pboardobjgrp_e255->super.pmuhdrdatainit =
56 boardobjgrp_pmuhdrdatainit_e255;
57
58boardobjgrpconstruct_e255_exit:
59 return status;
60}
61
62int boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g,
63 struct boardobjgrp *pboardobjgrp,
64 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
65 struct boardobjgrpmask *mask)
66{
67 struct nv_pmu_boardobjgrp_e255 *pgrpe255 =
68 (struct nv_pmu_boardobjgrp_e255 *)pboardobjgrppmu;
69 int status;
70
71 nvgpu_log_info(g, " ");
72
73 if (pboardobjgrp == NULL) {
74 return -EINVAL;
75 }
76
77 if (pboardobjgrppmu == NULL) {
78 return -EINVAL;
79 }
80
81 status = boardobjgrpmask_export(mask,
82 mask->bitcount,
83 &pgrpe255->obj_mask.super);
84 if (status) {
85 nvgpu_err(g, "e255 init:failed export grpmask");
86 return status;
87 }
88
89 return boardobjgrp_pmuhdrdatainit_super(g,
90 pboardobjgrp, pboardobjgrppmu, mask);
91}
diff --git a/include/boardobj/boardobjgrp_e255.h b/include/boardobj/boardobjgrp_e255.h
new file mode 100644
index 0000000..bc40541
--- /dev/null
+++ b/include/boardobj/boardobjgrp_e255.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_BOARDOBJGRP_E255_H
24#define NVGPU_BOARDOBJGRP_E255_H
25
26#include "ctrl/ctrlboardobj.h"
27#include "boardobj.h"
28#include "boardobjgrpmask.h"
29#include "boardobj/boardobjgrp.h"
30
31/*
32 * boardobjgrp_e255 is @ref BOARDOBJGRP child class allowing storage of up
33 * to 255 @ref BOARDOBJ object pointers with single static 255-bit mask denoting
34 * valid object pointers.
35 */
36struct boardobjgrp_e255 {
37 struct boardobjgrp super;
38 struct boardobj *objects[CTRL_BOARDOBJGRP_E255_MAX_OBJECTS];
39 struct boardobjgrpmask_e255 mask;
40};
41
42#define boardobjgrp_pmudatainit_e255(g, pboardpbjgrp, pboardobjgrppmu) \
43 boardobjgrp_pmudatainit_super(g, pboardpbjgrp, pboardobjgrppmu)
44
45/* Constructor and destructor */
46int boardobjgrpconstruct_e255(struct gk20a *g,
47 struct boardobjgrp_e255 *pboardobjgrp);
48boardobjgrp_destruct boardobjgrpdestruct_e255;
49boardobjgrp_pmuhdrdatainit boardobjgrp_pmuhdrdatainit_e255;
50
51#endif /* NVGPU_BOARDOBJGRP_E255_H */
diff --git a/include/boardobj/boardobjgrp_e32.c b/include/boardobj/boardobjgrp_e32.c
new file mode 100644
index 0000000..d72e8cb
--- /dev/null
+++ b/include/boardobj/boardobjgrp_e32.c
@@ -0,0 +1,89 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#include <nvgpu/gk20a.h>
23
24#include "boardobj.h"
25#include "boardobjgrp.h"
26#include "boardobjgrp_e32.h"
27#include "ctrl/ctrlboardobj.h"
28#include "boardobjgrpmask.h"
29
30
31int boardobjgrpconstruct_e32(struct gk20a *g,
32 struct boardobjgrp_e32 *pboardobjgrp_e32)
33{
34 int status;
35 u8 objslots;
36
37 nvgpu_log_info(g, " ");
38 objslots = 32;
39
40 status = boardobjgrpmask_e32_init(&pboardobjgrp_e32->mask, NULL);
41 if (status) {
42 goto boardobjgrpconstruct_e32_exit;
43 }
44
45 pboardobjgrp_e32->super.type = CTRL_BOARDOBJGRP_TYPE_E32;
46 pboardobjgrp_e32->super.ppobjects = pboardobjgrp_e32->objects;
47 pboardobjgrp_e32->super.objslots = objslots;
48 pboardobjgrp_e32->super.mask = &(pboardobjgrp_e32->mask.super);
49
50 status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super);
51 if (status) {
52 goto boardobjgrpconstruct_e32_exit;
53 }
54
55 pboardobjgrp_e32->super.pmuhdrdatainit = boardobjgrp_pmuhdrdatainit_e32;
56
57boardobjgrpconstruct_e32_exit:
58 return status;
59}
60
61int boardobjgrp_pmuhdrdatainit_e32(struct gk20a *g,
62 struct boardobjgrp *pboardobjgrp,
63 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
64 struct boardobjgrpmask *mask)
65{
66 struct nv_pmu_boardobjgrp_e32 *pgrpe32 =
67 (struct nv_pmu_boardobjgrp_e32 *)pboardobjgrppmu;
68 int status;
69
70 nvgpu_log_info(g, " ");
71
72 if (pboardobjgrp == NULL) {
73 return -EINVAL;
74 }
75
76 if (pboardobjgrppmu == NULL) {
77 return -EINVAL;
78 }
79 status = boardobjgrpmask_export(mask,
80 mask->bitcount,
81 &pgrpe32->obj_mask.super);
82 if (status) {
83 nvgpu_err(g, "e32 init:failed export grpmask");
84 return status;
85 }
86
87 return boardobjgrp_pmuhdrdatainit_super(g,
88 pboardobjgrp, pboardobjgrppmu, mask);
89}
diff --git a/include/boardobj/boardobjgrp_e32.h b/include/boardobj/boardobjgrp_e32.h
new file mode 100644
index 0000000..d4beb47
--- /dev/null
+++ b/include/boardobj/boardobjgrp_e32.h
@@ -0,0 +1,66 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_BOARDOBJGRP_E32_H
24#define NVGPU_BOARDOBJGRP_E32_H
25
26#include "ctrl/ctrlboardobj.h"
27#include "boardobj.h"
28#include "boardobjgrp.h"
29#include "boardobjgrpmask.h"
30#include "boardobj/boardobjgrp.h"
31
32/*
33 * boardobjgrp_e32 is @ref BOARDOBJGRP child class allowing storage of up to 32
34 * @ref BOARDOBJ object pointers with single static 32-bit mask denoting valid
35 * object pointers.
36 */
37struct boardobjgrp_e32 {
38 /*
39 * BOARDOBJGRP super-class. Must be first element of the structure.
40 */
41 struct boardobjgrp super;
42 /*
43 * Statically allocated array of PBOARDOBJ-s
44 */
45 struct boardobj *objects[CTRL_BOARDOBJGRP_E32_MAX_OBJECTS];
46
47 /*
48 * Statically allocated mask strcuture referenced by super::pMask.
49 */
50 struct boardobjgrpmask_e32 mask;
51};
52
53/*
54 * Wrapper to the _SUPER implementation. Provided for the child classes which
55 * implement this interface.
56 */
57#define boardobjgrp_pmudatainit_e32(g, pboardpbjgrp, pboardobjgrppmu) \
58 boardobjgrp_pmudatainit_super(g, pboardpbjgrp, pboardobjgrppmu)
59
60/* Constructor and destructor */
61int boardobjgrpconstruct_e32(struct gk20a *g,
62 struct boardobjgrp_e32 *pboardobjgrp);
63boardobjgrp_destruct boardobjgrpdestruct_e32;
64boardobjgrp_pmuhdrdatainit boardobjgrp_pmuhdrdatainit_e32;
65
66#endif /* NVGPU_BOARDOBJGRP_E32_H */
diff --git a/include/boardobj/boardobjgrpmask.c b/include/boardobj/boardobjgrpmask.c
new file mode 100644
index 0000000..a1dcd6d
--- /dev/null
+++ b/include/boardobj/boardobjgrpmask.c
@@ -0,0 +1,411 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#include <nvgpu/gk20a.h>
23
24#include "boardobjgrp.h"
25#include "ctrl/ctrlboardobj.h"
26
27/*
28* Assures that unused bits (size .. (maskDataCount * 32 - 1)) are always zero.
29*/
30#define BOARDOBJGRPMASK_NORMALIZE(_pmask) \
31 ((_pmask)->data[(_pmask)->maskdatacount-1] &= (_pmask)->lastmaskfilter)
32
33u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
34 struct ctrl_boardobjgrp_mask *extmask)
35{
36 if (mask == NULL) {
37 return -EINVAL;
38 }
39 if ((bitsize != CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) &&
40 (bitsize != CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)) {
41 return -EINVAL;
42 }
43
44 mask->bitcount = bitsize;
45 mask->maskdatacount = CTRL_BOARDOBJGRP_MASK_DATA_SIZE(bitsize);
46 mask->lastmaskfilter = bitsize %
47 CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE;
48
49 mask->lastmaskfilter = (mask->lastmaskfilter == 0) ?
50 0xFFFFFFFF : (u32)(BIT(mask->lastmaskfilter) - 1);
51
52 return (extmask == NULL) ?
53 boardobjgrpmask_clr(mask) :
54 boardobjgrpmask_import(mask, bitsize, extmask);
55}
56
57u32 boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
58 struct ctrl_boardobjgrp_mask *extmask)
59{
60 u8 index;
61
62 if (mask == NULL) {
63 return -EINVAL;
64 }
65 if (extmask == NULL) {
66 return -EINVAL;
67 }
68 if (mask->bitcount != bitsize) {
69 return -EINVAL;
70 }
71
72 for (index = 0; index < mask->maskdatacount; index++) {
73 mask->data[index] = extmask->data[index];
74 }
75
76 BOARDOBJGRPMASK_NORMALIZE(mask);
77
78 return 0;
79}
80
81u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
82 struct ctrl_boardobjgrp_mask *extmask)
83{
84 u8 index;
85
86 if (mask == NULL) {
87 return -EINVAL;
88 }
89 if (extmask == NULL) {
90 return -EINVAL;
91 }
92 if (mask->bitcount != bitsize) {
93 return -EINVAL;
94 }
95
96 for (index = 0; index < mask->maskdatacount; index++) {
97 extmask->data[index] = mask->data[index];
98 }
99
100 return 0;
101}
102
103u32 boardobjgrpmask_clr(struct boardobjgrpmask *mask)
104{
105 u8 index;
106
107 if (mask == NULL) {
108 return -EINVAL;
109 }
110 for (index = 0; index < mask->maskdatacount; index++) {
111 mask->data[index] = 0;
112 }
113
114 return 0;
115}
116
117u32 boardobjgrpmask_set(struct boardobjgrpmask *mask)
118{
119 u8 index;
120
121 if (mask == NULL) {
122 return -EINVAL;
123 }
124 for (index = 0; index < mask->maskdatacount; index++) {
125 mask->data[index] = 0xFFFFFFFF;
126 }
127 BOARDOBJGRPMASK_NORMALIZE(mask);
128 return 0;
129}
130
131u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask)
132{
133 u8 index;
134
135 if (mask == NULL) {
136 return -EINVAL;
137 }
138 for (index = 0; index < mask->maskdatacount; index++) {
139 mask->data[index] = ~mask->data[index];
140 }
141 BOARDOBJGRPMASK_NORMALIZE(mask);
142 return 0;
143}
144
145bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask)
146{
147 u8 index;
148
149 if (mask == NULL) {
150 return true;
151 }
152 for (index = 0; index < mask->maskdatacount; index++) {
153 if (mask->data[index] != 0) {
154 return false;
155 }
156 }
157 return true;
158}
159
160u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask)
161{
162 u8 index;
163 u8 result = 0;
164
165 if (mask == NULL) {
166 return result;
167 }
168
169 for (index = 0; index < mask->maskdatacount; index++) {
170 u32 m = mask->data[index];
171
172 NUMSETBITS_32(m);
173 result += (u8)m;
174 }
175
176 return result;
177}
178
179u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask)
180{
181 u8 index;
182 u8 result = CTRL_BOARDOBJ_IDX_INVALID;
183
184 if (mask == NULL) {
185 return result;
186 }
187
188 for (index = 0; index < mask->maskdatacount; index++) {
189 u32 m = mask->data[index];
190
191 if (m != 0) {
192 LOWESTBITIDX_32(m);
193 result = (u8)m + index *
194 CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE;
195 break;
196 }
197 }
198
199 return result;
200}
201
202u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask)
203{
204 u8 index;
205 u8 result = CTRL_BOARDOBJ_IDX_INVALID;
206
207 if (mask == NULL) {
208 return result;
209 }
210
211 for (index = 0; index < mask->maskdatacount; index++) {
212 u32 m = mask->data[index];
213
214 if (m != 0) {
215 HIGHESTBITIDX_32(m);
216 result = (u8)m + index *
217 CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE;
218 break;
219 }
220 }
221
222 return result;
223}
224
225int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx)
226{
227 u8 index;
228 u8 offset;
229
230 if (mask == NULL) {
231 return -EINVAL;
232 }
233 if (bitidx >= mask->bitcount) {
234 return -EINVAL;
235 }
236
237 index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
238 offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
239
240 mask->data[index] &= ~BIT(offset);
241
242 return 0;
243}
244
245int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx)
246{
247 u8 index;
248 u8 offset;
249
250 if (mask == NULL) {
251 return -EINVAL;
252 }
253 if (bitidx >= mask->bitcount) {
254 return -EINVAL;
255 }
256
257 index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
258 offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
259
260 mask->data[index] |= BIT(offset);
261
262 return 0;
263}
264
265u32 boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx)
266{
267 u8 index;
268 u8 offset;
269
270 if (mask == NULL) {
271 return -EINVAL;
272 }
273 if (bitidx >= mask->bitcount) {
274 return -EINVAL;
275 }
276
277 index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
278 offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
279
280 mask->data[index] ^= ~BIT(offset);
281
282 return 0;
283}
284
285bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx)
286{
287 u8 index;
288 u8 offset;
289
290 if (mask == NULL) {
291 return false;
292 }
293 if (bitidx >= mask->bitcount) {
294 return false;
295 }
296
297 index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
298 offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
299
300 return (mask->data[index] & BIT(offset)) != 0;
301}
302
303u32 boardobjgrpmask_and(struct boardobjgrpmask *dst,
304 struct boardobjgrpmask *op1,
305 struct boardobjgrpmask *op2)
306{
307 u8 index;
308
309 if (!boardobjgrpmask_sizeeq(dst, op1)) {
310 return -EINVAL;
311 }
312 if (!boardobjgrpmask_sizeeq(dst, op2)) {
313 return -EINVAL;
314 }
315
316 for (index = 0; index < dst->maskdatacount; index++) {
317 dst->data[index] = op1->data[index] & op2->data[index];
318 }
319
320 return 0;
321}
322
323u32 boardobjgrpmask_or(struct boardobjgrpmask *dst,
324 struct boardobjgrpmask *op1,
325 struct boardobjgrpmask *op2)
326{
327 u8 index;
328
329 if (!boardobjgrpmask_sizeeq(dst, op1)) {
330 return -EINVAL;
331 }
332 if (!boardobjgrpmask_sizeeq(dst, op2)) {
333 return -EINVAL;
334 }
335
336 for (index = 0; index < dst->maskdatacount; index++) {
337 dst->data[index] = op1->data[index] | op2->data[index];
338 }
339
340 return 0;
341}
342
343u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst,
344 struct boardobjgrpmask *op1,
345 struct boardobjgrpmask *op2)
346{
347 u8 index;
348
349 if (!boardobjgrpmask_sizeeq(dst, op1)) {
350 return -EINVAL;
351 }
352 if (!boardobjgrpmask_sizeeq(dst, op2)) {
353 return -EINVAL;
354 }
355
356 for (index = 0; index < dst->maskdatacount; index++) {
357 dst->data[index] = op1->data[index] ^ op2->data[index];
358 }
359
360 return 0;
361}
362
363u32 boardobjgrpmask_copy(struct boardobjgrpmask *dst,
364 struct boardobjgrpmask *src)
365{
366 u8 index;
367
368 if (!boardobjgrpmask_sizeeq(dst, src)) {
369 return -EINVAL;
370 }
371
372 for (index = 0; index < dst->maskdatacount; index++) {
373 dst->data[index] = src->data[index];
374 }
375
376 return 0;
377}
378
379bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1,
380 struct boardobjgrpmask *op2)
381{
382 if (op1 == NULL) {
383 return false;
384 }
385 if (op2 == NULL) {
386 return false;
387 }
388
389 return op1->bitcount == op2->bitcount;
390}
391
392bool boardobjgrpmask_issubset(struct boardobjgrpmask *op1,
393 struct boardobjgrpmask *op2)
394{
395 u8 index;
396
397 if (!boardobjgrpmask_sizeeq(op2, op1)) {
398 return false;
399 }
400
401 for (index = 0; index < op1->maskdatacount; index++) {
402 u32 op_1 = op1->data[index];
403 u32 op_2 = op2->data[index];
404
405 if ((op_1 & op_2) != op_1) {
406 return false;
407 }
408 }
409
410 return true;
411}
diff --git a/include/boardobj/boardobjgrpmask.h b/include/boardobj/boardobjgrpmask.h
new file mode 100644
index 0000000..f4ed0af
--- /dev/null
+++ b/include/boardobj/boardobjgrpmask.h
@@ -0,0 +1,119 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_BOARDOBJGRPMASK_H
24#define NVGPU_BOARDOBJGRPMASK_H
25
26#include "ctrl/ctrlboardobj.h"
27
28
29/*
30* Board Object Group Mask super-structure.
31* Used to unify access to all BOARDOBJGRPMASK_E** child classes
32*/
33struct boardobjgrpmask {
34 /* Number of bits supported by the mask */
35 u8 bitcount;
36 /* Number of 32-bit words required to store all @ref bitCount bits */
37 u8 maskdatacount;
38 /*
39 * Bit-mask of used-bits within last 32-bit word. Used to
40 * normalize data
41 */
42 u32 lastmaskfilter;
43 /*
44 * Start of the array of 32-bit words representing the bit-mask
45 * Must be the last element of the structure.
46 */
47 u32 data[CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE];
48};
49
50struct boardobjgrpmask_e32 {
51 /*
52 * BOARDOBJGRPMASK super-class. Must be the first element of the
53 * structure.
54 */
55 struct boardobjgrpmask super;
56 /*u32 data_e32[1]; */
57};
58
59struct boardobjgrpmask_e255 {
60 /*
61 * BOARDOBJGRPMASK super-class. Must be the first element of the
62 * structure.
63 */
64 struct boardobjgrpmask super;
65 u32 data_e255[254];
66};
67
68/* Init and I/O operations.*/
69u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
70 struct ctrl_boardobjgrp_mask *extmask);
71u32 boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
72 struct ctrl_boardobjgrp_mask *extmask);
73u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
74 struct ctrl_boardobjgrp_mask *extmask);
75
76/* Operations on all bits of a single mask.*/
77u32 boardobjgrpmask_clr(struct boardobjgrpmask *mask);
78u32 boardobjgrpmask_set(struct boardobjgrpmask *mask);
79u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask);
80bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask);
81u8 boardobjgrpmask_bitsetcount(struct boardobjgrpmask *mask);
82u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask);
83u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask);
84
85/* Operations on a single bit of a single mask */
86int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx);
87int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx);
88u32 boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx);
89bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx);
90
91/* Operations on a multiple masks */
92u32 boardobjgrpmask_and(struct boardobjgrpmask *dst,
93 struct boardobjgrpmask *op1,
94 struct boardobjgrpmask *op2);
95u32 boardobjgrpmask_or(struct boardobjgrpmask *dst, struct boardobjgrpmask *op1,
96 struct boardobjgrpmask *op2);
97u32 boardobjgrpmask_xor(struct boardobjgrpmask *dst,
98 struct boardobjgrpmask *op1,
99 struct boardobjgrpmask *op2);
100
101/* Special interfaces */
102u32 boardobjgrpmask_copy(struct boardobjgrpmask *dst,
103 struct boardobjgrpmask *src);
104bool boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1,
105 struct boardobjgrpmask *op2);
106bool boardobjgrpmask_issubset(struct boardobjgrpmask *op1,
107 struct boardobjgrpmask *op2);
108
109/* init boardobjgrpmask_e32 structure */
110#define boardobjgrpmask_e32_init(pmaske32, pextmask) \
111 boardobjgrpmask_init(&(pmaske32)->super, \
112 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS, (pextmask))
113
114/* init boardobjgrpmask_e255 structure */
115#define boardobjgrpmask_e255_init(pmaske255, pextmask) \
116 boardobjgrpmask_init(&(pmaske255)->super, \
117 CTRL_BOARDOBJGRP_E255_MAX_OBJECTS, (pextmask))
118
119#endif /* NVGPU_BOARDOBJGRPMASK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 02:12:11 -0400