Rearrange, fix an off-by-one error, and remove an unused define

The code in nvdebug.h has been rearranged to enable an easier merge
against the jbakita-wip branch.

2 files changed, 53 insertions, 54 deletions

diff --git a/device_info_procfs.c b/device_info_procfs.c
index 195b3ff..e94bef5 100644
--- a/device_info_procfs.c
+++ b/device_info_procfs.c
@@ -47,7 +47,7 @@ static void* device_info_file_seq_start(struct seq_file *s, loff_t *pos) {
                 iter.type_of_next_entry = 0;
                 iter.has_next_entry = 0;
                 // On Ampere+, the device_info table length can vary
-                if (g->chip_id > NV_CHIP_ID_AMPERE)
+                if (g->chip_id >= NV_CHIP_ID_AMPERE)
                         iter.length = NV_PTOP_DEVICE_INFO__SIZE_1_GA100(g);
                 else
                         iter.length = NV_PTOP_DEVICE_INFO__SIZE_1_GK104;
diff --git a/nvdebug.h b/nvdebug.h
index 39e07b4..e91763e 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -449,58 +449,6 @@ typedef union {
         } __attribute__((packed));
 } mc_boot_0_t;
 
-enum DEVICE_INFO_TYPE {INFO_TYPE_NOT_VALID = 0, INFO_TYPE_DATA = 1, INFO_TYPE_ENUM = 2, INFO_TYPE_ENGINE_TYPE = 3};
-enum ENGINE_TYPES {
-        ENGINE_GRAPHICS = 0, // GRAPHICS [/compute]
-        ENGINE_COPY0 = 1, // [raw/physical] COPY #0
-        ENGINE_COPY1 = 2, // [raw/physical] COPY #1
-        ENGINE_COPY2 = 3, // [raw/physical] COPY #2
-
-        ENGINE_MSPDEC = 8, // Picture DECoder
-        ENGINE_MSPPP = 9, // [Video] Picture Post Processor
-        ENGINE_MSVLD = 10, // [Video] Variable Length Decoder
-        ENGINE_MSENC = 11, // [Video] ENCoding
-        ENGINE_VIC = 12, // Video Image Compositor
-        ENGINE_SEC = 13, // SEquenCer [?]
-        ENGINE_NVENC0 = 14, // Nvidia Video ENCoder #0
-        ENGINE_NVENC1 = 15, // Nvidia Video ENCoder #1
-        ENGINE_NVDEC = 16, // Nvidia Video DECoder
-
-        ENGINE_IOCTRL = 18, // I/O ConTRoLler [of NVLINK at least]
-        ENGINE_LCE = 19, // Logical Copy Engine
-        ENGINE_GSP = 20, // Gpu System Processor (Volta+)
-        ENGINE_NVJPG = 21, // NVidia JPeG [Decoder] (Turing+)
-        ENGINE_OFA = 22, // Optical Flow Accelerator (Turing+)
-        ENGINE_FLA = 23, // [NVLink] Fabric Logical Addressing [?]
-};
-#define ENGINE_TYPES_LEN 24
-static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = {
-        "Graphics/Compute",
-        "COPY0",
-        "COPY1",
-        "COPY2",
-        "Unknown Engine ID#4",
-        "Unknown Engine ID#5",
-        "Unknown Engine ID#6",
-        "Unknown Engine ID#7",
-        "MSPDEC: Picture Decoder",
-        "MSPPP: Post Processing",
-        "MSVLD: Variable Length Decoder",
-        "MSENC: Encoder",
-        "VIC: Video Image Compositor",
-        "SEC: Sequencer",
-        "NVENC0: NVIDIA Video Encoder #0",
-        "NVENC1: NVIDIA Video Encoder #1",
-        "NVDEC: NVIDIA Video Decoder",
-        "Unknown Engine ID#17",
-        "IOCTRL: I/O Controller",
-        "LCE: Logical Copy Engine",
-        "GSP: GPU System Processor",
-        "NVJPG: NVIDIA JPEG Decoder",
-        "OFA: Optical Flow Accelerator",
-        "FLA: Fabric Logical Addressing",
-};
-
 /* GPU engine information and control register offsets (GPU TOPology)
   Each engine is described by one or more entries (terminated by an entry with
   the `has_next_entry` flag unset) in the fixed-size PTOP_DEVICE_INFO table. A
@@ -567,7 +515,58 @@ static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = {
 #define NV_PTOP_DEVICE_INFO_GK104(i) (0x00022700+(i)*4)
 #define NV_PTOP_DEVICE_INFO__SIZE_1_GA100(g) (nvdebug_readl(g, 0x0224fc) >> 20)
 #define NV_PTOP_DEVICE_INFO__SIZE_1_GK104 64
-#define NV_PTOP_DEVICE_INFO_TYPE_COUNT 3
+enum DEVICE_INFO_TYPE {INFO_TYPE_NOT_VALID = 0, INFO_TYPE_DATA = 1, INFO_TYPE_ENUM = 2, INFO_TYPE_ENGINE_TYPE = 3};
+enum ENGINE_TYPES {
+        ENGINE_GRAPHICS = 0, // GRAPHICS [/compute]
+        ENGINE_COPY0 = 1, // [raw/physical] COPY #0
+        ENGINE_COPY1 = 2, // [raw/physical] COPY #1
+        ENGINE_COPY2 = 3, // [raw/physical] COPY #2
+
+        ENGINE_MSPDEC = 8, // Picture DECoder
+        ENGINE_MSPPP = 9, // [Video] Picture Post Processor
+        ENGINE_MSVLD = 10, // [Video] Variable Length Decoder
+        ENGINE_MSENC = 11, // [Video] ENCoding
+        ENGINE_VIC = 12, // Video Image Compositor
+        ENGINE_SEC = 13, // SEquenCer [?]
+        ENGINE_NVENC0 = 14, // Nvidia Video ENCoder #0
+        ENGINE_NVENC1 = 15, // Nvidia Video ENCoder #1
+        ENGINE_NVDEC = 16, // Nvidia Video DECoder
+
+        ENGINE_IOCTRL = 18, // I/O ConTRoLler [of NVLINK at least]
+        ENGINE_LCE = 19, // Logical Copy Engine
+        ENGINE_GSP = 20, // Gpu System Processor (Volta+)
+        ENGINE_NVJPG = 21, // NVidia JPeG [Decoder] (Turing+)
+        ENGINE_OFA = 22, // Optical Flow Accelerator (Turing+)
+        ENGINE_FLA = 23, // [NVLink] Fabric Logical Addressing [?]
+};
+#define ENGINE_TYPES_LEN 24
+static const char* const ENGINE_TYPES_NAMES[ENGINE_TYPES_LEN] = {
+        "Graphics/Compute",
+        "COPY0",
+        "COPY1",
+        "COPY2",
+        "Unknown Engine ID#4",
+        "Unknown Engine ID#5",
+        "Unknown Engine ID#6",
+        "Unknown Engine ID#7",
+        "MSPDEC: Picture Decoder",
+        "MSPPP: Post Processing",
+        "MSVLD: Variable Length Decoder",
+        "MSENC: Encoder",
+        "VIC: Video Image Compositor",
+        "SEC: Sequencer",
+        "NVENC0: NVIDIA Video Encoder #0",
+        "NVENC1: NVIDIA Video Encoder #1",
+        "NVDEC: NVIDIA Video Decoder",
+        "Unknown Engine ID#17",
+        "IOCTRL: I/O Controller",
+        "LCE: Logical Copy Engine",
+        "GSP: GPU System Processor",
+        "NVJPG: NVIDIA JPEG Decoder",
+        "OFA: Optical Flow Accelerator",
+        "FLA: Fabric Logical Addressing",
+};
+
 typedef union {
         struct {
                 uint32_t fault_id:11;