index : mc2-scripts-and-benchmarks.git	master rtas20-wip rtas21-ae rtas22 rtas22-casestudy sd-vbs
	Benchmarks and execution scripts for testing spatial isolation and SMT interference in MC^2	Joshua J Bakita

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path: root/SD-VBS/common/toolbox/toolbox_basic/TOOLBOX_calib/projectedGrid.m

	Commit message (Expand)	Author	Age
*	Squashed commit of the sb-vbs branch.	Leo Chan	2020-10-22

generated by cgit v1.2.2 (git 2.25.0) at 2026-10-16 04:22:55 -0400

/* Copyright 2021 Joshua Bakita
 * SPDX-License-Identifier: MIT
 */

// TODO(jbakita): Don't depend on these.
#include <nvgpu/gk20a.h>  // For struct gk20a
#include <linux/proc_fs.h>  // For PDE_DATA() macro
#include <linux/device.h>   // For dev_get_drvdata()
#include <linux/version.h>  // For KERNEL_VERSION and LINUX_VERSION_CODE
#include <asm/io.h>

/* Runlist Channel
  A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue
  of GPU commands. These commands are typically queued from userspace.

  Prior to Volta, channels could also exist independent of a TSG. These are
  called "bare channels" in the Jetson nvgpu driver.

  `INST_PTR` points to a GPU Instance Block which contains FIFO states, virtual
  address space configuration for this context, and a pointer to the page
  tables. All channels in a TSG point to the same GPU Instance Block (?).

  "RUNQUEUE_SELECTOR determines to which runqueue the channel belongs, and
  thereby which PBDMA will run the channel.  Increasing values select
  increasingly numbered PBDMA IDs serving the runlist.  If the selector value
  exceeds the number of PBDMAs on the runlist, the hardware will silently
  reassign the channel to run on the first PBDMA as though RUNQUEUE_SELECTOR had
  been set to 0.  (In current hardware, this is used by SCG on the graphics
  runlist only to determine which FE pipe should service a given channel.  A
  value of 0 targets the first FE pipe, which can process all FE driven engines:
  Graphics, Compute, Inline2Memory, and TwoD.  A value of 1 targets the second
  FE pipe, which can only process Compute work.  Note that GRCE work is allowed
  on either runqueue." (NVIDIA) Note that it appears runqueue 1 is the default
  for CUDA work on the Jetson Xavier.

  ENTRY_TYPE (T)        : type of this entry: ENTRY_TYPE_CHAN
  CHID (ID)             : identifier of the channel to run (overlays ENTRY_ID)
  RUNQUEUE_SELECTOR (Q) : selects which PBDMA should run this channel if
                          more than one PBDMA is supported by the runlist,
                          additionally, "A value of 0 targets the first FE
                          pipe, which can process all FE driven engines:
                          Graphics, Compute, Inline2Memory, and TwoD.  A value
                          of 1 targets the second FE pipe, which can only
                          process Compute work.  Note that GRCE work is allowed
                          on either runqueue.)"

  INST_PTR_LO           : lower 20 bits of the 4k-aligned instance block pointer
  INST_PTR_HI           : upper 32 bit of instance block pointer
  INST_TARGET (TGI)     : aperture of the instance block

  USERD_PTR_LO          : upper 24 bits of the low 32 bits, of the 512-byte-aligned USERD pointer
  USERD_PTR_HI          : upper 32 bits of USERD pointer
  USERD_TARGET (TGU)    : aperture of the USERD data structure

  Channels were around since at least Fermi, but were rearranged with Volta to
  add a USERD pointer, a longer INST pointer, and a runqueue selector flag.
*/
enum ENTRY_TYPE {ENTRY_TYPE_CHAN = 0, ENTRY_TYPE_TSG = 1};
enum INST_TARGET {TARGET_VID_MEM = 0, TARGET_SYS_MEM_COHERENT = 2, TARGET_SYS_MEM_NONCOHERENT = 3};
static inline char* target_to_text(enum INST_TARGET t) {
	switch (t) {
		case TARGET_VID_MEM:
			return "VID_MEM";
		case TARGET_SYS_MEM_COHERENT:
			return "SYS_MEM_COHERENT";
		case TARGET_SYS_MEM_NONCOHERENT:
			return "SYS_MEM_NONCOHERENT";
		default:
			printk(KERN_WARNING "[nvdebug] Invalid aperture!\n");
			return "INVALID";
	}
}

// Support: Volta, Ampere, Turing
struct gv100_runlist_chan {
// 0:63
	enum ENTRY_TYPE entry_type:1;
	uint32_t runqueue_selector:1;
	 uint32_t padding:2;
	enum INST_TARGET inst_target:2;
	 uint32_t padding2:2;
	uint32_t userd_ptr_lo:24;
	uint32_t userd_ptr_hi:32;
// 64:128
	uint32_t chid:12;
	uint32_t inst_ptr_lo:20;
	uint32_t inst_ptr_hi:32;
} __attribute__((packed));

// Support: Fermi, Kepler*, Maxwell, Pascal
// *In Kepler, inst fields may be unpopulated?
struct gm107_runlist_chan {
	uint32_t chid:12;
	 uint32_t padding0:1;
	enum ENTRY_TYPE entry_type:1;
	 uint32_t padding1:18;
	uint32_t inst_ptr_lo:20;
	enum INST_TARGET inst_target:2;  // Totally guessing on this
	 uint32_t padding2:10;
} __attribute__((packed));

#define gk110_runlist_chan gm107_runlist_chan

/* Runlist TSG (TimeSlice Group)
  The runlist is composed of timeslice groups (TSG). Each TSG corresponds
  to a single virtual address space on the GPU and contains `TSG_LENGTH`
  channels. These channels and virtual address space are accessible to the GPU
  host unit for use until the timeslice expires or a TSG switch is forcibly
  initiated via a write to `NV_PFIFO_PREEMPT`.

  timeslice = (TSG_TIMESLICE_TIMEOUT << TSG_TIMESLICE_SCALE) * 1024 nanoseconds

  ENTRY_TYPE (T)      : type of this entry: ENTRY_TYPE_TSG
  TIMESLICE_SCALE     : scale factor for the TSG's timeslice
  TIMESLICE_TIMEOUT   : timeout amount for the TSG's timeslice
  TSG_LENGTH          : number of channels that are part of this timeslice group
  TSGID               : identifier of the Timeslice group (overlays ENTRY_ID)

  TSGs appear to have been introduced with Kepler and stayed the same until
  they were rearranged at the time of channel rearrangement to support longer
  GPU instance addresses with Volta.
*/

// Support: Volta, Ampere*, Turing*
// *These treat the top 8 bits of TSGID as GFID (unused)
struct gv100_runlist_tsg {
// 0:63
	enum ENTRY_TYPE entry_type:1;
	 uint64_t padding:15;
	uint32_t timeslice_scale:4;
	 uint64_t padding2:4;
	uint32_t timeslice_timeout:8;
	uint32_t tsg_length:8;
	 uint32_t padding3:24;
// 64:128
	uint32_t tsgid:12;
	 uint64_t padding4:52;
} __attribute__((packed));
#define MAX_TSGID (1 << 12)

// Support: Kepler (v2?), Maxwell, Pascal
// Same fields as Volta except tsg_length is 6 bits rather than 8
// Last 32 bits appear to contain an undocumented inst ptr
struct gk110_runlist_tsg {
	uint32_t tsgid:12;
	 uint32_t padding0:1;
	enum ENTRY_TYPE entry_type:1;
	uint32_t timeslice_scale:4;
	uint32_t timeslice_timeout:8;
	uint32_t tsg_length:6;
	 uint32_t padding1:32;
} __attribute__((packed));


enum PREEMPT_TYPE {PREEMPT_TYPE_CHANNEL = 0, PREEMPT_TYPE_TSG = 1};

/* Preempt a TSG or Channel by ID
  ID/CHID     : Id of TSG or channel to preempt
  IS_PENDING  : Is a context switch pending?
  TYPE        : PREEMPT_TYPE_CHANNEL or PREEMPT_TYPE_TSG

  Support: Kepler, Maxwell, Pascal, Volta, Turing
*/
#define NV_PFIFO_PREEMPT 0x00002634
typedef union {
	struct {
		uint32_t id:12;
		 uint32_t padding:8;
		bool is_pending:1;
		 uint32_t padding2:3;
		enum PREEMPT_TYPE type:2;
		 uint32_t padding3:6;
	} __attribute__((packed));
	uint32_t raw;
} pfifo_preempt_t;

/*
  "Initiate a preempt of the engine by writing the bit associated with its
  runlist to NV_PFIFO_RUNLIST_PREEMPT...  Do not poll NV_PFIFO_RUNLIST_PREEMPT
  for the preempt to complete."

  Useful for preempting multiple runlists at once.

  Appears to trigger an interrupt or some other side-effect on the Jetson
  Xavier, as the built-in nvgpu driver seems to be disturbed by writing to this.

  To select the runlist dynamically, use the BIT(nr) kernel macro.
  Example:
    runlist_preempt_t rl_preempt;
    rl_preempt.raw = nvdebug_readl(g, NV_PFIFO_RUNLIST_PREEMPT);
    rl_preempt.raw |= BIT(nr);
    nvdebug_writel(g, NV_PFIFO_RUNLIST_PREEMPT, rl_preempt.raw);

  Support: Volta
*/
#define NV_PFIFO_RUNLIST_PREEMPT 0x00002638
typedef union {
	struct {
		bool runlist_0:1;
		bool runlist_1:1;
		bool runlist_2:1;
		bool runlist_3:1;
		bool runlist_4:1;