mc2-scripts-and-benchmarks.git - Benchmarks and execution scripts for testing spatial isolation and SMT interference in MC^2

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author	Joshua Bakita <jbakita@cs.unc.edu>	2020-10-20 13:35:52 -0400
committer	Joshua Bakita <jbakita@cs.unc.edu>	2020-10-20 13:41:49 -0400
commit	03412b9f841f140b9b7410a1890298e3ac2835db (patch)
tree	8417ed7fa548a571ab88f139da666787766740f3 /SD-VBS/common/toolbox/lagrcv/calcOptFlowLKMex.mexglx
parent	47ced4e96bbb782b9e780e8f2cfc637b2c21ff44 (diff)

TACLe and DIS benchmark fixes

- Use consistent approach to prevent computations from being optimized out in the DIS benchmarks - Don't print results in the DIS benchmarks - Fix a memory corruption in TACLe's "epic" benchmark reflect1() - Fix return codes for all benchmarks - Rename run_baseline.sh to run_bench.sh in preperation for this being the main benchmarking script

Diffstat (limited to 'SD-VBS/common/toolbox/lagrcv/calcOptFlowLKMex.mexglx')

0 files changed, 0 insertions, 0 deletions

/** * Copyright 2022-2025 Joshua Bakita * Library to control SM masks on CUDA launches. Co-opts preexisting debug * logic in the CUDA driver library, and thus requires a build with -lcuda. * * This file implements partitioning via three different mechanisms: * - Modifying the QMD/TMD immediately prior to upload * - Changing a field in CUDA's stream struct that CUDA applies to the QMD/TMD * This table shows the mechanism used with each CUDA version: * +-----------+---------------+---------------+--------------+ * | Version | Global Mask | Stream Mask | Next Mask | * +-----------+---------------+---------------+--------------+ * | 8.0-12.8 | TMD/QMD Hook | stream struct | TMD/QMD Hook | * | 6.5-7.5 | TMD/QMD Hook | N/A | TMD/QMD Hook | * +-----------+---------------+---------------+--------------+ * "N/A" indicates that a mask type is unsupported on that CUDA version. * Please contact the authors if support is needed for a particular feature on * an older CUDA version. Support for those is unimplemented, not impossible. * * An old implementation of this file affected the global mask on CUDA 10.2 by * changing a field in CUDA's global struct that CUDA applies to the QMD/TMD. * That implementation was extraordinarily complicated, and was replaced in * 2024 with a more-backward-compatible way of hooking the TMD/QMD. * View the old implementation via Git: `git show aa63a02e:libsmctrl.c`. */ #define _GNU_SOURCE // To enable use of memfd_create() #include <cuda.h> #include <errno.h> #include <error.h> #include <dlfcn.h> #include <fcntl.h> #include <stdbool.h> #include <stdint.h> #include <stdio.h> #include <string.h> #include <sys/mman.h> #include <sys/socket.h> #include <sys/types.h> #include <sys/un.h> #include <unistd.h> #include "libsmctrl.h" // In functions that do not return an error code, we favor terminating with an // error rather than merely printing a warning and continuing. #define abort(ret, errno, ...) error_at_line(ret, errno, __FILE__, __LINE__, \ __VA_ARGS__) /*** QMD/TMD-based SM Mask Control via Debug Callback. ***/ // Tested working on x86_64 CUDA 6.5, 9.1, and various 10+ versions // (No testing attempted on pre-CUDA-6.5 versions) // Values for the following three lines can be extracted by tracing CUPTI as // it interects with libcuda.so to set callbacks. static const CUuuid callback_funcs_id = {{0x2c, (char)0x8e, 0x0a, (char)0xd8, 0x07, 0x10, (char)0xab, 0x4e, (char)0x90, (char)0xdd, 0x54, 0x71, (char)0x9f, (char)0xe5, (char)0xf7, 0x4b}}; // These callback descriptors appear to intercept the TMD/QMD late enough that // CUDA has already applied the per-stream mask from its internal data // structures, allowing us to override it with the next mask. #define QMD_DOMAIN 0xb #define QMD_PRE_UPLOAD 0x1 /** * These globals must be non-static (i.e., have global linkage) to ensure that * if multiple copies of the library are loaded (e.g., dynamically linked to * both this program and a dependency), secondary copies do not attempt to * repeat initialization or make changes to unused copies of mask values. */ // Supreme mask (cannot be overridden) uint128_t *g_supreme_sm_mask = NULL; // Global mask (applies across all threads) uint64_t g_sm_mask = 0; // Next mask (applies per-thread) __thread uint64_t g_next_sm_mask = 0; // Flag value to indicate if setup has been completed bool sm_control_setup_called = false; #ifdef LIBSMCTRL_STATIC // Special handling for if built as a static library, and the libcuda.so.1 // libsmctrl wrapper is in use (see comment on setup() constructor for detail). static void (*shared_set_global_mask)(uint64_t) = NULL; static void (*shared_set_next_mask)(uint64_t) = NULL; #endif // v1 has been removed---it intercepted the TMD/QMD too early, making it // impossible to override the CUDA-injected stream mask with the next mask. static void control_callback_v2(void *ukwn, int domain, int cbid, const void *in_params) { // ***Only tested on platforms with 64-bit pointers.*** // The first 8-byte element in `in_params` appears to be its size. `in_params` // must have at least five 8-byte elements for index four to be valid. if (*(uint32_t*)in_params < 5 * sizeof(void*)) abort(1, 0, "Unsupported CUDA version for callback-based SM masking. Aborting..."); // The fourth 8-byte element in `in_params` is a pointer to the TMD. Note // that this fourth pointer must exist---it only exists when the first // 8-byte element of `in_params` is at least 0x28 (checked above). void* tmd = *((void**)in_params + 4); if (!tmd) abort(1, 0, "TMD allocation appears NULL; likely forward-compatibilty issue.\n"); uint32_t *lower_ptr, *upper_ptr, *ext_lower_ptr, *ext_upper_ptr; // The location of the TMD version field seems consistent across versions uint8_t tmd_ver = *(uint8_t*)(tmd + 72); if (tmd_ver >= 0x40) { // TMD V04_00 is used starting with Hopper to support masking >64 TPCs lower_ptr = tmd + 304; upper_ptr = tmd + 308; ext_lower_ptr = tmd + 312; ext_upper_ptr = tmd + 316; // XXX: Disable upper 64 TPCs until we have ...next_mask_ext and // ...global_mask_ext *ext_lower_ptr = -1; *ext_upper_ptr = -1; // An enable bit is also required *(uint32_t*)tmd |= 0x80000000; } else if (tmd_ver >= 0x16) { // TMD V01_06 is used starting with Kepler V2, and is the first to // support TPC masking lower_ptr = tmd + 84; upper_ptr = tmd + 88; } else { // TMD V00_06 is documented to not support SM masking abort(1, 0, "TMD version %04o is too old! This GPU does not support SM masking.\n", tmd_ver); } // Setting the next mask overrides both per-stream and global masks if (g_next_sm_mask) { *lower_ptr = (uint32_t)g_next_sm_mask; *upper_ptr = (uint32_t)(g_next_sm_mask >> 32); g_next_sm_mask = 0; } else if (!*lower_ptr && !*upper_ptr){ // Only apply the global mask if a per-stream mask hasn't been set *lower_ptr = (uint32_t)g_sm_mask; *upper_ptr = (uint32_t)(g_sm_mask >> 32); } // No one may override the supreme SM mask; any SMs disabled in it (set // bits) must always remain disabled. if (g_supreme_sm_mask) { *lower_ptr |= (uint32_t)*g_supreme_sm_mask; *upper_ptr |= (uint32_t)(*g_supreme_sm_mask >> 32); if (tmd_ver >= 0x40) { *ext_lower_ptr |= (uint32_t)(*g_supreme_sm_mask >> 64); *ext_upper_ptr |= (uint32_t)(*g_supreme_sm_mask >> 96); } } //fprintf(stderr, "Final SM Mask (lower): %x\n", *lower_ptr); //fprintf(stderr, "Final SM Mask (upper): %x\n", *upper_ptr); } static void setup_sm_control_callback() { int (*subscribe)(uint32_t* hndl, void(*callback)(void*, int, int, const void*), void* ukwn); int (*enable)(uint32_t enable, uint32_t hndl, int domain, int cbid); uintptr_t* tbl_base; uint32_t my_hndl; // Avoid race conditions (setup should only run once) if (__atomic_test_and_set(&sm_control_setup_called, __ATOMIC_SEQ_CST)) return; #if CUDA_VERSION <= 6050 // Verify supported CUDA version // It's impossible for us to run with a version of CUDA older than we were // built by, so this check is excluded if built with CUDA > 6.5. int ver = 0; cuDriverGetVersion(&ver); if (ver < 6050) abort(1, ENOSYS, "Global or next masking requires at least CUDA 6.5; " "this application is using CUDA %d.%d", ver / 1000, (ver % 100)); #endif // Set up callback cuGetExportTable((const void**)&tbl_base, &callback_funcs_id); uintptr_t subscribe_func_addr = *(tbl_base + 3); uintptr_t enable_func_addr = *(tbl_base + 6); subscribe = (typeof(subscribe))subscribe_func_addr; enable = (typeof(enable))enable_func_addr; int res = 0; res = subscribe(&my_hndl, control_callback_v2, NULL); if (res) abort(1, 0, "Error subscribing to launch callback. CUDA returned error code %d.", res); res = enable(1, my_hndl, QMD_DOMAIN, QMD_PRE_UPLOAD); if (res) abort(1, 0, "Error enabling launch callback. CUDA returned error code %d.", res); } // Set default mask for all launches void libsmctrl_set_global_mask(uint64_t mask) { #ifdef LIBSMCTRL_STATIC // Special handling for if built as a static library, and the libcuda.so.1 // libsmctrl wrapper is in use (see comment on setup() constructor for // detail). if (shared_set_global_mask) return (*shared_set_global_mask)(mask); #endif setup_sm_control_callback(); g_sm_mask = mask; } // Set mask for next launch from this thread void libsmctrl_set_next_mask(uint64_t mask) { #ifdef LIBSMCTRL_STATIC // Special handling for if built as a static library, and the libcuda.so.1 // libsmctrl wrapper is in use (see comment on setup() constructor for // detail). if (shared_set_next_mask) return (*shared_set_next_mask)(mask); #endif setup_sm_control_callback(); g_next_sm_mask = mask; } /*** Per-Stream SM Mask (unlikely to be forward-compatible) ***/ // Offsets for the stream struct on x86_64 // No offset appears to work with CUDA 6.5 (tried 0x0--0x1b4 w/ 4-byte step) // 6.5 tested on 340.118 #define CU_8_0_MASK_OFF 0xec #define CU_9_0_MASK_OFF 0x130 // CUDA 9.0 and 9.1 use the same offset // 9.1 tested on 390.157 #define CU_9_2_MASK_OFF 0x140 #define CU_10_0_MASK_OFF 0x244 // CUDA 10.0, 10.1 and 10.2 use the same offset // 10.1 tested on 418.113 // 10.2 tested on 440.100, 440.82, 440.64, and 440.36 #define CU_11_0_MASK_OFF 0x274 #define CU_11_1_MASK_OFF 0x2c4 #define CU_11_2_MASK_OFF 0x37c // CUDA 11.2, 11.3, 11.4, and 11.5 use the same offset // 11.4 tested on 470.223.02 #define CU_11_6_MASK_OFF 0x38c #define CU_11_7_MASK_OFF 0x3c4 #define CU_11_8_MASK_OFF 0x47c // 11.8 tested on 520.56.06 #define CU_12_0_MASK_OFF 0x4cc // CUDA 12.0 and 12.1 use the same offset // 12.0 tested on 525.147.05 #define CU_12_2_MASK_OFF 0x4e4 // 12.2 tested on 535.129.03 #define CU_12_3_MASK_OFF 0x49c // 12.3 tested on 545.29.06 #define CU_12_4_MASK_OFF 0x4ac // 12.4 tested on 550.54.14 and 550.54.15 #define CU_12_5_MASK_OFF 0x4ec // CUDA 12.5 and 12.6 use the same offset // 12.5 tested on 555.58.02 // 12.6 tested on 560.35.03 #define CU_12_7_MASK_OFF 0x4fc // CUDA 12.7 and 12.8 use the same offset // 12.7 tested on 565.77 // 12.8 tested on 570.124.06 // Offsets for the stream struct on Jetson aarch64 #define CU_9_0_MASK_OFF_JETSON 0x128 // 9.0 tested on Jetpack 3.x (TX2, Nov 2023) #define CU_10_2_MASK_OFF_JETSON 0x24c // 10.2 tested on Jetpack 4.x (AGX Xaver and TX2, Nov 2023) #define CU_11_4_MASK_OFF_JETSON 0x394 // 11.4 tested on Jetpack 5.x (AGX Orin, Nov 2023) // TODO: 11.8, 12.0, 12.1, and 12.2 on Jetpack 5.x via compatibility packages #define CU_12_2_MASK_OFF_JETSON 0x50c // 12.2 tested on Jetpack 6.x (AGX Orin, Dec 2024) #define CU_12_4_MASK_OFF_JETSON 0x4c4 // 12.4 tested on Jetpack 6.x with cuda-compat-12-4 (AGX Orin, Dec 2024) #define CU_12_5_MASK_OFF_JETSON 0x50c // 12.5 tested on Jetpack 6.x with cuda-compat-12-5 (AGX Orin, Dec 2024) #define CU_12_6_MASK_OFF_JETSON 0x514 // 12.6 tested on Jetpack 6.x with cuda-compat-12-6 (AGX Orin, Dec 2024) // Used up through CUDA 11.8 in the stream struct struct stream_sm_mask { uint32_t upper; uint32_t lower; }; // Used starting with CUDA 12.0 in the stream struct struct stream_sm_mask_v2 { uint32_t enabled; uint32_t mask[4]; }; // Check if this system has a Parker SoC (TX2/PX2 chip) // (CUDA 9.0 behaves slightly different on this platform.) // @return 1 if detected, 0 if not, -cuda_err on error #if __aarch64__ static int detect_parker_soc() { int cap_major, cap_minor, err, dev_count; if (err = cuDeviceGetCount(&dev_count)) return -err; // As CUDA devices are numbered by order of compute power, check every // device, in case a powerful discrete GPU is attached (such as on the // DRIVE PX2). We detect the Parker SoC via its unique CUDA compute // capability: 6.2. for (int i = 0; i < dev_count; i++) { if (err = cuDeviceGetAttribute(&cap_minor, CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR, i)) return -err; if (err = cuDeviceGetAttribute(&cap_major, CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR, i)) return -err; if (cap_major == 6 && cap_minor == 2) return 1; } return 0; } #endif // __aarch64__ // Should work for CUDA 8.0 through 12.8 // A cudaStream_t is a CUstream*. We use void* to avoid a cuda.h dependency in // our header void libsmctrl_set_stream_mask(void* stream, uint64_t mask) { // When the old API is used on GPUs with over 64 TPCs, disable all TPCs >64 uint128_t full_mask = -1; full_mask <<= 64; full_mask |= mask; libsmctrl_set_stream_mask_ext(stream, full_mask); } void libsmctrl_set_stream_mask_ext(void* stream, uint128_t mask) { char* stream_struct_base = *(char**)stream; struct stream_sm_mask* hw_mask = NULL; struct stream_sm_mask_v2* hw_mask_v2 = NULL; int ver; cuDriverGetVersion(&ver);


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