path: root/drivers/pci/hotplug/shpchp_hpc.c

/*
 * Standard PCI Hot Plug Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM Corp.
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include "shpchp.h"

#ifdef DEBUG
#define DBG_K_TRACE_ENTRY      ((unsigned int)0x00000001)	/* On function entry */
#define DBG_K_TRACE_EXIT       ((unsigned int)0x00000002)	/* On function exit */
#define DBG_K_INFO             ((unsigned int)0x00000004)	/* Info messages */
#define DBG_K_ERROR            ((unsigned int)0x00000008)	/* Error messages */
#define DBG_K_TRACE            (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
#define DBG_K_STANDARD         (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
/* Redefine this flagword to set debug level */
#define DEBUG_LEVEL            DBG_K_STANDARD

#define DEFINE_DBG_BUFFER     char __dbg_str_buf[256];

#define DBG_PRINT( dbg_flags, args... )              \
	do {                                             \
	  if ( DEBUG_LEVEL & ( dbg_flags ) )             \
	  {                                              \
	    int len;                                     \
	    len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
		  __FILE__, __LINE__, __FUNCTION__ );    \
	    sprintf( __dbg_str_buf + len, args );        \
	    printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
	  }                                              \
	} while (0)

#define DBG_ENTER_ROUTINE	DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
#define DBG_LEAVE_ROUTINE	DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
#else
#define DEFINE_DBG_BUFFER
#define DBG_ENTER_ROUTINE
#define DBG_LEAVE_ROUTINE
#endif				/* DEBUG */

/* Slot Available Register I field definition */
#define SLOT_33MHZ		0x0000001f
#define SLOT_66MHZ_PCIX		0x00001f00
#define SLOT_100MHZ_PCIX	0x001f0000
#define SLOT_133MHZ_PCIX	0x1f000000

/* Slot Available Register II field definition */
#define SLOT_66MHZ		0x0000001f
#define SLOT_66MHZ_PCIX_266	0x00000f00
#define SLOT_100MHZ_PCIX_266	0x0000f000
#define SLOT_133MHZ_PCIX_266	0x000f0000
#define SLOT_66MHZ_PCIX_533	0x00f00000
#define SLOT_100MHZ_PCIX_533	0x0f000000
#define SLOT_133MHZ_PCIX_533	0xf0000000

/* Slot Configuration */
#define SLOT_NUM		0x0000001F
#define	FIRST_DEV_NUM		0x00001F00
#define PSN			0x07FF0000
#define	UPDOWN			0x20000000
#define	MRLSENSOR		0x40000000
#define ATTN_BUTTON		0x80000000

/* Slot Status Field Definitions */
/* Slot State */
#define PWR_ONLY		0x0001
#define ENABLED			0x0002
#define DISABLED		0x0003

/* Power Indicator State */
#define PWR_LED_ON		0x0004
#define PWR_LED_BLINK		0x0008
#define PWR_LED_OFF		0x000c

/* Attention Indicator State */
#define ATTEN_LED_ON		0x0010
#define	ATTEN_LED_BLINK		0x0020
#define ATTEN_LED_OFF		0x0030

/* Power Fault */
#define pwr_fault		0x0040

/* Attention Button */
#define ATTEN_BUTTON		0x0080

/* MRL Sensor */
#define MRL_SENSOR		0x0100

/* 66 MHz Capable */
#define IS_66MHZ_CAP		0x0200

/* PRSNT1#/PRSNT2# */
#define SLOT_EMP		0x0c00

/* PCI-X Capability */
#define NON_PCIX		0x0000
#define PCIX_66			0x1000
#define PCIX_133		0x3000
#define PCIX_266		0x4000  /* For PI = 2 only */
#define PCIX_533		0x5000	/* For PI = 2 only */

/* SHPC 'write' operations/commands */

/* Slot operation - 0x00h to 0x3Fh */

#define NO_CHANGE		0x00

/* Slot state - Bits 0 & 1 of controller command register */
#define SET_SLOT_PWR		0x01	
#define SET_SLOT_ENABLE		0x02	
#define SET_SLOT_DISABLE	0x03	

/* Power indicator state - Bits 2 & 3 of controller command register*/
#define SET_PWR_ON		0x04	
#define SET_PWR_BLINK		0x08	
#define SET_PWR_OFF		0x0C	

/* Attention indicator state - Bits 4 & 5 of controller command register*/
#define SET_ATTN_ON		0x010	
#define SET_ATTN_BLINK		0x020
#define SET_ATTN_OFF		0x030	

/* Set bus speed/mode A - 0x40h to 0x47h */
#define SETA_PCI_33MHZ		0x40
#define SETA_PCI_66MHZ		0x41
#define SETA_PCIX_66MHZ		0x42
#define SETA_PCIX_100MHZ	0x43
#define SETA_PCIX_133MHZ	0x44
#define RESERV_1		0x45
#define RESERV_2		0x46
#define RESERV_3		0x47

/* Set bus speed/mode B - 0x50h to 0x5fh */
#define	SETB_PCI_33MHZ		0x50
#define SETB_PCI_66MHZ		0x51
#define SETB_PCIX_66MHZ_PM	0x52
#define SETB_PCIX_100MHZ_PM	0x53
#define SETB_PCIX_133MHZ_PM	0x54
#define SETB_PCIX_66MHZ_EM	0x55
#define SETB_PCIX_100MHZ_EM	0x56
#define SETB_PCIX_133MHZ_EM	0x57
#define SETB_PCIX_66MHZ_266	0x58
#define SETB_PCIX_100MHZ_266	0x59
#define SETB_PCIX_133MHZ_266	0x5a
#define SETB_PCIX_66MHZ_533	0x5b
#define SETB_PCIX_100MHZ_533	0x5c
#define SETB_PCIX_133MHZ_533	0x5d


/* Power-on all slots - 0x48h */
#define SET_PWR_ON_ALL		0x48

/* Enable all slots	- 0x49h */
#define SET_ENABLE_ALL		0x49

/*  SHPC controller command error code */
#define SWITCH_OPEN		0x1
#define INVALID_CMD		0x2
#define INVALID_SPEED_MODE	0x4

/* For accessing SHPC Working Register Set */
#define DWORD_SELECT		0x2
#define DWORD_DATA		0x4
#define BASE_OFFSET		0x0

/* Field Offset in Logical Slot Register - byte boundary */
#define SLOT