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path: root/arch/powerpc/platforms/cell/axon_msi.c
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* Remove msic_dcr_read() in axon_msi.cMichael Ellerman2007-10-15
| | | | | | | | msic_dcr_read() doesn't really do anything useful, just replace it with direct calls to dcr_read(). Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* Add dcr_host_t.base in dcr_read()/dcr_write()Michael Ellerman2007-10-15
| | | | | | | | | | | | | | | | | | | | | | | Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we can save them the trouble and do it in dcr_read()/dcr_write(). As some background to why we just went through all this jiggery-pokery, benh sayeth: Initially the goal of the dcr_read/dcr_write routines was to operate like mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx hardware, indirect DCR access is a pain (goes through a table of instructions) and it's useful to have the compiler resolve an absolute DCR inline. We decided that wasn't worth the API bastardisation since most places where absolute DCR values are used are low level 4xx-only code which may as well continue using mfdcr/mtdcr, while the new API is designed for device "instances" that can exist on 4xx and Axon type platforms and may be located at variable DCR offsets. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* [POWERPC] Update axon_msi to use dcr_host_t.baseMichael Ellerman2007-10-02
| | | | | | | | | Now that dcr_host_t contains the base address, we can use that in the axon_msi code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Make sure to of_node_get() the result of pci_device_to_OF_node()Michael Ellerman2007-10-02
| | | | | | | | | pci_device_to_OF_node() returns the device node attached to a PCI device, but doesn't actually grab a reference - we need to do it ourselves. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Provide a default irq_host match, which matches on an exact of_nodeMichael Ellerman2007-09-13
| | | | | | | | | The most common match semantic is an exact match based on the device node. So provide a default implementation that does this, and hook it up if no match routine is specified. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add an optional device_node pointer to the irq_hostMichael Ellerman2007-09-13
| | | | | | | | | | The majority of irq_host implementations (3 out of 4) are associated with a device_node, and need to stash it somewhere. Rather than having it somewhere different for each host, add an optional device_node pointer to the irq_host structure. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [CELL] add support for MSI on Axon-based Cell systemsMichael Ellerman2007-07-20
This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>