diff options
Diffstat (limited to 'include/asm-mips/sibyte/sb1250_scd.h')
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_scd.h | 102 |
1 files changed, 82 insertions, 20 deletions
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index dbbd682fb4..a667bc14a7 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h | |||
| @@ -8,8 +8,6 @@ | |||
| 8 | * | 8 | * |
| 9 | * SB1250 specification level: User's manual 1/02/02 | 9 | * SB1250 specification level: User's manual 1/02/02 |
| 10 | * | 10 | * |
| 11 | * Author: Mitch Lichtenberg | ||
| 12 | * | ||
| 13 | ********************************************************************* | 11 | ********************************************************************* |
| 14 | * | 12 | * |
| 15 | * Copyright 2000,2001,2002,2003 | 13 | * Copyright 2000,2001,2002,2003 |
| @@ -51,26 +49,70 @@ | |||
| 51 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) | 49 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) |
| 52 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) | 50 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) |
| 53 | 51 | ||
| 54 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | 52 | #define K_SYS_REVISION_BCM1250_PASS1 0x01 |
| 55 | #define K_SYS_REVISION_BCM1250_PASS1 1 | 53 | |
| 56 | #define K_SYS_REVISION_BCM1250_PASS2 3 | 54 | #define K_SYS_REVISION_BCM1250_PASS2 0x03 |
| 57 | #define K_SYS_REVISION_BCM1250_A10 11 | 55 | #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ |
| 58 | #define K_SYS_REVISION_BCM1250_PASS2_2 16 | 56 | #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ |
| 59 | #define K_SYS_REVISION_BCM1250_B2 17 | 57 | #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ |
| 60 | #define K_SYS_REVISION_BCM1250_PASS3 32 | 58 | #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ |
| 61 | #define K_SYS_REVISION_BCM1250_C1 33 | 59 | #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ |
| 60 | #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ | ||
| 61 | #define K_SYS_REVISION_BCM1250_A9 0x08 | ||
| 62 | #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 | ||
| 62 | 63 | ||
| 64 | #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 | ||
| 65 | #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 | ||
| 66 | #define K_SYS_REVISION_BCM1250_B1 0x10 | ||
| 67 | #define K_SYS_REVISION_BCM1250_B2 0x11 | ||
| 68 | |||
| 69 | #define K_SYS_REVISION_BCM1250_C0 0x20 | ||
| 70 | #define K_SYS_REVISION_BCM1250_C1 0x21 | ||
| 71 | #define K_SYS_REVISION_BCM1250_C2 0x22 | ||
| 72 | #define K_SYS_REVISION_BCM1250_C3 0x23 | ||
| 73 | |||
| 74 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | ||
| 63 | /* XXX: discourage people from using these constants. */ | 75 | /* XXX: discourage people from using these constants. */ |
| 64 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 | 76 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 |
| 65 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 | 77 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 |
| 66 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 | 78 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 |
| 67 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 | 79 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 |
| 80 | #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 | ||
| 68 | #endif /* 1250 */ | 81 | #endif /* 1250 */ |
| 69 | 82 | ||
| 70 | #if SIBYTE_HDR_FEATURE_CHIP(112x) | 83 | #define K_SYS_REVISION_BCM112x_A1 0x20 |
| 71 | #define K_SYS_REVISION_BCM112x_A1 32 | 84 | #define K_SYS_REVISION_BCM112x_A2 0x21 |
| 72 | #define K_SYS_REVISION_BCM112x_A2 33 | 85 | #define K_SYS_REVISION_BCM112x_A3 0x22 |
| 73 | #endif /* 112x */ | 86 | #define K_SYS_REVISION_BCM112x_A4 0x23 |
| 87 | |||
| 88 | #define K_SYS_REVISION_BCM1480_S0 0x01 | ||
| 89 | #define K_SYS_REVISION_BCM1480_A1 0x02 | ||
| 90 | #define K_SYS_REVISION_BCM1480_A2 0x03 | ||
| 91 | #define K_SYS_REVISION_BCM1480_A3 0x04 | ||
| 92 | #define K_SYS_REVISION_BCM1480_B0 0x11 | ||
| 93 | |||
| 94 | /*Cache size - 23:20 of revision register*/ | ||
| 95 | #define S_SYS_L2C_SIZE _SB_MAKE64(20) | ||
| 96 | #define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) | ||
| 97 | #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) | ||
| 98 | #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) | ||
| 99 | |||
| 100 | #define K_SYS_L2C_SIZE_1MB 0 | ||
| 101 | #define K_SYS_L2C_SIZE_512KB 5 | ||
| 102 | #define K_SYS_L2C_SIZE_256KB 2 | ||
| 103 | #define K_SYS_L2C_SIZE_128KB 1 | ||
| 104 | |||
| 105 | #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB | ||
| 106 | #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB | ||
| 107 | #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB | ||
| 108 | |||
| 109 | |||
| 110 | /* Number of CPU cores, bits 27:24 of revision register*/ | ||
| 111 | #define S_SYS_NUM_CPUS _SB_MAKE64(24) | ||
| 112 | #define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) | ||
| 113 | #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) | ||
| 114 | #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) | ||
| 115 | |||
| 74 | 116 | ||
| 75 | /* XXX: discourage people from using these constants. */ | 117 | /* XXX: discourage people from using these constants. */ |
| 76 | #define S_SYS_PART _SB_MAKE64(16) | 118 | #define S_SYS_PART _SB_MAKE64(16) |
| @@ -83,6 +125,8 @@ | |||
| 83 | #define K_SYS_PART_BCM1120 0x1121 | 125 | #define K_SYS_PART_BCM1120 0x1121 |
| 84 | #define K_SYS_PART_BCM1125 0x1123 | 126 | #define K_SYS_PART_BCM1125 0x1123 |
| 85 | #define K_SYS_PART_BCM1125H 0x1124 | 127 | #define K_SYS_PART_BCM1125H 0x1124 |
| 128 | #define K_SYS_PART_BCM1122 0x1113 | ||
| 129 | |||
| 86 | 130 | ||
| 87 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ | 131 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ |
| 88 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) | 132 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) |
| @@ -96,6 +140,8 @@ | |||
| 96 | #define K_SYS_SOC_TYPE_BCM1125 0x3 | 140 | #define K_SYS_SOC_TYPE_BCM1125 0x3 |
| 97 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 | 141 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 |
| 98 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ | 142 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ |
| 143 | #define K_SYS_SOC_TYPE_BCM1x80 0x6 | ||
| 144 | #define K_SYS_SOC_TYPE_BCM1x55 0x7 | ||
| 99 | 145 | ||
| 100 | /* | 146 | /* |
| 101 | * Calculate correct SOC type given a copy of system revision register. | 147 | * Calculate correct SOC type given a copy of system revision register. |
| @@ -127,10 +173,12 @@ | |||
| 127 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) | 173 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) |
| 128 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) | 174 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) |
| 129 | 175 | ||
| 130 | /* System Manufacturing Register | 176 | /* |
| 131 | * Register: SCD_SYSTEM_MANUF | 177 | * System Manufacturing Register |
| 132 | */ | 178 | * Register: SCD_SYSTEM_MANUF |
| 179 | */ | ||
| 133 | 180 | ||
| 181 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 134 | /* Wafer ID: bits 31:0 */ | 182 | /* Wafer ID: bits 31:0 */ |
| 135 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) | 183 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) |
| 136 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) | 184 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) |
| @@ -139,8 +187,8 @@ | |||
| 139 | 187 | ||
| 140 | #define S_SYS_BIN _SB_MAKE64(32) | 188 | #define S_SYS_BIN _SB_MAKE64(32) |
| 141 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) | 189 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) |
| 142 | #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) | 190 | #define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) |
| 143 | #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) | 191 | #define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) |
| 144 | 192 | ||
| 145 | /* Wafer ID: bits 39:36 */ | 193 | /* Wafer ID: bits 39:36 */ |
| 146 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) | 194 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) |
| @@ -163,12 +211,14 @@ | |||
| 163 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) | 211 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) |
| 164 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) | 212 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) |
| 165 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) | 213 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) |
| 214 | #endif | ||
| 166 | 215 | ||
| 167 | /* | 216 | /* |
| 168 | * System Config Register (Table 4-2) | 217 | * System Config Register (Table 4-2) |
| 169 | * Register: SCD_SYSTEM_CFG | 218 | * Register: SCD_SYSTEM_CFG |
| 170 | */ | 219 | */ |
| 171 | 220 | ||
| 221 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 172 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) | 222 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) |
| 173 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) | 223 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) |
| 174 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) | 224 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) |
| @@ -253,6 +303,8 @@ | |||
| 253 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) | 303 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) |
| 254 | #endif /* 1250 PASS2 || 112x PASS1 */ | 304 | #endif /* 1250 PASS2 || 112x PASS1 */ |
| 255 | 305 | ||
| 306 | #endif | ||
| 307 | |||
| 256 | 308 | ||
| 257 | /* | 309 | /* |
| 258 | * Mailbox Registers (Table 4-3) | 310 | * Mailbox Registers (Table 4-3) |
| @@ -326,6 +378,7 @@ | |||
| 326 | * System Performance Counters | 378 | * System Performance Counters |
| 327 | */ | 379 | */ |
| 328 | 380 | ||
| 381 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 329 | #define S_SPC_CFG_SRC0 0 | 382 | #define S_SPC_CFG_SRC0 0 |
| 330 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) | 383 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) |
| 331 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) | 384 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) |
| @@ -348,6 +401,7 @@ | |||
| 348 | 401 | ||
| 349 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) | 402 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) |
| 350 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) | 403 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) |
| 404 | #endif | ||
| 351 | 405 | ||
| 352 | 406 | ||
| 353 | /* | 407 | /* |
| @@ -412,6 +466,7 @@ | |||
| 412 | * Address Trap Registers | 466 | * Address Trap Registers |
| 413 | */ | 467 | */ |
| 414 | 468 | ||
| 469 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 415 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) | 470 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) |
| 416 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) | 471 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) |
| 417 | 472 | ||
| @@ -436,7 +491,6 @@ | |||
| 436 | #define K_BUS_AGENT_IOB0 2 | 491 | #define K_BUS_AGENT_IOB0 2 |
| 437 | #define K_BUS_AGENT_IOB1 3 | 492 | #define K_BUS_AGENT_IOB1 3 |
| 438 | #define K_BUS_AGENT_SCD 4 | 493 | #define K_BUS_AGENT_SCD 4 |
| 439 | #define K_BUS_AGENT_RESERVED 5 | ||
| 440 | #define K_BUS_AGENT_L2C 6 | 494 | #define K_BUS_AGENT_L2C 6 |
| 441 | #define K_BUS_AGENT_MC 7 | 495 | #define K_BUS_AGENT_MC 7 |
| 442 | 496 | ||
| @@ -454,10 +508,14 @@ | |||
| 454 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 | 508 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 |
| 455 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 | 509 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 |
| 456 | 510 | ||
| 511 | #endif /* 1250/112x */ | ||
| 512 | |||
| 457 | /* | 513 | /* |
| 458 | * Trace Buffer Config register | 514 | * Trace Buffer Config register |
| 459 | */ | 515 | */ |
| 460 | 516 | ||
| 517 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 518 | |||
| 461 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | 519 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) |
| 462 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | 520 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) |
| 463 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | 521 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) |
| @@ -475,6 +533,8 @@ | |||
| 475 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) | 533 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) |
| 476 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) | 534 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) |
| 477 | 535 | ||
| 536 | #endif /* 1250/112x */ | ||
| 537 | |||
| 478 | /* | 538 | /* |
| 479 | * Trace Event registers | 539 | * Trace Event registers |
| 480 | */ | 540 | */ |
| @@ -578,5 +638,7 @@ | |||
| 578 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) | 638 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) |
| 579 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) | 639 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) |
| 580 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) | 640 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) |
| 641 | #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) | ||
| 642 | #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) | ||
| 581 | 643 | ||
| 582 | #endif | 644 | #endif |
