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-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c335
1 files changed, 196 insertions, 139 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
index 14213f090e..a27e49cfe4 100644
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ b/drivers/net/ibm_emac/ibm_emac_phy.c
@@ -1,96 +1,80 @@
1/* 1/*
2 * ibm_ocp_phy.c 2 * drivers/net/ibm_emac/ibm_emac_phy.c
3 * 3 *
4 * PHY drivers for the ibm ocp ethernet driver. Borrowed 4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * from sungem_phy.c, though I only kept the generic MII 5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now. 6 * driver for now.
7 * 7 *
8 * This file should be shared with other drivers or eventually 8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib 9 * merged as the "low level" part of miilib
10 * 10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org) 11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
12 * 13 *
13 */ 14 */
14
15#include <linux/config.h> 15#include <linux/config.h>
16
17#include <linux/module.h> 16#include <linux/module.h>
18
19#include <linux/kernel.h> 17#include <linux/kernel.h>
20#include <linux/sched.h>
21#include <linux/types.h> 18#include <linux/types.h>
22#include <linux/netdevice.h> 19#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/mii.h> 20#include <linux/mii.h>
25#include <linux/ethtool.h> 21#include <linux/ethtool.h>
26#include <linux/delay.h> 22#include <linux/delay.h>
27 23
24#include <asm/ocp.h>
25
28#include "ibm_emac_phy.h" 26#include "ibm_emac_phy.h"
29 27
30static int reset_one_mii_phy(struct mii_phy *phy, int phy_id) 28static inline int phy_read(struct mii_phy *phy, int reg)
29{
30 return phy->mdio_read(phy->dev, phy->address, reg);
31}
32
33static inline void phy_write(struct mii_phy *phy, int reg, int val)
31{ 34{
32 u16 val; 35 phy->mdio_write(phy->dev, phy->address, reg, val);
36}
37
38int mii_reset_phy(struct mii_phy *phy)
39{
40 int val;
33 int limit = 10000; 41 int limit = 10000;
34 42
35 val = __phy_read(phy, phy_id, MII_BMCR); 43 val = phy_read(phy, MII_BMCR);
36 val &= ~BMCR_ISOLATE; 44 val &= ~BMCR_ISOLATE;
37 val |= BMCR_RESET; 45 val |= BMCR_RESET;
38 __phy_write(phy, phy_id, MII_BMCR, val); 46 phy_write(phy, MII_BMCR, val);
39 47
40 udelay(100); 48 udelay(300);
41 49
42 while (limit--) { 50 while (limit--) {
43 val = __phy_read(phy, phy_id, MII_BMCR); 51 val = phy_read(phy, MII_BMCR);
44 if ((val & BMCR_RESET) == 0) 52 if (val >= 0 && (val & BMCR_RESET) == 0)
45 break; 53 break;
46 udelay(10); 54 udelay(10);
47 } 55 }
48 if ((val & BMCR_ISOLATE) && limit > 0) 56 if ((val & BMCR_ISOLATE) && limit > 0)
49 __phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE); 57 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
50
51 return (limit <= 0);
52}
53
54static int cis8201_init(struct mii_phy *phy)
55{
56 u16 epcr;
57
58 epcr = phy_read(phy, MII_CIS8201_EPCR);
59 epcr &= ~EPCR_MODE_MASK;
60
61 switch (phy->mode) {
62 case PHY_MODE_TBI:
63 epcr |= EPCR_TBI_MODE;
64 break;
65 case PHY_MODE_RTBI:
66 epcr |= EPCR_RTBI_MODE;
67 break;
68 case PHY_MODE_GMII:
69 epcr |= EPCR_GMII_MODE;
70 break;
71 case PHY_MODE_RGMII:
72 default:
73 epcr |= EPCR_RGMII_MODE;
74 }
75 58
76 phy_write(phy, MII_CIS8201_EPCR, epcr); 59 return limit <= 0;
77
78 return 0;
79} 60}
80 61
81static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise) 62static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
82{ 63{
83 u16 ctl, adv; 64 int ctl, adv;
84 65
85 phy->autoneg = 1; 66 phy->autoneg = AUTONEG_ENABLE;
86 phy->speed = SPEED_10; 67 phy->speed = SPEED_10;
87 phy->duplex = DUPLEX_HALF; 68 phy->duplex = DUPLEX_HALF;
88 phy->pause = 0; 69 phy->pause = phy->asym_pause = 0;
89 phy->advertising = advertise; 70 phy->advertising = advertise;
90 71
91 /* Setup standard advertise */ 72 /* Setup standard advertise */
92 adv = phy_read(phy, MII_ADVERTISE); 73 adv = phy_read(phy, MII_ADVERTISE);
93 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 74 if (adv < 0)
75 return adv;
76 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
77 ADVERTISE_PAUSE_ASYM);
94 if (advertise & ADVERTISED_10baseT_Half) 78 if (advertise & ADVERTISED_10baseT_Half)
95 adv |= ADVERTISE_10HALF; 79 adv |= ADVERTISE_10HALF;
96 if (advertise & ADVERTISED_10baseT_Full) 80 if (advertise & ADVERTISED_10baseT_Full)
@@ -99,8 +83,25 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
99 adv |= ADVERTISE_100HALF; 83 adv |= ADVERTISE_100HALF;
100 if (advertise & ADVERTISED_100baseT_Full) 84 if (advertise & ADVERTISED_100baseT_Full)
101 adv |= ADVERTISE_100FULL; 85 adv |= ADVERTISE_100FULL;
86 if (advertise & ADVERTISED_Pause)
87 adv |= ADVERTISE_PAUSE_CAP;
88 if (advertise & ADVERTISED_Asym_Pause)
89 adv |= ADVERTISE_PAUSE_ASYM;
102 phy_write(phy, MII_ADVERTISE, adv); 90 phy_write(phy, MII_ADVERTISE, adv);
103 91
92 if (phy->features &
93 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
94 adv = phy_read(phy, MII_CTRL1000);
95 if (adv < 0)
96 return adv;
97 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
98 if (advertise & ADVERTISED_1000baseT_Full)
99 adv |= ADVERTISE_1000FULL;
100 if (advertise & ADVERTISED_1000baseT_Half)
101 adv |= ADVERTISE_1000HALF;
102 phy_write(phy, MII_CTRL1000, adv);
103 }
104
104 /* Start/Restart aneg */ 105 /* Start/Restart aneg */
105 ctl = phy_read(phy, MII_BMCR); 106 ctl = phy_read(phy, MII_BMCR);
106 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 107 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
@@ -111,14 +112,16 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
111 112
112static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd) 113static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
113{ 114{
114 u16 ctl; 115 int ctl;
115 116
116 phy->autoneg = 0; 117 phy->autoneg = AUTONEG_DISABLE;
117 phy->speed = speed; 118 phy->speed = speed;
118 phy->duplex = fd; 119 phy->duplex = fd;
119 phy->pause = 0; 120 phy->pause = phy->asym_pause = 0;
120 121
121 ctl = phy_read(phy, MII_BMCR); 122 ctl = phy_read(phy, MII_BMCR);
123 if (ctl < 0)
124 return ctl;
122 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE); 125 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
123 126
124 /* First reset the PHY */ 127 /* First reset the PHY */
@@ -132,6 +135,8 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
132 ctl |= BMCR_SPEED100; 135 ctl |= BMCR_SPEED100;
133 break; 136 break;
134 case SPEED_1000: 137 case SPEED_1000:
138 ctl |= BMCR_SPEED1000;
139 break;
135 default: 140 default:
136 return -EINVAL; 141 return -EINVAL;
137 } 142 }
@@ -144,112 +149,143 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
144 149
145static int genmii_poll_link(struct mii_phy *phy) 150static int genmii_poll_link(struct mii_phy *phy)
146{ 151{
147 u16 status; 152 int status;
148 153
149 (void)phy_read(phy, MII_BMSR); 154 /* Clear latched value with dummy read */
155 phy_read(phy, MII_BMSR);
150 status = phy_read(phy, MII_BMSR); 156 status = phy_read(phy, MII_BMSR);
151 if ((status & BMSR_LSTATUS) == 0) 157 if (status < 0 || (status & BMSR_LSTATUS) == 0)
152 return 0; 158 return 0;
153 if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE)) 159 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
154 return 0; 160 return 0;
155 return 1; 161 return 1;
156} 162}
157 163
158#define MII_CIS8201_ACSR 0x1c 164static int genmii_read_link(struct mii_phy *phy)
159#define ACSR_DUPLEX_STATUS 0x0020
160#define ACSR_SPEED_1000BASET 0x0010
161#define ACSR_SPEED_100BASET 0x0008
162
163static int cis8201_read_link(struct mii_phy *phy)
164{ 165{
165 u16 acsr; 166 if (phy->autoneg == AUTONEG_ENABLE) {
167 int glpa = 0;
168 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
169 if (lpa < 0)
170 return lpa;
171
172 if (phy->features &
173 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
174 int adv = phy_read(phy, MII_CTRL1000);
175 glpa = phy_read(phy, MII_STAT1000);
176
177 if (glpa < 0 || adv < 0)
178 return adv;
179
180 glpa &= adv << 2;
181 }
182
183 phy->speed = SPEED_10;
184 phy->duplex = DUPLEX_HALF;
185 phy->pause = phy->asym_pause = 0;
186
187 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
188 phy->speed = SPEED_1000;
189 if (glpa & LPA_1000FULL)
190 phy->duplex = DUPLEX_FULL;
191 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
192 phy->speed = SPEED_100;
193 if (lpa & LPA_100FULL)
194 phy->duplex = DUPLEX_FULL;
195 } else if (lpa & LPA_10FULL)
196 phy->duplex = DUPLEX_FULL;
166 197
167 if (phy->autoneg) { 198 if (phy->duplex == DUPLEX_FULL) {
168 acsr = phy_read(phy, MII_CIS8201_ACSR); 199 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
200 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
201 }
202 } else {
203 int bmcr = phy_read(phy, MII_BMCR);
204 if (bmcr < 0)
205 return bmcr;
169 206
170 if (acsr & ACSR_DUPLEX_STATUS) 207 if (bmcr & BMCR_FULLDPLX)
171 phy->duplex = DUPLEX_FULL; 208 phy->duplex = DUPLEX_FULL;
172 else 209 else
173 phy->duplex = DUPLEX_HALF; 210 phy->duplex = DUPLEX_HALF;
174 if (acsr & ACSR_SPEED_1000BASET) { 211 if (bmcr & BMCR_SPEED1000)
175 phy->speed = SPEED_1000; 212 phy->speed = SPEED_1000;
176 } else if (acsr & ACSR_SPEED_100BASET) 213 else if (bmcr & BMCR_SPEED100)
177 phy->speed = SPEED_100; 214 phy->speed = SPEED_100;
178 else 215 else
179 phy->speed = SPEED_10; 216 phy->speed = SPEED_10;
180 phy->pause = 0;
181 }
182 /* On non-aneg, we assume what we put in BMCR is the speed,
183 * though magic-aneg shouldn't prevent this case from occurring
184 */
185 217
218 phy->pause = phy->asym_pause = 0;
219 }
186 return 0; 220 return 0;
187} 221}
188 222
189static int genmii_read_link(struct mii_phy *phy) 223/* Generic implementation for most 10/100/1000 PHYs */
224static struct mii_phy_ops generic_phy_ops = {
225 .setup_aneg = genmii_setup_aneg,
226 .setup_forced = genmii_setup_forced,
227 .poll_link = genmii_poll_link,
228 .read_link = genmii_read_link
229};
230
231static struct mii_phy_def genmii_phy_def = {
232 .phy_id = 0x00000000,
233 .phy_id_mask = 0x00000000,
234 .name = "Generic MII",
235 .ops = &generic_phy_ops
236};
237
238/* CIS8201 */
239#define MII_CIS8201_EPCR 0x17
240#define EPCR_MODE_MASK 0x3000
241#define EPCR_GMII_MODE 0x0000
242#define EPCR_RGMII_MODE 0x1000
243#define EPCR_TBI_MODE 0x2000
244#define EPCR_RTBI_MODE 0x3000
245
246static int cis8201_init(struct mii_phy *phy)
190{ 247{
191 u16 lpa; 248 int epcr;
192 249
193 if (phy->autoneg) { 250 epcr = phy_read(phy, MII_CIS8201_EPCR);
194 lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE); 251 if (epcr < 0)
252 return epcr;
195 253
196 phy->speed = SPEED_10; 254 epcr &= ~EPCR_MODE_MASK;
197 phy->duplex = DUPLEX_HALF;
198 phy->pause = 0;
199 255
200 if (lpa & (LPA_100FULL | LPA_100HALF)) { 256 switch (phy->mode) {
201 phy->speed = SPEED_100; 257 case PHY_MODE_TBI:
202 if (lpa & LPA_100FULL) 258 epcr |= EPCR_TBI_MODE;
203 phy->duplex = DUPLEX_FULL; 259 break;
204 } else if (lpa & LPA_10FULL) 260 case PHY_MODE_RTBI:
205 phy->duplex = DUPLEX_FULL; 261 epcr |= EPCR_RTBI_MODE;
262 break;
263 case PHY_MODE_GMII:
264 epcr |= EPCR_GMII_MODE;
265 break;
266 case PHY_MODE_RGMII:
267 default:
268 epcr |= EPCR_RGMII_MODE;
206 } 269 }
207 /* On non-aneg, we assume what we put in BMCR is the speed, 270
208 * though magic-aneg shouldn't prevent this case from occurring 271 phy_write(phy, MII_CIS8201_EPCR, epcr);
209 */
210 272
211 return 0; 273 return 0;
212} 274}
213 275
214#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
215 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
216 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
217#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
218 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
219
220/* CIS8201 phy ops */
221static struct mii_phy_ops cis8201_phy_ops = { 276static struct mii_phy_ops cis8201_phy_ops = {
222 init:cis8201_init, 277 .init = cis8201_init,
223 setup_aneg:genmii_setup_aneg, 278 .setup_aneg = genmii_setup_aneg,
224 setup_forced:genmii_setup_forced, 279 .setup_forced = genmii_setup_forced,
225 poll_link:genmii_poll_link, 280 .poll_link = genmii_poll_link,
226 read_link:cis8201_read_link 281 .read_link = genmii_read_link
227};
228
229/* Generic implementation for most 10/100 PHYs */
230static struct mii_phy_ops generic_phy_ops = {
231 setup_aneg:genmii_setup_aneg,
232 setup_forced:genmii_setup_forced,
233 poll_link:genmii_poll_link,
234 read_link:genmii_read_link
235}; 282};
236 283
237static struct mii_phy_def cis8201_phy_def = { 284static struct mii_phy_def cis8201_phy_def = {
238 phy_id:0x000fc410, 285 .phy_id = 0x000fc410,
239 phy_id_mask:0x000ffff0, 286 .phy_id_mask = 0x000ffff0,
240 name:"CIS8201 Gigabit Ethernet", 287 .name = "CIS8201 Gigabit Ethernet",
241 features:MII_GBIT_FEATURES, 288 .ops = &cis8201_phy_ops
242 magic_aneg:0,
243 ops:&cis8201_phy_ops
244};
245
246static struct mii_phy_def genmii_phy_def = {
247 phy_id:0x00000000,
248 phy_id_mask:0x00000000,
249 name:"Generic MII",
250 features:MII_BASIC_FEATURES,
251 magic_aneg:0,
252 ops:&generic_phy_ops
253}; 289};
254 290
255static struct mii_phy_def *mii_phy_table[] = { 291static struct mii_phy_def *mii_phy_table[] = {
@@ -258,39 +294,60 @@ static struct mii_phy_def *mii_phy_table[] = {
258 NULL 294 NULL
259}; 295};
260 296
261int mii_phy_probe(struct mii_phy *phy, int mii_id) 297int mii_phy_probe(struct mii_phy *phy, int address)
262{ 298{
263 int rc;
264 u32 id;
265 struct mii_phy_def *def; 299 struct mii_phy_def *def;
266 int i; 300 int i;
301 u32 id;
267 302
268 phy->autoneg = 0; 303 phy->autoneg = AUTONEG_DISABLE;
269 phy->advertising = 0; 304 phy->advertising = 0;
270 phy->mii_id = mii_id; 305 phy->address = address;
271 phy->speed = 0; 306 phy->speed = SPEED_10;
272 phy->duplex = 0; 307 phy->duplex = DUPLEX_HALF;
273 phy->pause = 0; 308 phy->pause = phy->asym_pause = 0;
274 309
275 /* Take PHY out of isloate mode and reset it. */ 310 /* Take PHY out of isolate mode and reset it. */
276 rc = reset_one_mii_phy(phy, mii_id); 311 if (mii_reset_phy(phy))
277 if (rc)
278 return -ENODEV; 312 return -ENODEV;
279 313
280 /* Read ID and find matching entry */ 314 /* Read ID and find matching entry */
281 id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2)) 315 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
282 & 0xfffffff0;
283 for (i = 0; (def = mii_phy_table[i]) != NULL; i++) 316 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
284 if ((id & def->phy_id_mask) == def->phy_id) 317 if ((id & def->phy_id_mask) == def->phy_id)
285 break; 318 break;
286 /* Should never be NULL (we have a generic entry), but... */ 319 /* Should never be NULL (we have a generic entry), but... */
287 if (def == NULL) 320 if (!def)
288 return -ENODEV; 321 return -ENODEV;
289 322
290 phy->def = def; 323 phy->def = def;
291 324
325 /* Determine PHY features if needed */
326 phy->features = def->features;
327 if (!phy->features) {
328 u16 bmsr = phy_read(phy, MII_BMSR);
329 if (bmsr & BMSR_ANEGCAPABLE)
330 phy->features |= SUPPORTED_Autoneg;
331 if (bmsr & BMSR_10HALF)
332 phy->features |= SUPPORTED_10baseT_Half;
333 if (bmsr & BMSR_10FULL)
334 phy->features |= SUPPORTED_10baseT_Full;
335 if (bmsr & BMSR_100HALF)
336 phy->features |= SUPPORTED_100baseT_Half;
337 if (bmsr & BMSR_100FULL)
338 phy->features |= SUPPORTED_100baseT_Full;
339 if (bmsr & BMSR_ESTATEN) {
340 u16 esr = phy_read(phy, MII_ESTATUS);
341 if (esr & ESTATUS_1000_TFULL)
342 phy->features |= SUPPORTED_1000baseT_Full;
343 if (esr & ESTATUS_1000_THALF)
344 phy->features |= SUPPORTED_1000baseT_Half;
345 }
346 phy->features |= SUPPORTED_MII;
347 }
348
292 /* Setup default advertising */ 349 /* Setup default advertising */
293 phy->advertising = def->features; 350 phy->advertising = phy->features;
294 351
295 return 0; 352 return 0;
296} 353}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-06 09:56:08 -0400