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-rw-r--r--arch/ppc/4xx_io/serial_sicc.c2
-rw-r--r--arch/ppc/Kconfig80
-rw-r--r--arch/ppc/Makefile3
-rw-r--r--arch/ppc/amiga/amiints.c40
-rw-r--r--arch/ppc/amiga/cia.c8
-rw-r--r--arch/ppc/amiga/config.c24
-rw-r--r--arch/ppc/boot/Makefile2
-rw-r--r--arch/ppc/boot/common/util.S6
-rw-r--r--arch/ppc/boot/images/Makefile2
-rw-r--r--arch/ppc/boot/openfirmware/Makefile96
-rw-r--r--arch/ppc/boot/openfirmware/coffmain.c101
-rw-r--r--arch/ppc/boot/openfirmware/newworldmain.c94
-rw-r--r--arch/ppc/boot/simple/Makefile6
-rw-r--r--arch/ppc/configs/TQM8540_defconfig973
-rw-r--r--arch/ppc/configs/TQM8541_defconfig986
-rw-r--r--arch/ppc/configs/TQM8555_defconfig983
-rw-r--r--arch/ppc/configs/TQM8560_defconfig992
-rw-r--r--arch/ppc/configs/bamboo_defconfig1
-rw-r--r--arch/ppc/configs/katana_defconfig1
-rw-r--r--arch/ppc/configs/mpc834x_sys_defconfig1
-rw-r--r--arch/ppc/configs/power3_defconfig1
-rw-r--r--arch/ppc/kernel/Makefile7
-rw-r--r--arch/ppc/kernel/align.c410
-rw-r--r--arch/ppc/kernel/asm-offsets.c2
-rw-r--r--arch/ppc/kernel/entry.S167
-rw-r--r--arch/ppc/kernel/head_8xx.S77
-rw-r--r--arch/ppc/kernel/head_fsl_booke.S2
-rw-r--r--arch/ppc/kernel/idle.c4
-rw-r--r--arch/ppc/kernel/machine_kexec.c6
-rw-r--r--arch/ppc/kernel/misc.S78
-rw-r--r--arch/ppc/kernel/pci.c290
-rw-r--r--arch/ppc/kernel/ppc_htab.c1
-rw-r--r--arch/ppc/kernel/ppc_ksyms.c17
-rw-r--r--arch/ppc/kernel/process.c845
-rw-r--r--arch/ppc/kernel/setup.c49
-rw-r--r--arch/ppc/kernel/smp.c8
-rw-r--r--arch/ppc/kernel/traps.c13
-rw-r--r--arch/ppc/mm/fsl_booke_mmu.c2
-rw-r--r--arch/ppc/mm/init.c52
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c2
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c1
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.c27
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.h2
-rw-r--r--arch/ppc/platforms/85xx/Kconfig28
-rw-r--r--arch/ppc/platforms/85xx/Makefile4
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c16
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.h2
-rw-r--r--arch/ppc/platforms/85xx/mpc8555_cds.h2
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c13
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.h2
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.c2
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.h4
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c32
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.h2
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c12
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c10
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.h2
-rw-r--r--arch/ppc/platforms/85xx/tqm85xx.c415
-rw-r--r--arch/ppc/platforms/85xx/tqm85xx.h56
-rw-r--r--arch/ppc/platforms/Makefile11
-rw-r--r--arch/ppc/platforms/apus_setup.c30
-rw-r--r--arch/ppc/platforms/chrp_pci.c2
-rw-r--r--arch/ppc/platforms/chrp_setup.c74
-rw-r--r--arch/ppc/platforms/chrp_time.c64
-rw-r--r--arch/ppc/platforms/lite5200.c2
-rw-r--r--arch/ppc/platforms/mpc5200.c53
-rw-r--r--arch/ppc/platforms/pmac_backlight.c202
-rw-r--r--arch/ppc/platforms/pmac_cache.S359
-rw-r--r--arch/ppc/platforms/pmac_cpufreq.c735
-rw-r--r--arch/ppc/platforms/pmac_feature.c3005
-rw-r--r--arch/ppc/platforms/pmac_low_i2c.c511
-rw-r--r--arch/ppc/platforms/pmac_nvram.c584
-rw-r--r--arch/ppc/platforms/pmac_pci.c1124
-rw-r--r--arch/ppc/platforms/pmac_pic.c693
-rw-r--r--arch/ppc/platforms/pmac_pic.h11
-rw-r--r--arch/ppc/platforms/pmac_setup.c745
-rw-r--r--arch/ppc/platforms/pmac_sleep.S396
-rw-r--r--arch/ppc/platforms/pmac_smp.c692
-rw-r--r--arch/ppc/platforms/pmac_time.c291
-rw-r--r--arch/ppc/platforms/pq2ads.c2
-rw-r--r--arch/ppc/platforms/prep_setup.c2
-rw-r--r--arch/ppc/syslib/Makefile4
-rw-r--r--arch/ppc/syslib/ipic.c646
-rw-r--r--arch/ppc/syslib/ipic.h49
-rw-r--r--arch/ppc/syslib/m82xx_pci.c3
-rw-r--r--arch/ppc/syslib/m8xx_setup.c15
-rw-r--r--arch/ppc/syslib/m8xx_wdt.c92
-rw-r--r--arch/ppc/syslib/m8xx_wdt.h4
-rw-r--r--arch/ppc/syslib/mpc52xx_pci.c95
-rw-r--r--arch/ppc/syslib/mpc52xx_setup.c6
-rw-r--r--arch/ppc/syslib/mpc83xx_devices.c12
-rw-r--r--arch/ppc/syslib/mpc83xx_sys.c30
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c12
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c2
-rw-r--r--arch/ppc/syslib/mpc8xx_devices.c2
-rw-r--r--arch/ppc/syslib/mpc8xx_sys.c2
-rw-r--r--arch/ppc/syslib/ocp.c4
-rw-r--r--arch/ppc/syslib/ppc4xx_dma.c1
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c2
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.h2
-rw-r--r--arch/ppc/syslib/ppc85xx_common.c2
-rw-r--r--arch/ppc/syslib/ppc85xx_common.h2
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c2
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.h2
-rw-r--r--arch/ppc/syslib/ppc_sys.c2
-rw-r--r--arch/ppc/syslib/pq2_devices.c2
-rw-r--r--arch/ppc/syslib/pq2_sys.c2
-rw-r--r--arch/ppc/syslib/prom.c21
-rw-r--r--arch/ppc/xmon/start.c162
-rw-r--r--arch/ppc/xmon/xmon.c15
110 files changed, 5235 insertions, 12614 deletions
diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c
index 84d96b857e..8ace2a1f3b 100644
--- a/arch/ppc/4xx_io/serial_sicc.c
+++ b/arch/ppc/4xx_io/serial_sicc.c
@@ -47,6 +47,7 @@
47#include <linux/mm.h> 47#include <linux/mm.h>
48#include <linux/slab.h> 48#include <linux/slab.h>
49#include <linux/init.h> 49#include <linux/init.h>
50#include <linux/capability.h>
50#include <linux/circ_buf.h> 51#include <linux/circ_buf.h>
51#include <linux/serial.h> 52#include <linux/serial.h>
52#include <linux/console.h> 53#include <linux/console.h>
@@ -214,7 +215,6 @@ static struct tty_driver *siccnormal_driver;
214 * memory if large numbers of serial ports are open. 215 * memory if large numbers of serial ports are open.
215 */ 216 */
216static u_char *tmp_buf; 217static u_char *tmp_buf;
217static DECLARE_MUTEX(tmp_buf_sem);
218 218
219#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) 219#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
220 220
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 8fa51b0a32..11899f06bf 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -8,9 +8,6 @@ config MMU
8 bool 8 bool
9 default y 9 default y
10 10
11config UID16
12 bool
13
14config GENERIC_HARDIRQS 11config GENERIC_HARDIRQS
15 bool 12 bool
16 default y 13 default y
@@ -61,11 +58,11 @@ config 6xx
61 help 58 help
62 There are four types of PowerPC chips supported. The more common 59 There are four types of PowerPC chips supported. The more common
63 types (601, 603, 604, 740, 750, 7400), the Motorola embedded 60 types (601, 603, 604, 740, 750, 7400), the Motorola embedded
64 versions (821, 823, 850, 855, 860, 52xx, 82xx, 83xx), the IBM embedded 61 versions (821, 823, 850, 855, 860, 52xx, 82xx, 83xx), the IBM
65 versions (403 and 405) and the high end 64 bit Power processors 62 embedded versions (403 and 405) and the POWER3 processor.
66 (POWER 3, POWER4, and IBM 970 also known as G5) 63 (For support for more recent 64-bit processors, set ARCH=powerpc.)
67 Unless you are building a kernel for one of the embedded processor 64 Unless you are building a kernel for one of the embedded processor
68 systems, 64 bit IBM RS/6000 or an Apple G5, choose 6xx. 65 systems or a POWER3-based IBM RS/6000, choose 6xx.
69 Note that the kernel runs in 32-bit mode even on 64-bit chips. 66 Note that the kernel runs in 32-bit mode even on 64-bit chips.
70 Also note that because the 52xx, 82xx, & 83xx family has a 603e core, 67 Also note that because the 52xx, 82xx, & 83xx family has a 603e core,
71 specific support for that chipset is asked later on. 68 specific support for that chipset is asked later on.
@@ -80,10 +77,6 @@ config POWER3
80 select PPC_FPU 77 select PPC_FPU
81 bool "POWER3" 78 bool "POWER3"
82 79
83config POWER4
84 select PPC_FPU
85 bool "POWER4 and 970 (G5)"
86
87config 8xx 80config 8xx
88 bool "8xx" 81 bool "8xx"
89 82
@@ -126,7 +119,7 @@ config PHYS_64BIT
126 119
127config ALTIVEC 120config ALTIVEC
128 bool "AltiVec Support" 121 bool "AltiVec Support"
129 depends on 6xx || POWER4 122 depends on 6xx
130 depends on !8260 && !83xx 123 depends on !8260 && !83xx
131 ---help--- 124 ---help---
132 This option enables kernel support for the Altivec extensions to the 125 This option enables kernel support for the Altivec extensions to the
@@ -238,18 +231,9 @@ config KEXEC
238 231
239source "drivers/cpufreq/Kconfig" 232source "drivers/cpufreq/Kconfig"
240 233
241config CPU_FREQ_PMAC
242 bool "Support for Apple PowerBooks"
243 depends on CPU_FREQ && ADB_PMU
244 select CPU_FREQ_TABLE
245 help
246 This adds support for frequency switching on Apple PowerBooks,
247 this currently includes some models of iBook & Titanium
248 PowerBook.
249
250config PPC601_SYNC_FIX 234config PPC601_SYNC_FIX
251 bool "Workarounds for PPC601 bugs" 235 bool "Workarounds for PPC601 bugs"
252 depends on 6xx && (PPC_PREP || PPC_PMAC) 236 depends on 6xx && PPC_PREP
253 help 237 help
254 Some versions of the PPC601 (the first PowerPC chip) have bugs which 238 Some versions of the PPC601 (the first PowerPC chip) have bugs which
255 mean that extra synchronization instructions are required near 239 mean that extra synchronization instructions are required near
@@ -261,26 +245,17 @@ config PPC601_SYNC_FIX
261 245
262 If in doubt, say Y here. 246 If in doubt, say Y here.
263 247
264config HOTPLUG_CPU
265 bool "Support for enabling/disabling CPUs"
266 depends on SMP && HOTPLUG && EXPERIMENTAL && PPC_PMAC
267 ---help---
268 Say Y here to be able to disable and re-enable individual
269 CPUs at runtime on SMP machines.
270
271 Say N if you are unsure.
272
273source arch/ppc/platforms/4xx/Kconfig 248source arch/ppc/platforms/4xx/Kconfig
274source arch/ppc/platforms/85xx/Kconfig 249source arch/ppc/platforms/85xx/Kconfig
275 250
276config PPC64BRIDGE 251config PPC64BRIDGE
277 bool 252 bool
278 depends on POWER3 || POWER4 253 depends on POWER3
279 default y 254 default y
280 255
281config PPC_STD_MMU 256config PPC_STD_MMU
282 bool 257 bool
283 depends on 6xx || POWER3 || POWER4 258 depends on 6xx || POWER3
284 default y 259 default y
285 260
286config NOT_COHERENT_CACHE 261config NOT_COHERENT_CACHE
@@ -508,7 +483,7 @@ endchoice
508 483
509choice 484choice
510 prompt "Machine Type" 485 prompt "Machine Type"
511 depends on 6xx || POWER3 || POWER4 486 depends on 6xx || POWER3
512 default PPC_MULTIPLATFORM 487 default PPC_MULTIPLATFORM
513 ---help--- 488 ---help---
514 Linux currently supports several different kinds of PowerPC-based 489 Linux currently supports several different kinds of PowerPC-based
@@ -519,11 +494,15 @@ choice
519 Platform) machines (including all of the recent IBM RS/6000 and 494 Platform) machines (including all of the recent IBM RS/6000 and
520 pSeries machines), and several embedded PowerPC systems containing 495 pSeries machines), and several embedded PowerPC systems containing
521 4xx, 6xx, 7xx, 8xx, 74xx, and 82xx processors. Currently, the 496 4xx, 6xx, 7xx, 8xx, 74xx, and 82xx processors. Currently, the
522 default option is to build a kernel which works on the first three. 497 default option is to build a kernel which works on PReP and CHRP.
523 498
524 Select CHRP/PowerMac/PReP if configuring for an IBM RS/6000 or 499 Note that support for Apple machines is now only available with
525 pSeries machine, a Power Macintosh (including iMacs, iBooks and 500 ARCH=powerpc, and has been removed from this menu. If you wish
526 Powerbooks), or a PReP machine. 501 to build a kernel for an Apple machine, exit this configuration
502 process and re-run it with ARCH=powerpc.
503
504 Select CHRP/PReP if configuring for an IBM RS/6000 or
505 pSeries machine, or a PReP machine.
527 506
528 Select Gemini if configuring for a Synergy Microsystems' Gemini 507 Select Gemini if configuring for a Synergy Microsystems' Gemini
529 series Single Board Computer. More information is available at: 508 series Single Board Computer. More information is available at:
@@ -533,7 +512,7 @@ choice
533 available at: <http://linux-apus.sourceforge.net/>. 512 available at: <http://linux-apus.sourceforge.net/>.
534 513
535config PPC_MULTIPLATFORM 514config PPC_MULTIPLATFORM
536 bool "CHRP/PowerMac/PReP" 515 bool "CHRP/PReP"
537 516
538config APUS 517config APUS
539 bool "Amiga-APUS" 518 bool "Amiga-APUS"
@@ -746,6 +725,10 @@ config MPC834x
746 bool 725 bool
747 default y if MPC834x_SYS 726 default y if MPC834x_SYS
748 727
728config PPC_83xx
729 bool
730 default y if 83xx
731
749config CPM1 732config CPM1
750 bool 733 bool
751 depends on 8xx 734 depends on 8xx
@@ -767,25 +750,14 @@ config CPM2
767 on it (826x, 827x, 8560). 750 on it (826x, 827x, 8560).
768 751
769config PPC_CHRP 752config PPC_CHRP
770 bool " Common Hardware Reference Platform (CHRP) based machines" 753 bool "Support for CHRP (Common Hardware Reference Platform) machines"
771 depends on PPC_MULTIPLATFORM 754 depends on PPC_MULTIPLATFORM
772 select PPC_I8259 755 select PPC_I8259
773 select PPC_INDIRECT_PCI 756 select PPC_INDIRECT_PCI
774 default y 757 default y
775 758
776config PPC_PMAC
777 bool " Apple PowerMac based machines"
778 depends on PPC_MULTIPLATFORM
779 select PPC_INDIRECT_PCI
780 default y
781
782config PPC_PMAC64
783 bool
784 depends on PPC_PMAC && POWER4
785 default y
786
787config PPC_PREP 759config PPC_PREP
788 bool " PowerPC Reference Platform (PReP) based machines" 760 bool "Support for PReP (PowerPC Reference Platform) machines"
789 depends on PPC_MULTIPLATFORM 761 depends on PPC_MULTIPLATFORM
790 select PPC_I8259 762 select PPC_I8259
791 select PPC_INDIRECT_PCI 763 select PPC_INDIRECT_PCI
@@ -793,7 +765,7 @@ config PPC_PREP
793 765
794config PPC_OF 766config PPC_OF
795 bool 767 bool
796 depends on PPC_PMAC || PPC_CHRP 768 depends on PPC_CHRP
797 default y 769 default y
798 770
799config PPC_GEN550 771config PPC_GEN550
@@ -1165,7 +1137,7 @@ config ISA
1165 1137
1166config GENERIC_ISA_DMA 1138config GENERIC_ISA_DMA
1167 bool 1139 bool
1168 depends on POWER3 || POWER4 || 6xx && !CPM2 1140 depends on POWER3 || 6xx && !CPM2
1169 default y 1141 default y
1170 1142
1171config PPC_I8259 1143config PPC_I8259
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile
index e719a4933a..98e940beeb 100644
--- a/arch/ppc/Makefile
+++ b/arch/ppc/Makefile
@@ -128,10 +128,9 @@ TOUT := .tmp_gas_check
128# Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later for altivec 128# Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later for altivec
129# instructions. 129# instructions.
130# gcc-3.4 and binutils-2.14 are a fatal combination. 130# gcc-3.4 and binutils-2.14 are a fatal combination.
131GCC_VERSION := $(call cc-version)
132 131
133checkbin: 132checkbin:
134 @if test "$(GCC_VERSION)" = "0304" ; then \ 133 @if test "$(call cc-version)" = "0304" ; then \
135 if ! /bin/echo mftb 5 | $(AS) -v -mppc -many -o $(TOUT) >/dev/null 2>&1 ; then \ 134 if ! /bin/echo mftb 5 | $(AS) -v -mppc -many -o $(TOUT) >/dev/null 2>&1 ; then \
136 echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build '; \ 135 echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build '; \
137 echo 'correctly with gcc-3.4 and your version of binutils.'; \ 136 echo 'correctly with gcc-3.4 and your version of binutils.'; \
diff --git a/arch/ppc/amiga/amiints.c b/arch/ppc/amiga/amiints.c
index 91195e2ce3..5f35cf3986 100644
--- a/arch/ppc/amiga/amiints.c
+++ b/arch/ppc/amiga/amiints.c
@@ -96,8 +96,8 @@ void amiga_init_IRQ(void)
96 gayle.inten = GAYLE_IRQ_IDE; 96 gayle.inten = GAYLE_IRQ_IDE;
97 97
98 /* turn off all interrupts... */ 98 /* turn off all interrupts... */
99 custom.intena = 0x7fff; 99 amiga_custom.intena = 0x7fff;
100 custom.intreq = 0x7fff; 100 amiga_custom.intreq = 0x7fff;
101 101
102#ifdef CONFIG_APUS 102#ifdef CONFIG_APUS
103 /* Clear any inter-CPU interrupt requests. Circumvents bug in 103 /* Clear any inter-CPU interrupt requests. Circumvents bug in
@@ -110,7 +110,7 @@ void amiga_init_IRQ(void)
110 APUS_WRITE(APUS_IPL_EMU, IPLEMU_SETRESET | IPLEMU_IPLMASK); 110 APUS_WRITE(APUS_IPL_EMU, IPLEMU_SETRESET | IPLEMU_IPLMASK);
111#endif 111#endif
112 /* ... and enable the master interrupt bit */ 112 /* ... and enable the master interrupt bit */
113 custom.intena = IF_SETCLR | IF_INTEN; 113 amiga_custom.intena = IF_SETCLR | IF_INTEN;
114 114
115 cia_init_IRQ(&ciaa_base); 115 cia_init_IRQ(&ciaa_base);
116 cia_init_IRQ(&ciab_base); 116 cia_init_IRQ(&ciab_base);
@@ -151,7 +151,7 @@ void amiga_enable_irq(unsigned int irq)
151 } 151 }
152 152
153 /* enable the interrupt */ 153 /* enable the interrupt */
154 custom.intena = IF_SETCLR | ami_intena_vals[irq]; 154 amiga_custom.intena = IF_SETCLR | ami_intena_vals[irq];
155} 155}
156 156
157void amiga_disable_irq(unsigned int irq) 157void amiga_disable_irq(unsigned int irq)
@@ -177,7 +177,7 @@ void amiga_disable_irq(unsigned int irq)
177 } 177 }
178 178
179 /* disable the interrupt */ 179 /* disable the interrupt */
180 custom.intena = ami_intena_vals[irq]; 180 amiga_custom.intena = ami_intena_vals[irq];
181} 181}
182 182
183inline void amiga_do_irq(int irq, struct pt_regs *fp) 183inline void amiga_do_irq(int irq, struct pt_regs *fp)
@@ -196,7 +196,7 @@ void amiga_do_irq_list(int irq, struct pt_regs *fp)
196 196
197 kstat_cpu(0).irqs[irq]++; 197 kstat_cpu(0).irqs[irq]++;
198 198
199 custom.intreq = ami_intena_vals[irq]; 199 amiga_custom.intreq = ami_intena_vals[irq];
200 200
201 for (action = desc->action; action; action = action->next) 201 for (action = desc->action; action; action = action->next)
202 action->handler(irq, action->dev_id, fp); 202 action->handler(irq, action->dev_id, fp);
@@ -208,40 +208,40 @@ void amiga_do_irq_list(int irq, struct pt_regs *fp)
208 208
209static void ami_int1(int irq, void *dev_id, struct pt_regs *fp) 209static void ami_int1(int irq, void *dev_id, struct pt_regs *fp)
210{ 210{
211 unsigned short ints = custom.intreqr & custom.intenar; 211 unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
212 212
213 /* if serial transmit buffer empty, interrupt */ 213 /* if serial transmit buffer empty, interrupt */
214 if (ints & IF_TBE) { 214 if (ints & IF_TBE) {
215 custom.intreq = IF_TBE; 215 amiga_custom.intreq = IF_TBE;
216 amiga_do_irq(IRQ_AMIGA_TBE, fp); 216 amiga_do_irq(IRQ_AMIGA_TBE, fp);
217 } 217 }
218 218
219 /* if floppy disk transfer complete, interrupt */ 219 /* if floppy disk transfer complete, interrupt */
220 if (ints & IF_DSKBLK) { 220 if (ints & IF_DSKBLK) {
221 custom.intreq = IF_DSKBLK; 221 amiga_custom.intreq = IF_DSKBLK;
222 amiga_do_irq(IRQ_AMIGA_DSKBLK, fp); 222 amiga_do_irq(IRQ_AMIGA_DSKBLK, fp);
223 } 223 }
224 224
225 /* if software interrupt set, interrupt */ 225 /* if software interrupt set, interrupt */
226 if (ints & IF_SOFT) { 226 if (ints & IF_SOFT) {
227 custom.intreq = IF_SOFT; 227 amiga_custom.intreq = IF_SOFT;
228 amiga_do_irq(IRQ_AMIGA_SOFT, fp); 228 amiga_do_irq(IRQ_AMIGA_SOFT, fp);
229 } 229 }
230} 230}
231 231
232static void ami_int3(int irq, void *dev_id, struct pt_regs *fp) 232static void ami_int3(int irq, void *dev_id, struct pt_regs *fp)
233{ 233{
234 unsigned short ints = custom.intreqr & custom.intenar; 234 unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
235 235
236 /* if a blitter interrupt */ 236 /* if a blitter interrupt */
237 if (ints & IF_BLIT) { 237 if (ints & IF_BLIT) {
238 custom.intreq = IF_BLIT; 238 amiga_custom.intreq = IF_BLIT;
239 amiga_do_irq(IRQ_AMIGA_BLIT, fp); 239 amiga_do_irq(IRQ_AMIGA_BLIT, fp);
240 } 240 }
241 241
242 /* if a copper interrupt */ 242 /* if a copper interrupt */
243 if (ints & IF_COPER) { 243 if (ints & IF_COPER) {
244 custom.intreq = IF_COPER; 244 amiga_custom.intreq = IF_COPER;
245 amiga_do_irq(IRQ_AMIGA_COPPER, fp); 245 amiga_do_irq(IRQ_AMIGA_COPPER, fp);
246 } 246 }
247 247
@@ -252,36 +252,36 @@ static void ami_int3(int irq, void *dev_id, struct pt_regs *fp)
252 252
253static void ami_int4(int irq, void *dev_id, struct pt_regs *fp) 253static void ami_int4(int irq, void *dev_id, struct pt_regs *fp)
254{ 254{
255 unsigned short ints = custom.intreqr & custom.intenar; 255 unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
256 256
257 /* if audio 0 interrupt */ 257 /* if audio 0 interrupt */
258 if (ints & IF_AUD0) { 258 if (ints & IF_AUD0) {
259 custom.intreq = IF_AUD0; 259 amiga_custom.intreq = IF_AUD0;
260 amiga_do_irq(IRQ_AMIGA_AUD0, fp); 260 amiga_do_irq(IRQ_AMIGA_AUD0, fp);
261 } 261 }
262 262
263 /* if audio 1 interrupt */ 263 /* if audio 1 interrupt */
264 if (ints & IF_AUD1) { 264 if (ints & IF_AUD1) {
265 custom.intreq = IF_AUD1; 265 amiga_custom.intreq = IF_AUD1;
266 amiga_do_irq(IRQ_AMIGA_AUD1, fp); 266 amiga_do_irq(IRQ_AMIGA_AUD1, fp);
267 } 267 }
268 268
269 /* if audio 2 interrupt */ 269 /* if audio 2 interrupt */
270 if (ints & IF_AUD2) { 270 if (ints & IF_AUD2) {
271 custom.intreq = IF_AUD2; 271 amiga_custom.intreq = IF_AUD2;
272 amiga_do_irq(IRQ_AMIGA_AUD2, fp); 272 amiga_do_irq(IRQ_AMIGA_AUD2, fp);
273 } 273 }
274 274
275 /* if audio 3 interrupt */ 275 /* if audio 3 interrupt */
276 if (ints & IF_AUD3) { 276 if (ints & IF_AUD3) {
277 custom.intreq = IF_AUD3; 277 amiga_custom.intreq = IF_AUD3;
278 amiga_do_irq(IRQ_AMIGA_AUD3, fp); 278 amiga_do_irq(IRQ_AMIGA_AUD3, fp);
279 } 279 }
280} 280}
281 281
282static void ami_int5(int irq, void *dev_id, struct pt_regs *fp) 282static void ami_int5(int irq, void *dev_id, struct pt_regs *fp)
283{ 283{
284 unsigned short ints = custom.intreqr & custom.intenar; 284 unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
285 285
286 /* if serial receive buffer full interrupt */ 286 /* if serial receive buffer full interrupt */
287 if (ints & IF_RBF) { 287 if (ints & IF_RBF) {
@@ -291,7 +291,7 @@ static void ami_int5(int irq, void *dev_id, struct pt_regs *fp)
291 291
292 /* if a disk sync interrupt */ 292 /* if a disk sync interrupt */
293 if (ints & IF_DSKSYN) { 293 if (ints & IF_DSKSYN) {
294 custom.intreq = IF_DSKSYN; 294 amiga_custom.intreq = IF_DSKSYN;
295 amiga_do_irq(IRQ_AMIGA_DSKSYN, fp); 295 amiga_do_irq(IRQ_AMIGA_DSKSYN, fp);
296 } 296 }
297} 297}
diff --git a/arch/ppc/amiga/cia.c b/arch/ppc/amiga/cia.c
index ad961465b6..4431c58f61 100644
--- a/arch/ppc/amiga/cia.c
+++ b/arch/ppc/amiga/cia.c
@@ -66,7 +66,7 @@ static unsigned char cia_set_irq_private(struct ciabase *base,
66 else 66 else
67 base->icr_data &= ~mask; 67 base->icr_data &= ~mask;
68 if (base->icr_data & base->icr_mask) 68 if (base->icr_data & base->icr_mask)
69 custom.intreq = IF_SETCLR | base->int_mask; 69 amiga_custom.intreq = IF_SETCLR | base->int_mask;
70 return old & base->icr_mask; 70 return old & base->icr_mask;
71} 71}
72 72
@@ -114,7 +114,7 @@ static unsigned char cia_able_irq_private(struct ciabase *base,
114 base->icr_mask &= CIA_ICR_ALL; 114 base->icr_mask &= CIA_ICR_ALL;
115 115
116 if (base->icr_data & base->icr_mask) 116 if (base->icr_data & base->icr_mask)
117 custom.intreq = IF_SETCLR | base->int_mask; 117 amiga_custom.intreq = IF_SETCLR | base->int_mask;
118 return old; 118 return old;
119} 119}
120 120
@@ -145,7 +145,7 @@ static void cia_handler(int irq, void *dev_id, struct pt_regs *fp)
145 irq = base->cia_irq; 145 irq = base->cia_irq;
146 desc = irq_desc + irq; 146 desc = irq_desc + irq;
147 ints = cia_set_irq_private(base, CIA_ICR_ALL); 147 ints = cia_set_irq_private(base, CIA_ICR_ALL);
148 custom.intreq = base->int_mask; 148 amiga_custom.intreq = base->int_mask;
149 for (i = 0; i < CIA_IRQS; i++, irq++) { 149 for (i = 0; i < CIA_IRQS; i++, irq++) {
150 if (ints & 1) { 150 if (ints & 1) {
151 kstat_cpu(0).irqs[irq]++; 151 kstat_cpu(0).irqs[irq]++;
@@ -174,5 +174,5 @@ void __init cia_init_IRQ(struct ciabase *base)
174 action->name = base->name; 174 action->name = base->name;
175 setup_irq(base->handler_irq, &amiga_sys_irqaction[base->handler_irq-IRQ_AMIGA_AUTO]); 175 setup_irq(base->handler_irq, &amiga_sys_irqaction[base->handler_irq-IRQ_AMIGA_AUTO]);
176 176
177 custom.intena = IF_SETCLR | base->int_mask; 177 amiga_custom.intena = IF_SETCLR | base->int_mask;
178} 178}
diff --git a/arch/ppc/amiga/config.c b/arch/ppc/amiga/config.c
index af881d7454..60e2da1c92 100644
--- a/arch/ppc/amiga/config.c
+++ b/arch/ppc/amiga/config.c
@@ -90,9 +90,6 @@ static void a3000_gettod (int *, int *, int *, int *, int *, int *);
90static void a2000_gettod (int *, int *, int *, int *, int *, int *); 90static void a2000_gettod (int *, int *, int *, int *, int *, int *);
91static int amiga_hwclk (int, struct hwclk_time *); 91static int amiga_hwclk (int, struct hwclk_time *);
92static int amiga_set_clock_mmss (unsigned long); 92static int amiga_set_clock_mmss (unsigned long);
93#ifdef CONFIG_AMIGA_FLOPPY
94extern void amiga_floppy_setup(char *, int *);
95#endif
96static void amiga_reset (void); 93static void amiga_reset (void);
97extern void amiga_init_sound(void); 94extern void amiga_init_sound(void);
98static void amiga_savekmsg_init(void); 95static void amiga_savekmsg_init(void);
@@ -281,7 +278,7 @@ static void __init amiga_identify(void)
281 case CS_OCS: 278 case CS_OCS:
282 case CS_ECS: 279 case CS_ECS:
283 case CS_AGA: 280 case CS_AGA:
284 switch (custom.deniseid & 0xf) { 281 switch (amiga_custom.deniseid & 0xf) {
285 case 0x0c: 282 case 0x0c:
286 AMIGAHW_SET(DENISE_HR); 283 AMIGAHW_SET(DENISE_HR);
287 break; 284 break;
@@ -294,7 +291,7 @@ static void __init amiga_identify(void)
294 AMIGAHW_SET(DENISE); 291 AMIGAHW_SET(DENISE);
295 break; 292 break;
296 } 293 }
297 switch ((custom.vposr>>8) & 0x7f) { 294 switch ((amiga_custom.vposr>>8) & 0x7f) {
298 case 0x00: 295 case 0x00:
299 AMIGAHW_SET(AGNUS_PAL); 296 AMIGAHW_SET(AGNUS_PAL);
300 break; 297 break;
@@ -419,9 +416,6 @@ void __init config_amiga(void)
419 416
420 mach_hwclk = amiga_hwclk; 417 mach_hwclk = amiga_hwclk;
421 mach_set_clock_mmss = amiga_set_clock_mmss; 418 mach_set_clock_mmss = amiga_set_clock_mmss;
422#ifdef CONFIG_AMIGA_FLOPPY
423 mach_floppy_setup = amiga_floppy_setup;
424#endif
425 mach_reset = amiga_reset; 419 mach_reset = amiga_reset;
426#ifdef CONFIG_HEARTBEAT 420#ifdef CONFIG_HEARTBEAT
427 mach_heartbeat = amiga_heartbeat; 421 mach_heartbeat = amiga_heartbeat;
@@ -432,9 +426,9 @@ void __init config_amiga(void)
432 amiga_colorclock = 5*amiga_eclock; /* 3.5 MHz */ 426 amiga_colorclock = 5*amiga_eclock; /* 3.5 MHz */
433 427
434 /* clear all DMA bits */ 428 /* clear all DMA bits */
435 custom.dmacon = DMAF_ALL; 429 amiga_custom.dmacon = DMAF_ALL;
436 /* ensure that the DMA master bit is set */ 430 /* ensure that the DMA master bit is set */
437 custom.dmacon = DMAF_SETCLR | DMAF_MASTER; 431 amiga_custom.dmacon = DMAF_SETCLR | DMAF_MASTER;
438 432
439 /* request all RAM */ 433 /* request all RAM */
440 for (i = 0; i < m68k_num_memory; i++) { 434 for (i = 0; i < m68k_num_memory; i++) {
@@ -753,9 +747,9 @@ static void amiga_savekmsg_init(void)
753 747
754static void amiga_serial_putc(char c) 748static void amiga_serial_putc(char c)
755{ 749{
756 custom.serdat = (unsigned char)c | 0x100; 750 amiga_custom.serdat = (unsigned char)c | 0x100;
757 mb(); 751 mb();
758 while (!(custom.serdatr & 0x2000)) 752 while (!(amiga_custom.serdatr & 0x2000))
759 ; 753 ;
760} 754}
761 755
@@ -785,11 +779,11 @@ int amiga_serial_console_wait_key(struct console *co)
785{ 779{
786 int ch; 780 int ch;
787 781
788 while (!(custom.intreqr & IF_RBF)) 782 while (!(amiga_custom.intreqr & IF_RBF))
789 barrier(); 783 barrier();
790 ch = custom.serdatr & 0xff; 784 ch = amiga_custom.serdatr & 0xff;
791 /* clear the interrupt, so that another character can be read */ 785 /* clear the interrupt, so that another character can be read */
792 custom.intreq = IF_RBF; 786 amiga_custom.intreq = IF_RBF;
793 return ch; 787 return ch;
794} 788}
795 789
diff --git a/arch/ppc/boot/Makefile b/arch/ppc/boot/Makefile
index 995f89bb04..efd8ce515d 100644
--- a/arch/ppc/boot/Makefile
+++ b/arch/ppc/boot/Makefile
@@ -18,7 +18,7 @@ BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd
18bootdir-y := simple 18bootdir-y := simple
19bootdir-$(CONFIG_PPC_OF) += openfirmware 19bootdir-$(CONFIG_PPC_OF) += openfirmware
20subdir-y := lib common images 20subdir-y := lib common images
21subdir-$(CONFIG_PPC_OF) += of1275 21subdir-$(CONFIG_PPC_MULTIPLATFORM) += of1275
22 22
23# for cleaning 23# for cleaning
24subdir- += simple openfirmware 24subdir- += simple openfirmware
diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S
index c96c9f8052..368ec035e6 100644
--- a/arch/ppc/boot/common/util.S
+++ b/arch/ppc/boot/common/util.S
@@ -234,7 +234,8 @@ udelay:
234 * First, flush the data cache in case it was enabled and may be 234 * First, flush the data cache in case it was enabled and may be
235 * holding instructions for copy back. 235 * holding instructions for copy back.
236 */ 236 */
237_GLOBAL(flush_instruction_cache) 237 .globl flush_instruction_cache
238flush_instruction_cache:
238 mflr r6 239 mflr r6
239 bl flush_data_cache 240 bl flush_data_cache
240 241
@@ -279,7 +280,8 @@ _GLOBAL(flush_instruction_cache)
279 * Flush data cache 280 * Flush data cache
280 * Do this by just reading lots of stuff into the cache. 281 * Do this by just reading lots of stuff into the cache.
281 */ 282 */
282_GLOBAL(flush_data_cache) 283 .globl flush_data_cache
284flush_data_cache:
283 lis r3,cache_flush_buffer@h 285 lis r3,cache_flush_buffer@h
284 ori r3,r3,cache_flush_buffer@l 286 ori r3,r3,cache_flush_buffer@l
285 li r4,NUM_CACHE_LINES 287 li r4,NUM_CACHE_LINES
diff --git a/arch/ppc/boot/images/Makefile b/arch/ppc/boot/images/Makefile
index 532e7ef1ed..58415d5718 100644
--- a/arch/ppc/boot/images/Makefile
+++ b/arch/ppc/boot/images/Makefile
@@ -26,7 +26,7 @@ quiet_cmd_uimage = UIMAGE $@
26targets += uImage 26targets += uImage
27$(obj)/uImage: $(obj)/vmlinux.gz 27$(obj)/uImage: $(obj)/vmlinux.gz
28 $(Q)rm -f $@ 28 $(Q)rm -f $@
29 $(call if_changed,uimage) 29 $(call cmd,uimage)
30 @echo -n ' Image: $@ ' 30 @echo -n ' Image: $@ '
31 @if [ -f $@ ]; then echo 'is ready' ; else echo 'not made'; fi 31 @if [ -f $@ ]; then echo 'is ready' ; else echo 'not made'; fi
32 32
diff --git a/arch/ppc/boot/openfirmware/Makefile b/arch/ppc/boot/openfirmware/Makefile
index 83a6433459..2a411ec2e6 100644
--- a/arch/ppc/boot/openfirmware/Makefile
+++ b/arch/ppc/boot/openfirmware/Makefile
@@ -21,26 +21,16 @@ bootlib := $(boot)/lib
21of1275 := $(boot)/of1275 21of1275 := $(boot)/of1275
22images := $(boot)/images 22images := $(boot)/images
23 23
24OBJCOPY_ARGS := -O aixcoff-rs6000 -R .stab -R .stabstr -R .comment
25COFF_LD_ARGS := -T $(srctree)/$(boot)/ld.script -e _start -Ttext 0x00500000 \
26 -Bstatic
27CHRP_LD_ARGS := -T $(srctree)/$(boot)/ld.script -e _start -Ttext 0x00800000 24CHRP_LD_ARGS := -T $(srctree)/$(boot)/ld.script -e _start -Ttext 0x00800000
28NEWWORLD_LD_ARGS:= -T $(srctree)/$(boot)/ld.script -e _start -Ttext 0x01000000
29 25
30COMMONOBJS := start.o misc.o common.o 26COMMONOBJS := start.o misc.o common.o
31COFFOBJS := coffcrt0.o $(COMMONOBJS) coffmain.o
32CHRPOBJS := crt0.o $(COMMONOBJS) chrpmain.o 27CHRPOBJS := crt0.o $(COMMONOBJS) chrpmain.o
33NEWWORLDOBJS := crt0.o $(COMMONOBJS) newworldmain.o
34 28
35targets := $(COFFOBJS) $(CHRPOBJS) $(NEWWORLDOBJS) dummy.o 29targets := $(CHRPOBJS) dummy.o
36COFFOBJS := $(addprefix $(obj)/, $(COFFOBJS))
37CHRPOBJS := $(addprefix $(obj)/, $(CHRPOBJS)) 30CHRPOBJS := $(addprefix $(obj)/, $(CHRPOBJS))
38NEWWORLDOBJS := $(addprefix $(obj)/, $(NEWWORLDOBJS))
39 31
40LIBS := lib/lib.a $(bootlib)/lib.a $(of1275)/lib.a $(common)/lib.a 32LIBS := lib/lib.a $(bootlib)/lib.a $(of1275)/lib.a $(common)/lib.a
41 33
42HACKCOFF := $(utils)/hack-coff
43
44ifdef CONFIG_SMP 34ifdef CONFIG_SMP
45END := .smp 35END := .smp
46endif 36endif
@@ -72,56 +62,11 @@ targets += image.initrd.o
72$(obj)/image.initrd.o: $(obj)/image.o $(images)/ramdisk.image.gz FORCE 62$(obj)/image.initrd.o: $(obj)/image.o $(images)/ramdisk.image.gz FORCE
73 $(call if_changed,genimage-initrd) 63 $(call if_changed,genimage-initrd)
74 64
75# Create the note section for New-World PowerMacs.
76quiet_cmd_mknote = MKNOTE $@
77 cmd_mknote = $(utils)/mknote > $@
78targets += note
79$(obj)/note: $(utils)/mknote FORCE
80 $(call if_changed,mknote)
81
82 65
83$(obj)/coffcrt0.o: EXTRA_AFLAGS := -DXCOFF 66targets += crt0.o
84targets += coffcrt0.o crt0.o 67$(obj)/crt0.o: $(common)/crt0.S FORCE
85$(obj)/coffcrt0.o $(obj)/crt0.o: $(common)/crt0.S FORCE
86 $(call if_changed_dep,as_o_S) 68 $(call if_changed_dep,as_o_S)
87 69
88quiet_cmd_gencoffb = COFF $@
89 cmd_gencoffb = $(LD) -o $@ $(COFF_LD_ARGS) $(COFFOBJS) $< $(LIBS) && \
90 $(OBJCOPY) $@ $@ -R .comment $(del-ramdisk-sec)
91targets += coffboot
92$(obj)/coffboot: $(obj)/image.o $(COFFOBJS) $(LIBS) $(srctree)/$(boot)/ld.script FORCE
93 $(call if_changed,gencoffb)
94targets += coffboot.initrd
95$(obj)/coffboot.initrd: $(obj)/image.initrd.o $(COFFOBJS) $(LIBS) \
96 $(srctree)/$(boot)/ld.script FORCE
97 $(call if_changed,gencoffb)
98
99
100quiet_cmd_gen-coff = COFF $@
101 cmd_gen-coff = $(OBJCOPY) $(OBJCOPY_ARGS) $< $@ && \
102 $(HACKCOFF) $@ && \
103 ln -sf $(notdir $@) $(images)/zImage$(initrd).pmac
104
105$(images)/vmlinux.coff: $(obj)/coffboot
106 $(call cmd,gen-coff)
107
108$(images)/vmlinux.initrd.coff: $(obj)/coffboot.initrd
109 $(call cmd,gen-coff)
110
111quiet_cmd_gen-elf-pmac = ELF $@
112 cmd_gen-elf-pmac = $(LD) $(NEWWORLD_LD_ARGS) -o $@ \
113 $(NEWWORLDOBJS) $(LIBS) $< && \
114 $(OBJCOPY) $@ $@ --add-section=.note=$(obj)/note \
115 -R .comment $(del-ramdisk-sec)
116
117$(images)/vmlinux.elf-pmac: $(obj)/image.o $(NEWWORLDOBJS) $(LIBS) \
118 $(obj)/note $(srctree)/$(boot)/ld.script
119 $(call cmd,gen-elf-pmac)
120$(images)/vmlinux.initrd.elf-pmac: $(obj)/image.initrd.o $(NEWWORLDOBJS) \
121 $(LIBS) $(obj)/note \
122 $(srctree)/$(boot)/ld.script
123 $(call cmd,gen-elf-pmac)
124
125quiet_cmd_gen-chrp = CHRP $@ 70quiet_cmd_gen-chrp = CHRP $@
126 cmd_gen-chrp = $(LD) $(CHRP_LD_ARGS) -o $@ $(CHRPOBJS) $< $(LIBS) && \ 71 cmd_gen-chrp = $(LD) $(CHRP_LD_ARGS) -o $@ $(CHRPOBJS) $< $(LIBS) && \
127 $(OBJCOPY) $@ $@ -R .comment $(del-ramdisk-sec) 72 $(OBJCOPY) $@ $@ -R .comment $(del-ramdisk-sec)
@@ -139,46 +84,23 @@ $(images)/zImage.chrp-rs6k $(images)/zImage.initrd.chrp-rs6k: \
139 %-rs6k: % 84 %-rs6k: %
140 $(call cmd,addnote) 85 $(call cmd,addnote)
141 86
142quiet_cmd_gen-miboot = GEN $@
143 cmd_gen-miboot = $(OBJCOPY) $(OBJCOPY_ARGS) \
144 --add-section=$1=$(word 2, $^) $< $@
145$(images)/miboot.image: $(obj)/dummy.o $(images)/vmlinux.gz
146 $(call cmd,gen-miboot,image)
147
148$(images)/miboot.initrd.image: $(images)/miboot.image $(images)/ramdisk.image.gz
149 $(call cmd,gen-miboot,initrd)
150
151# The targets used on the make command-line 87# The targets used on the make command-line
152 88
153.PHONY: zImage zImage.initrd 89.PHONY: zImage zImage.initrd
154zImage: $(images)/vmlinux.coff \ 90zImage: $(images)/zImage.chrp \
155 $(images)/vmlinux.elf-pmac \ 91 $(images)/zImage.chrp-rs6k
156 $(images)/zImage.chrp \
157 $(images)/zImage.chrp-rs6k \
158 $(images)/miboot.image
159 @echo ' kernel: $@ is ready ($<)' 92 @echo ' kernel: $@ is ready ($<)'
160zImage.initrd: $(images)/vmlinux.initrd.coff \ 93zImage.initrd: $(images)/zImage.initrd.chrp \
161 $(images)/vmlinux.initrd.elf-pmac \ 94 $(images)/zImage.initrd.chrp-rs6k
162 $(images)/zImage.initrd.chrp \
163 $(images)/zImage.initrd.chrp-rs6k \
164 $(images)/miboot.initrd.image
165 @echo ' kernel: $@ is ready ($<)' 95 @echo ' kernel: $@ is ready ($<)'
166 96
167TFTPIMAGE := /tftpboot/zImage 97TFTPIMAGE := /tftpboot/zImage
168 98
169.PHONY: znetboot znetboot.initrd 99.PHONY: znetboot znetboot.initrd
170znetboot: $(images)/vmlinux.coff \ 100znetboot: $(images)/zImage.chrp
171 $(images)/vmlinux.elf-pmac \
172 $(images)/zImage.chrp
173 cp $(images)/vmlinux.coff $(TFTPIMAGE).pmac$(END)
174 cp $(images)/vmlinux.elf-pmac $(TFTPIMAGE).pmac$(END).elf
175 cp $(images)/zImage.chrp $(TFTPIMAGE).chrp$(END) 101 cp $(images)/zImage.chrp $(TFTPIMAGE).chrp$(END)
176 @echo ' kernel: $@ is ready ($<)' 102 @echo ' kernel: $@ is ready ($<)'
177znetboot.initrd:$(images)/vmlinux.initrd.coff \ 103znetboot.initrd:$(images)/zImage.initrd.chrp
178 $(images)/vmlinux.initrd.elf-pmac \
179 $(images)/zImage.initrd.chrp
180 cp $(images)/vmlinux.initrd.coff $(TFTPIMAGE).pmac$(END)
181 cp $(images)/vmlinux.initrd.elf-pmac $(TFTPIMAGE).pmac$(END).elf
182 cp $(images)/zImage.initrd.chrp $(TFTPIMAGE).chrp$(END) 104 cp $(images)/zImage.initrd.chrp $(TFTPIMAGE).chrp$(END)
183 @echo ' kernel: $@ is ready ($<)' 105 @echo ' kernel: $@ is ready ($<)'
184 106
diff --git a/arch/ppc/boot/openfirmware/coffmain.c b/arch/ppc/boot/openfirmware/coffmain.c
deleted file mode 100644
index 2da8855e2b..0000000000
--- a/arch/ppc/boot/openfirmware/coffmain.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Copyright (C) Paul Mackerras 1997.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/string.h>
10#include <asm/processor.h>
11#include <asm/page.h>
12
13#include "nonstdio.h"
14#include "of1275.h"
15
16/* Passed from the linker */
17extern char __image_begin, __image_end;
18extern char __ramdisk_begin[], __ramdisk_end;
19extern char _start, _end;
20
21extern char image_data[], initrd_data[];
22extern int initrd_len, image_len;
23extern unsigned int heap_max;
24extern void flush_cache(void *start, unsigned int len);
25extern void gunzip(void *, int, unsigned char *, int *);
26extern void make_bi_recs(unsigned long addr, char *name, unsigned int mach,
27 unsigned int progend);
28extern void setup_bats(unsigned long start);
29
30char *avail_ram;
31char *begin_avail, *end_avail;
32char *avail_high;
33
34#define SCRATCH_SIZE (128 << 10)
35
36static char heap[SCRATCH_SIZE];
37
38static unsigned long ram_start = 0;
39static unsigned long ram_end = 0x1000000;
40
41static unsigned long prog_start = 0x800000;
42static unsigned long prog_size = 0x700000;
43
44typedef void (*kernel_start_t)(int, int, void *);
45
46void boot(int a1, int a2, void *prom)
47{
48 unsigned sa, len;
49 void *dst;
50 unsigned char *im;
51 unsigned initrd_start, initrd_size;
52
53 printf("coffboot starting: loaded at 0x%p\n", &_start);
54 setup_bats(ram_start);
55
56 initrd_size = (char *)(&__ramdisk_end) - (char *)(&__ramdisk_begin);
57 if (initrd_size) {
58 initrd_start = (ram_end - initrd_size) & ~0xFFF;
59 a1 = initrd_start;
60 a2 = initrd_size;
61 claim(initrd_start, ram_end - initrd_start, 0);
62 printf("initial ramdisk moving 0x%x <- 0x%p (%x bytes)\n\r",
63 initrd_start, (char *)(&__ramdisk_begin), initrd_size);
64 memcpy((char *)initrd_start, (char *)(&__ramdisk_begin), initrd_size);
65 prog_size = initrd_start - prog_start;
66 } else
67 a2 = 0xdeadbeef;
68
69 im = (char *)(&__image_begin);
70 len = (char *)(&__image_end) - (char *)(&__image_begin);
71 /* claim 4MB starting at PROG_START */
72 claim(prog_start, prog_size, 0);
73 map(prog_start, prog_start, prog_size);
74 dst = (void *) prog_start;
75 if (im[0] == 0x1f && im[1] == 0x8b) {
76 /* set up scratch space */
77 begin_avail = avail_high = avail_ram = heap;
78 end_avail = heap + sizeof(heap);
79 printf("heap at 0x%p\n", avail_ram);
80 printf("gunzipping (0x%p <- 0x%p:0x%p)...", dst, im, im+len);
81 gunzip(dst, prog_size, im, &len);
82 printf("done %u bytes\n", len);
83 printf("%u bytes of heap consumed, max in use %u\n",
84 avail_high - begin_avail, heap_max);
85 } else {
86 memmove(dst, im, len);
87 }
88
89 flush_cache(dst, len);
90 make_bi_recs(((unsigned long) dst + len), "coffboot", _MACH_Pmac,
91 (prog_start + prog_size));
92
93 sa = (unsigned long)prog_start;
94 printf("start address = 0x%x\n", sa);
95
96 (*(kernel_start_t)sa)(a1, a2, prom);
97
98 printf("returned?\n");
99
100 pause();
101}
diff --git a/arch/ppc/boot/openfirmware/newworldmain.c b/arch/ppc/boot/openfirmware/newworldmain.c
deleted file mode 100644
index fa8a8f9313..0000000000
--- a/arch/ppc/boot/openfirmware/newworldmain.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright (C) Paul Mackerras 1997.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/string.h>
10#include "nonstdio.h"
11#include "of1275.h"
12#include <asm/processor.h>
13#include <asm/page.h>
14
15/* Passed from the linker */
16extern char __image_begin, __image_end;
17extern char __ramdisk_begin[], __ramdisk_end;
18extern char _start, _end;
19
20extern unsigned int heap_max;
21extern void flush_cache(void *start, unsigned int len);
22extern void gunzip(void *, int, unsigned char *, int *);
23extern void make_bi_recs(unsigned long addr, char *name, unsigned int mach,
24 unsigned int progend);
25
26char *avail_ram;
27char *begin_avail, *end_avail;
28char *avail_high;
29
30
31#define RAM_END (16 << 20)
32
33#define PROG_START 0x00010000
34#define PROG_SIZE 0x007f0000
35
36#define SCRATCH_SIZE (128 << 10)
37
38typedef void (*kernel_start_t)(int, int, void *);
39
40void boot(int a1, int a2, void *prom)
41{
42 unsigned sa, len;
43 void *dst;
44 unsigned char *im;
45 unsigned initrd_start, initrd_size;
46
47 printf("chrpboot starting: loaded at 0x%p\n", &_start);
48
49 initrd_size = (char *)(&__ramdisk_end) - (char *)(&__ramdisk_begin);
50 if (initrd_size) {
51 initrd_start = (RAM_END - initrd_size) & ~0xFFF;
52 a1 = initrd_start;
53 a2 = initrd_size;
54 claim(initrd_start, RAM_END - initrd_start, 0);
55 printf("initial ramdisk moving 0x%x <- 0x%p (%x bytes)\n\r",
56 initrd_start, (char *)(&__ramdisk_begin), initrd_size);
57 memcpy((char *)initrd_start, (char *)(&__ramdisk_begin), initrd_size);
58 } else
59 a2 = 0xdeadbeef;
60
61 im = (char *)(&__image_begin);
62 len = (char *)(&__image_end) - (char *)(&__image_begin);
63 /* claim 3MB starting at PROG_START */
64 claim(PROG_START, PROG_SIZE, 0);
65 dst = (void *) PROG_START;
66 if (im[0] == 0x1f && im[1] == 0x8b) {
67 /* claim some memory for scratch space */
68 avail_ram = (char *) claim(0, SCRATCH_SIZE, 0x10);
69 begin_avail = avail_high = avail_ram;
70 end_avail = avail_ram + SCRATCH_SIZE;
71 printf("heap at 0x%p\n", avail_ram);
72 printf("gunzipping (0x%p <- 0x%p:0x%p)...", dst, im, im+len);
73 gunzip(dst, PROG_SIZE, im, &len);
74 printf("done %u bytes\n", len);
75 printf("%u bytes of heap consumed, max in use %u\n",
76 avail_high - begin_avail, heap_max);
77 release(begin_avail, SCRATCH_SIZE);
78 } else {
79 memmove(dst, im, len);
80 }
81
82 flush_cache(dst, len);
83 make_bi_recs(((unsigned long) dst + len), "chrpboot", _MACH_Pmac,
84 (PROG_START + PROG_SIZE));
85
86 sa = (unsigned long)PROG_START;
87 printf("start address = 0x%x\n", sa);
88
89 (*(kernel_start_t)sa)(a1, a2, prom);
90
91 printf("returned?\n");
92
93 pause();
94}
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
index 82df88b01b..9533f8de23 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -190,6 +190,8 @@ boot-$(CONFIG_REDWOOD_5) += embed_config.o
190boot-$(CONFIG_REDWOOD_6) += embed_config.o 190boot-$(CONFIG_REDWOOD_6) += embed_config.o
191boot-$(CONFIG_8xx) += embed_config.o 191boot-$(CONFIG_8xx) += embed_config.o
192boot-$(CONFIG_8260) += embed_config.o 192boot-$(CONFIG_8260) += embed_config.o
193boot-$(CONFIG_EP405) += embed_config.o
194boot-$(CONFIG_XILINX_ML300) += embed_config.o
193boot-$(CONFIG_BSEIP) += iic.o 195boot-$(CONFIG_BSEIP) += iic.o
194boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o 196boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o
195boot-$(CONFIG_MV64X60) += misc-mv64x60.o 197boot-$(CONFIG_MV64X60) += misc-mv64x60.o
@@ -262,11 +264,11 @@ $(images)/zImage.initrd-STRIPELF: $(obj)/zvmlinux.initrd
262 skip=64 bs=1k 264 skip=64 bs=1k
263 265
264$(images)/zImage-TREE: $(obj)/zvmlinux $(MKTREE) 266$(images)/zImage-TREE: $(obj)/zvmlinux $(MKTREE)
265 $(MKTREE) $(obj)/zvmlinux $(images)/zImage.$(end-y) $(ENTRYPOINT) 267 $(MKTREE) $(obj)/zvmlinux $(images)/zImage.$(end-y) $(entrypoint-y)
266 268
267$(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE) 269$(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE)
268 $(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \ 270 $(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \
269 $(ENTRYPOINT) 271 $(entrypoint-y)
270 272
271$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT) 273$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT)
272 $(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y) 274 $(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y)
diff --git a/arch/ppc/configs/TQM8540_defconfig b/arch/ppc/configs/TQM8540_defconfig
new file mode 100644
index 0000000000..99bf3b7a27
--- /dev/null
+++ b/arch/ppc/configs/TQM8540_defconfig
@@ -0,0 +1,973 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15-rc2
4# Fri Nov 25 17:26:50 2005
5#
6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y
8CONFIG_RWSEM_XCHGADD_ALGORITHM=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_PPC=y
11CONFIG_PPC32=y
12CONFIG_GENERIC_NVRAM=y
13CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
15
16#
17# Code maturity level options
18#
19CONFIG_EXPERIMENTAL=y
20CONFIG_CLEAN_COMPILE=y
21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
23
24#
25# General setup
26#
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SWAP=y
30CONFIG_SYSVIPC=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33CONFIG_SYSCTL=y
34# CONFIG_AUDIT is not set
35# CONFIG_HOTPLUG is not set
36CONFIG_KOBJECT_UEVENT=y
37# CONFIG_IKCONFIG is not set
38CONFIG_INITRAMFS_SOURCE=""
39CONFIG_EMBEDDED=y
40# CONFIG_KALLSYMS is not set
41CONFIG_PRINTK=y
42CONFIG_BUG=y
43CONFIG_BASE_FULL=y
44CONFIG_FUTEX=y
45# CONFIG_EPOLL is not set
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SHMEM=y
48CONFIG_CC_ALIGN_FUNCTIONS=0
49CONFIG_CC_ALIGN_LABELS=0
50CONFIG_CC_ALIGN_LOOPS=0
51CONFIG_CC_ALIGN_JUMPS=0
52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
54
55#
56# Loadable module support
57#
58# CONFIG_MODULES is not set
59
60#
61# Block layer
62#
63# CONFIG_LBD is not set
64
65#
66# IO Schedulers
67#
68CONFIG_IOSCHED_NOOP=y
69CONFIG_IOSCHED_AS=y
70CONFIG_IOSCHED_DEADLINE=y
71CONFIG_IOSCHED_CFQ=y
72CONFIG_DEFAULT_AS=y
73# CONFIG_DEFAULT_DEADLINE is not set
74# CONFIG_DEFAULT_CFQ is not set
75# CONFIG_DEFAULT_NOOP is not set
76CONFIG_DEFAULT_IOSCHED="anticipatory"
77
78#
79# Processor
80#
81# CONFIG_6xx is not set
82# CONFIG_40x is not set
83# CONFIG_44x is not set
84# CONFIG_POWER3 is not set
85# CONFIG_POWER4 is not set
86# CONFIG_8xx is not set
87# CONFIG_E200 is not set
88CONFIG_E500=y
89CONFIG_BOOKE=y
90CONFIG_FSL_BOOKE=y
91# CONFIG_PHYS_64BIT is not set
92CONFIG_SPE=y
93CONFIG_MATH_EMULATION=y
94# CONFIG_KEXEC is not set
95# CONFIG_CPU_FREQ is not set
96# CONFIG_WANT_EARLY_SERIAL is not set
97CONFIG_PPC_GEN550=y
98CONFIG_85xx=y
99CONFIG_PPC_INDIRECT_PCI_BE=y
100
101#
102# Freescale 85xx options
103#
104# CONFIG_MPC8540_ADS is not set
105# CONFIG_MPC8548_CDS is not set
106# CONFIG_MPC8555_CDS is not set
107# CONFIG_MPC8560_ADS is not set
108# CONFIG_SBC8560 is not set
109# CONFIG_STX_GP3 is not set
110CONFIG_TQM8540=y
111# CONFIG_TQM8541 is not set
112# CONFIG_TQM8555 is not set
113# CONFIG_TQM8560 is not set
114CONFIG_MPC8540=y
115
116#
117# Platform options
118#
119# CONFIG_HIGHMEM is not set
120# CONFIG_HZ_100 is not set
121CONFIG_HZ_250=y
122# CONFIG_HZ_1000 is not set
123CONFIG_HZ=250
124CONFIG_PREEMPT_NONE=y
125# CONFIG_PREEMPT_VOLUNTARY is not set
126# CONFIG_PREEMPT is not set
127CONFIG_SELECT_MEMORY_MODEL=y
128CONFIG_FLATMEM_MANUAL=y
129# CONFIG_DISCONTIGMEM_MANUAL is not set
130# CONFIG_SPARSEMEM_MANUAL is not set
131CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4
135CONFIG_BINFMT_ELF=y
136# CONFIG_BINFMT_MISC is not set
137# CONFIG_CMDLINE_BOOL is not set
138# CONFIG_PM is not set
139# CONFIG_SOFTWARE_SUSPEND is not set
140CONFIG_SECCOMP=y
141CONFIG_ISA_DMA_API=y
142
143#
144# Bus options
145#
146CONFIG_PPC_I8259=y
147CONFIG_PPC_INDIRECT_PCI=y
148CONFIG_PCI=y
149CONFIG_PCI_DOMAINS=y
150# CONFIG_PCI_LEGACY_PROC is not set
151
152#
153# PCCARD (PCMCIA/CardBus) support
154#
155# CONFIG_PCCARD is not set
156# CONFIG_RAPIDIO is not set
157
158#
159# Advanced setup
160#
161# CONFIG_ADVANCED_OPTIONS is not set
162
163#
164# Default settings for advanced configuration options are used
165#
166CONFIG_HIGHMEM_START=0xfe000000
167CONFIG_LOWMEM_SIZE=0x30000000
168CONFIG_KERNEL_START=0xc0000000
169CONFIG_TASK_SIZE=0x80000000
170CONFIG_BOOT_LOAD=0x00800000
171
172#
173# Networking
174#
175CONFIG_NET=y
176
177#
178# Networking options
179#
180CONFIG_PACKET=y
181# CONFIG_PACKET_MMAP is not set
182CONFIG_UNIX=y
183# CONFIG_NET_KEY is not set
184CONFIG_INET=y
185CONFIG_IP_MULTICAST=y
186# CONFIG_IP_ADVANCED_ROUTER is not set
187CONFIG_IP_FIB_HASH=y
188CONFIG_IP_PNP=y
189CONFIG_IP_PNP_DHCP=y
190CONFIG_IP_PNP_BOOTP=y
191# CONFIG_IP_PNP_RARP is not set
192# CONFIG_NET_IPIP is not set
193# CONFIG_NET_IPGRE is not set
194# CONFIG_IP_MROUTE is not set
195# CONFIG_ARPD is not set
196CONFIG_SYN_COOKIES=y
197# CONFIG_INET_AH is not set
198# CONFIG_INET_ESP is not set
199# CONFIG_INET_IPCOMP is not set
200# CONFIG_INET_TUNNEL is not set
201CONFIG_INET_DIAG=y
202CONFIG_INET_TCP_DIAG=y
203# CONFIG_TCP_CONG_ADVANCED is not set
204CONFIG_TCP_CONG_BIC=y
205# CONFIG_IPV6 is not set
206# CONFIG_NETFILTER is not set
207
208#
209# DCCP Configuration (EXPERIMENTAL)
210#
211# CONFIG_IP_DCCP is not set
212
213#
214# SCTP Configuration (EXPERIMENTAL)
215#
216# CONFIG_IP_SCTP is not set
217# CONFIG_ATM is not set
218# CONFIG_BRIDGE is not set
219# CONFIG_VLAN_8021Q is not set
220# CONFIG_DECNET is not set
221# CONFIG_LLC2 is not set
222# CONFIG_IPX is not set
223# CONFIG_ATALK is not set
224# CONFIG_X25 is not set
225# CONFIG_LAPB is not set
226# CONFIG_NET_DIVERT is not set
227# CONFIG_ECONET is not set
228# CONFIG_WAN_ROUTER is not set
229
230#
231# QoS and/or fair queueing
232#
233# CONFIG_NET_SCHED is not set
234
235#
236# Network testing
237#
238# CONFIG_NET_PKTGEN is not set
239# CONFIG_HAMRADIO is not set
240# CONFIG_IRDA is not set
241# CONFIG_BT is not set
242# CONFIG_IEEE80211 is not set
243
244#
245# Device Drivers
246#
247
248#
249# Generic Driver Options
250#
251CONFIG_STANDALONE=y
252CONFIG_PREVENT_FIRMWARE_BUILD=y
253# CONFIG_FW_LOADER is not set
254
255#
256# Connector - unified userspace <-> kernelspace linker
257#
258# CONFIG_CONNECTOR is not set
259
260#
261# Memory Technology Devices (MTD)
262#
263CONFIG_MTD=y
264# CONFIG_MTD_DEBUG is not set
265CONFIG_MTD_CONCAT=y
266CONFIG_MTD_PARTITIONS=y
267# CONFIG_MTD_REDBOOT_PARTS is not set
268CONFIG_MTD_CMDLINE_PARTS=y
269
270#
271# User Modules And Translation Layers
272#
273CONFIG_MTD_CHAR=y
274CONFIG_MTD_BLOCK=y
275# CONFIG_FTL is not set
276# CONFIG_NFTL is not set
277# CONFIG_INFTL is not set
278# CONFIG_RFD_FTL is not set
279
280#
281# RAM/ROM/Flash chip drivers
282#
283CONFIG_MTD_CFI=y
284# CONFIG_MTD_JEDECPROBE is not set
285CONFIG_MTD_GEN_PROBE=y
286# CONFIG_MTD_CFI_ADV_OPTIONS is not set
287CONFIG_MTD_MAP_BANK_WIDTH_1=y
288CONFIG_MTD_MAP_BANK_WIDTH_2=y
289CONFIG_MTD_MAP_BANK_WIDTH_4=y
290# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
291# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
292# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
293CONFIG_MTD_CFI_I1=y
294CONFIG_MTD_CFI_I2=y
295# CONFIG_MTD_CFI_I4 is not set
296# CONFIG_MTD_CFI_I8 is not set
297# CONFIG_MTD_CFI_INTELEXT is not set
298CONFIG_MTD_CFI_AMDSTD=y
299CONFIG_MTD_CFI_AMDSTD_RETRY=0
300# CONFIG_MTD_CFI_STAA is not set
301CONFIG_MTD_CFI_UTIL=y
302# CONFIG_MTD_RAM is not set
303# CONFIG_MTD_ROM is not set
304# CONFIG_MTD_ABSENT is not set
305
306#
307# Mapping drivers for chip access
308#
309# CONFIG_MTD_COMPLEX_MAPPINGS is not set
310# CONFIG_MTD_PHYSMAP is not set
311CONFIG_MTD_TQM85xx=y
312# CONFIG_MTD_PLATRAM is not set
313
314#
315# Self-contained MTD device drivers
316#
317# CONFIG_MTD_PMC551 is not set
318# CONFIG_MTD_SLRAM is not set
319# CONFIG_MTD_PHRAM is not set
320# CONFIG_MTD_MTDRAM is not set
321# CONFIG_MTD_BLKMTD is not set
322# CONFIG_MTD_BLOCK2MTD is not set
323
324#
325# Disk-On-Chip Device Drivers
326#
327# CONFIG_MTD_DOC2000 is not set
328# CONFIG_MTD_DOC2001 is not set
329# CONFIG_MTD_DOC2001PLUS is not set
330
331#
332# NAND Flash Device Drivers
333#
334# CONFIG_MTD_NAND is not set
335
336#
337# OneNAND Flash Device Drivers
338#
339# CONFIG_MTD_ONENAND is not set
340
341#
342# Parallel port support
343#
344# CONFIG_PARPORT is not set
345
346#
347# Plug and Play support
348#
349
350#
351# Block devices
352#
353# CONFIG_BLK_DEV_FD is not set
354# CONFIG_BLK_CPQ_DA is not set
355# CONFIG_BLK_CPQ_CISS_DA is not set
356# CONFIG_BLK_DEV_DAC960 is not set
357# CONFIG_BLK_DEV_UMEM is not set
358# CONFIG_BLK_DEV_COW_COMMON is not set
359CONFIG_BLK_DEV_LOOP=y
360# CONFIG_BLK_DEV_CRYPTOLOOP is not set
361# CONFIG_BLK_DEV_NBD is not set
362# CONFIG_BLK_DEV_SX8 is not set
363CONFIG_BLK_DEV_RAM=y
364CONFIG_BLK_DEV_RAM_COUNT=16
365CONFIG_BLK_DEV_RAM_SIZE=32768
366CONFIG_BLK_DEV_INITRD=y
367# CONFIG_CDROM_PKTCDVD is not set
368# CONFIG_ATA_OVER_ETH is not set
369
370#
371# ATA/ATAPI/MFM/RLL support
372#
373CONFIG_IDE=y
374CONFIG_BLK_DEV_IDE=y
375
376#
377# Please see Documentation/ide.txt for help/info on IDE drives
378#
379# CONFIG_BLK_DEV_IDE_SATA is not set
380CONFIG_BLK_DEV_IDEDISK=y
381# CONFIG_IDEDISK_MULTI_MODE is not set
382# CONFIG_BLK_DEV_IDECD is not set
383# CONFIG_BLK_DEV_IDETAPE is not set
384# CONFIG_BLK_DEV_IDEFLOPPY is not set
385# CONFIG_IDE_TASK_IOCTL is not set
386
387#
388# IDE chipset support/bugfixes
389#
390CONFIG_IDE_GENERIC=y
391CONFIG_BLK_DEV_IDEPCI=y
392CONFIG_IDEPCI_SHARE_IRQ=y
393# CONFIG_BLK_DEV_OFFBOARD is not set
394CONFIG_BLK_DEV_GENERIC=y
395# CONFIG_BLK_DEV_OPTI621 is not set
396# CONFIG_BLK_DEV_SL82C105 is not set
397CONFIG_BLK_DEV_IDEDMA_PCI=y
398# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
399CONFIG_IDEDMA_PCI_AUTO=y
400# CONFIG_IDEDMA_ONLYDISK is not set
401# CONFIG_BLK_DEV_AEC62XX is not set
402# CONFIG_BLK_DEV_ALI15X3 is not set
403# CONFIG_BLK_DEV_AMD74XX is not set
404# CONFIG_BLK_DEV_CMD64X is not set
405# CONFIG_BLK_DEV_TRIFLEX is not set
406# CONFIG_BLK_DEV_CY82C693 is not set
407# CONFIG_BLK_DEV_CS5520 is not set
408# CONFIG_BLK_DEV_CS5530 is not set
409# CONFIG_BLK_DEV_HPT34X is not set
410# CONFIG_BLK_DEV_HPT366 is not set
411# CONFIG_BLK_DEV_SC1200 is not set
412# CONFIG_BLK_DEV_PIIX is not set
413# CONFIG_BLK_DEV_IT821X is not set
414# CONFIG_BLK_DEV_NS87415 is not set
415# CONFIG_BLK_DEV_PDC202XX_OLD is not set
416# CONFIG_BLK_DEV_PDC202XX_NEW is not set
417# CONFIG_BLK_DEV_SVWKS is not set
418# CONFIG_BLK_DEV_SIIMAGE is not set
419# CONFIG_BLK_DEV_SLC90E66 is not set
420# CONFIG_BLK_DEV_TRM290 is not set
421CONFIG_BLK_DEV_VIA82CXXX=y
422# CONFIG_IDE_ARM is not set
423CONFIG_BLK_DEV_IDEDMA=y
424# CONFIG_IDEDMA_IVB is not set
425CONFIG_IDEDMA_AUTO=y
426# CONFIG_BLK_DEV_HD is not set
427
428#
429# SCSI device support
430#
431# CONFIG_RAID_ATTRS is not set
432# CONFIG_SCSI is not set
433
434#
435# Multi-device support (RAID and LVM)
436#
437# CONFIG_MD is not set
438
439#
440# Fusion MPT device support
441#
442# CONFIG_FUSION is not set
443
444#
445# IEEE 1394 (FireWire) support
446#
447# CONFIG_IEEE1394 is not set
448
449#
450# I2O device support
451#
452# CONFIG_I2O is not set
453
454#
455# Macintosh device drivers
456#
457# CONFIG_WINDFARM is not set
458
459#
460# Network device support
461#
462CONFIG_NETDEVICES=y
463# CONFIG_DUMMY is not set
464# CONFIG_BONDING is not set
465# CONFIG_EQUALIZER is not set
466# CONFIG_TUN is not set
467
468#
469# ARCnet devices
470#
471# CONFIG_ARCNET is not set
472
473#
474# PHY device support
475#
476CONFIG_PHYLIB=y
477
478#
479# MII PHY device drivers
480#
481# CONFIG_MARVELL_PHY is not set
482# CONFIG_DAVICOM_PHY is not set
483# CONFIG_QSEMI_PHY is not set
484# CONFIG_LXT_PHY is not set
485# CONFIG_CICADA_PHY is not set
486
487#
488# Ethernet (10 or 100Mbit)
489#
490CONFIG_NET_ETHERNET=y
491CONFIG_MII=y
492# CONFIG_HAPPYMEAL is not set
493# CONFIG_SUNGEM is not set
494# CONFIG_CASSINI is not set
495# CONFIG_NET_VENDOR_3COM is not set
496
497#
498# Tulip family network device support
499#
500# CONFIG_NET_TULIP is not set
501# CONFIG_HP100 is not set
502CONFIG_NET_PCI=y
503# CONFIG_PCNET32 is not set
504# CONFIG_AMD8111_ETH is not set
505# CONFIG_ADAPTEC_STARFIRE is not set
506# CONFIG_B44 is not set
507# CONFIG_FORCEDETH is not set
508# CONFIG_DGRS is not set
509# CONFIG_EEPRO100 is not set
510CONFIG_E100=y
511# CONFIG_FEALNX is not set
512# CONFIG_NATSEMI is not set
513# CONFIG_NE2K_PCI is not set
514# CONFIG_8139CP is not set
515# CONFIG_8139TOO is not set
516# CONFIG_SIS900 is not set
517# CONFIG_EPIC100 is not set
518# CONFIG_SUNDANCE is not set
519# CONFIG_TLAN is not set
520# CONFIG_VIA_RHINE is not set
521
522#
523# Ethernet (1000 Mbit)
524#
525# CONFIG_ACENIC is not set
526# CONFIG_DL2K is not set
527# CONFIG_E1000 is not set
528# CONFIG_NS83820 is not set
529# CONFIG_HAMACHI is not set
530# CONFIG_YELLOWFIN is not set
531# CONFIG_R8169 is not set
532# CONFIG_SIS190 is not set
533# CONFIG_SKGE is not set
534# CONFIG_SK98LIN is not set
535# CONFIG_VIA_VELOCITY is not set
536# CONFIG_TIGON3 is not set
537# CONFIG_BNX2 is not set
538CONFIG_GIANFAR=y
539CONFIG_GFAR_NAPI=y
540
541#
542# Ethernet (10000 Mbit)
543#
544# CONFIG_CHELSIO_T1 is not set
545# CONFIG_IXGB is not set
546# CONFIG_S2IO is not set
547
548#
549# Token Ring devices
550#
551# CONFIG_TR is not set
552
553#
554# Wireless LAN (non-hamradio)
555#
556# CONFIG_NET_RADIO is not set
557
558#
559# Wan interfaces
560#
561# CONFIG_WAN is not set
562# CONFIG_FDDI is not set
563# CONFIG_HIPPI is not set
564# CONFIG_PPP is not set
565# CONFIG_SLIP is not set
566# CONFIG_SHAPER is not set
567# CONFIG_NETCONSOLE is not set
568# CONFIG_NETPOLL is not set
569# CONFIG_NET_POLL_CONTROLLER is not set
570
571#
572# ISDN subsystem
573#
574# CONFIG_ISDN is not set
575
576#
577# Telephony Support
578#
579# CONFIG_PHONE is not set
580
581#
582# Input device support
583#
584CONFIG_INPUT=y
585
586#
587# Userland interfaces
588#
589# CONFIG_INPUT_MOUSEDEV is not set
590# CONFIG_INPUT_JOYDEV is not set
591# CONFIG_INPUT_TSDEV is not set
592# CONFIG_INPUT_EVDEV is not set
593# CONFIG_INPUT_EVBUG is not set
594
595#
596# Input Device Drivers
597#
598# CONFIG_INPUT_KEYBOARD is not set
599# CONFIG_INPUT_MOUSE is not set
600# CONFIG_INPUT_JOYSTICK is not set
601# CONFIG_INPUT_TOUCHSCREEN is not set
602# CONFIG_INPUT_MISC is not set
603
604#
605# Hardware I/O ports
606#
607# CONFIG_SERIO is not set
608# CONFIG_GAMEPORT is not set
609
610#
611# Character devices
612#
613# CONFIG_VT is not set
614# CONFIG_SERIAL_NONSTANDARD is not set
615
616#
617# Serial drivers
618#
619CONFIG_SERIAL_8250=y
620CONFIG_SERIAL_8250_CONSOLE=y
621CONFIG_SERIAL_8250_NR_UARTS=4
622# CONFIG_SERIAL_8250_EXTENDED is not set
623
624#
625# Non-8250 serial port support
626#
627CONFIG_SERIAL_CORE=y
628CONFIG_SERIAL_CORE_CONSOLE=y
629# CONFIG_SERIAL_JSM is not set
630CONFIG_UNIX98_PTYS=y
631CONFIG_LEGACY_PTYS=y
632CONFIG_LEGACY_PTY_COUNT=256
633
634#
635# IPMI
636#
637# CONFIG_IPMI_HANDLER is not set
638
639#
640# Watchdog Cards
641#
642# CONFIG_WATCHDOG is not set
643# CONFIG_NVRAM is not set
644CONFIG_GEN_RTC=y
645# CONFIG_GEN_RTC_X is not set
646# CONFIG_DTLK is not set
647# CONFIG_R3964 is not set
648# CONFIG_APPLICOM is not set
649
650#
651# Ftape, the floppy tape device driver
652#
653# CONFIG_AGP is not set
654# CONFIG_DRM is not set
655# CONFIG_RAW_DRIVER is not set
656
657#
658# TPM devices
659#
660# CONFIG_TCG_TPM is not set
661# CONFIG_TELCLOCK is not set
662
663#
664# I2C support
665#
666CONFIG_I2C=y
667CONFIG_I2C_CHARDEV=y
668
669#
670# I2C Algorithms
671#
672# CONFIG_I2C_ALGOBIT is not set
673# CONFIG_I2C_ALGOPCF is not set
674# CONFIG_I2C_ALGOPCA is not set
675
676#
677# I2C Hardware Bus support
678#
679# CONFIG_I2C_ALI1535 is not set
680# CONFIG_I2C_ALI1563 is not set
681# CONFIG_I2C_ALI15X3 is not set
682# CONFIG_I2C_AMD756 is not set
683# CONFIG_I2C_AMD8111 is not set
684# CONFIG_I2C_I801 is not set
685# CONFIG_I2C_I810 is not set
686# CONFIG_I2C_PIIX4 is not set
687CONFIG_I2C_MPC=y
688# CONFIG_I2C_NFORCE2 is not set
689# CONFIG_I2C_PARPORT_LIGHT is not set
690# CONFIG_I2C_PROSAVAGE is not set
691# CONFIG_I2C_SAVAGE4 is not set
692# CONFIG_SCx200_ACB is not set
693# CONFIG_I2C_SIS5595 is not set
694# CONFIG_I2C_SIS630 is not set
695# CONFIG_I2C_SIS96X is not set
696# CONFIG_I2C_VIA is not set
697# CONFIG_I2C_VIAPRO is not set
698# CONFIG_I2C_VOODOO3 is not set
699# CONFIG_I2C_PCA_ISA is not set
700
701#
702# Miscellaneous I2C Chip support
703#
704CONFIG_SENSORS_DS1337=y
705# CONFIG_SENSORS_DS1374 is not set
706# CONFIG_SENSORS_EEPROM is not set
707# CONFIG_SENSORS_PCF8574 is not set
708# CONFIG_SENSORS_PCA9539 is not set
709# CONFIG_SENSORS_PCF8591 is not set
710# CONFIG_SENSORS_RTC8564 is not set
711# CONFIG_SENSORS_M41T00 is not set
712# CONFIG_SENSORS_MAX6875 is not set
713# CONFIG_RTC_X1205_I2C is not set
714# CONFIG_I2C_DEBUG_CORE is not set
715# CONFIG_I2C_DEBUG_ALGO is not set
716# CONFIG_I2C_DEBUG_BUS is not set
717# CONFIG_I2C_DEBUG_CHIP is not set
718
719#
720# Dallas's 1-wire bus
721#
722# CONFIG_W1 is not set
723
724#
725# Hardware Monitoring support
726#
727CONFIG_HWMON=y
728# CONFIG_HWMON_VID is not set
729# CONFIG_SENSORS_ADM1021 is not set
730# CONFIG_SENSORS_ADM1025 is not set
731# CONFIG_SENSORS_ADM1026 is not set
732# CONFIG_SENSORS_ADM1031 is not set
733# CONFIG_SENSORS_ADM9240 is not set
734# CONFIG_SENSORS_ASB100 is not set
735# CONFIG_SENSORS_ATXP1 is not set
736# CONFIG_SENSORS_DS1621 is not set
737# CONFIG_SENSORS_FSCHER is not set
738# CONFIG_SENSORS_FSCPOS is not set
739# CONFIG_SENSORS_GL518SM is not set
740# CONFIG_SENSORS_GL520SM is not set
741# CONFIG_SENSORS_IT87 is not set
742# CONFIG_SENSORS_LM63 is not set
743CONFIG_SENSORS_LM75=y
744# CONFIG_SENSORS_LM77 is not set
745# CONFIG_SENSORS_LM78 is not set
746# CONFIG_SENSORS_LM80 is not set
747# CONFIG_SENSORS_LM83 is not set
748# CONFIG_SENSORS_LM85 is not set
749# CONFIG_SENSORS_LM87 is not set
750# CONFIG_SENSORS_LM90 is not set
751# CONFIG_SENSORS_LM92 is not set
752# CONFIG_SENSORS_MAX1619 is not set
753# CONFIG_SENSORS_PC87360 is not set
754# CONFIG_SENSORS_SIS5595 is not set
755# CONFIG_SENSORS_SMSC47M1 is not set
756# CONFIG_SENSORS_SMSC47B397 is not set
757# CONFIG_SENSORS_VIA686A is not set
758# CONFIG_SENSORS_W83781D is not set
759# CONFIG_SENSORS_W83792D is not set
760# CONFIG_SENSORS_W83L785TS is not set
761# CONFIG_SENSORS_W83627HF is not set
762# CONFIG_SENSORS_W83627EHF is not set
763CONFIG_HWMON_DEBUG_CHIP=y
764
765#
766# Misc devices
767#
768
769#
770# Multimedia Capabilities Port drivers
771#
772
773#
774# Multimedia devices
775#
776# CONFIG_VIDEO_DEV is not set
777
778#
779# Digital Video Broadcasting Devices
780#
781# CONFIG_DVB is not set
782
783#
784# Graphics support
785#
786# CONFIG_FB is not set
787
788#
789# Sound
790#
791# CONFIG_SOUND is not set
792
793#
794# USB support
795#
796CONFIG_USB_ARCH_HAS_HCD=y
797CONFIG_USB_ARCH_HAS_OHCI=y
798# CONFIG_USB is not set
799
800#
801# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
802#
803
804#
805# USB Gadget Support
806#
807# CONFIG_USB_GADGET is not set
808
809#
810# MMC/SD Card support
811#
812# CONFIG_MMC is not set
813
814#
815# InfiniBand support
816#
817# CONFIG_INFINIBAND is not set
818
819#
820# SN Devices
821#
822
823#
824# File systems
825#
826CONFIG_EXT2_FS=y
827# CONFIG_EXT2_FS_XATTR is not set
828# CONFIG_EXT2_FS_XIP is not set
829CONFIG_EXT3_FS=y
830CONFIG_EXT3_FS_XATTR=y
831# CONFIG_EXT3_FS_POSIX_ACL is not set
832# CONFIG_EXT3_FS_SECURITY is not set
833CONFIG_JBD=y
834# CONFIG_JBD_DEBUG is not set
835CONFIG_FS_MBCACHE=y
836# CONFIG_REISERFS_FS is not set
837# CONFIG_JFS_FS is not set
838# CONFIG_FS_POSIX_ACL is not set
839# CONFIG_XFS_FS is not set
840# CONFIG_MINIX_FS is not set
841# CONFIG_ROMFS_FS is not set
842CONFIG_INOTIFY=y
843# CONFIG_QUOTA is not set
844CONFIG_DNOTIFY=y
845# CONFIG_AUTOFS_FS is not set
846# CONFIG_AUTOFS4_FS is not set
847# CONFIG_FUSE_FS is not set
848
849#
850# CD-ROM/DVD Filesystems
851#
852# CONFIG_ISO9660_FS is not set
853# CONFIG_UDF_FS is not set
854
855#
856# DOS/FAT/NT Filesystems
857#
858# CONFIG_MSDOS_FS is not set
859# CONFIG_VFAT_FS is not set
860# CONFIG_NTFS_FS is not set
861
862#
863# Pseudo filesystems
864#
865CONFIG_PROC_FS=y
866CONFIG_PROC_KCORE=y
867CONFIG_SYSFS=y
868CONFIG_TMPFS=y
869# CONFIG_HUGETLB_PAGE is not set
870CONFIG_RAMFS=y
871# CONFIG_RELAYFS_FS is not set
872
873#
874# Miscellaneous filesystems
875#
876# CONFIG_ADFS_FS is not set
877# CONFIG_AFFS_FS is not set
878# CONFIG_HFS_FS is not set
879# CONFIG_HFSPLUS_FS is not set
880# CONFIG_BEFS_FS is not set
881# CONFIG_BFS_FS is not set
882# CONFIG_EFS_FS is not set
883# CONFIG_JFFS_FS is not set
884CONFIG_JFFS2_FS=y
885CONFIG_JFFS2_FS_DEBUG=0
886CONFIG_JFFS2_FS_WRITEBUFFER=y
887# CONFIG_JFFS2_SUMMARY is not set
888# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
889CONFIG_JFFS2_ZLIB=y
890CONFIG_JFFS2_RTIME=y
891# CONFIG_JFFS2_RUBIN is not set
892CONFIG_CRAMFS=y
893# CONFIG_VXFS_FS is not set
894# CONFIG_HPFS_FS is not set
895# CONFIG_QNX4FS_FS is not set
896# CONFIG_SYSV_FS is not set
897# CONFIG_UFS_FS is not set
898
899#
900# Network File Systems
901#
902CONFIG_NFS_FS=y
903# CONFIG_NFS_V3 is not set
904# CONFIG_NFS_V4 is not set
905# CONFIG_NFS_DIRECTIO is not set
906# CONFIG_NFSD is not set
907CONFIG_ROOT_NFS=y
908CONFIG_LOCKD=y
909CONFIG_NFS_COMMON=y
910CONFIG_SUNRPC=y
911# CONFIG_RPCSEC_GSS_KRB5 is not set
912# CONFIG_RPCSEC_GSS_SPKM3 is not set
913# CONFIG_SMB_FS is not set
914# CONFIG_CIFS is not set
915# CONFIG_NCP_FS is not set
916# CONFIG_CODA_FS is not set
917# CONFIG_AFS_FS is not set
918# CONFIG_9P_FS is not set
919
920#
921# Partition Types
922#
923CONFIG_PARTITION_ADVANCED=y
924# CONFIG_ACORN_PARTITION is not set
925# CONFIG_OSF_PARTITION is not set
926# CONFIG_AMIGA_PARTITION is not set
927# CONFIG_ATARI_PARTITION is not set
928# CONFIG_MAC_PARTITION is not set
929# CONFIG_MSDOS_PARTITION is not set
930# CONFIG_LDM_PARTITION is not set
931# CONFIG_SGI_PARTITION is not set
932# CONFIG_ULTRIX_PARTITION is not set
933# CONFIG_SUN_PARTITION is not set
934# CONFIG_EFI_PARTITION is not set
935
936#
937# Native Language Support
938#
939# CONFIG_NLS is not set
940
941#
942# Library routines
943#
944# CONFIG_CRC_CCITT is not set
945# CONFIG_CRC16 is not set
946CONFIG_CRC32=y
947# CONFIG_LIBCRC32C is not set
948CONFIG_ZLIB_INFLATE=y
949CONFIG_ZLIB_DEFLATE=y
950# CONFIG_PROFILING is not set
951
952#
953# Kernel hacking
954#
955# CONFIG_PRINTK_TIME is not set
956# CONFIG_DEBUG_KERNEL is not set
957CONFIG_LOG_BUF_SHIFT=14
958# CONFIG_SERIAL_TEXT_DEBUG is not set
959
960#
961# Security options
962#
963# CONFIG_KEYS is not set
964# CONFIG_SECURITY is not set
965
966#
967# Cryptographic options
968#
969# CONFIG_CRYPTO is not set
970
971#
972# Hardware crypto devices
973#
diff --git a/arch/ppc/configs/TQM8541_defconfig b/arch/ppc/configs/TQM8541_defconfig
new file mode 100644
index 0000000000..0ff56695d3
--- /dev/null
+++ b/arch/ppc/configs/TQM8541_defconfig
@@ -0,0 +1,986 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15-rc2
4# Wed Nov 30 13:36:28 2005
5#
6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y
8CONFIG_RWSEM_XCHGADD_ALGORITHM=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_PPC=y
11CONFIG_PPC32=y
12CONFIG_GENERIC_NVRAM=y
13CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
15
16#
17# Code maturity level options
18#
19CONFIG_EXPERIMENTAL=y
20CONFIG_CLEAN_COMPILE=y
21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
23
24#
25# General setup
26#
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SWAP=y
30CONFIG_SYSVIPC=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33CONFIG_SYSCTL=y
34# CONFIG_AUDIT is not set
35# CONFIG_HOTPLUG is not set
36CONFIG_KOBJECT_UEVENT=y
37# CONFIG_IKCONFIG is not set
38CONFIG_INITRAMFS_SOURCE=""
39CONFIG_EMBEDDED=y
40# CONFIG_KALLSYMS is not set
41CONFIG_PRINTK=y
42CONFIG_BUG=y
43CONFIG_BASE_FULL=y
44CONFIG_FUTEX=y
45# CONFIG_EPOLL is not set
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SHMEM=y
48CONFIG_CC_ALIGN_FUNCTIONS=0
49CONFIG_CC_ALIGN_LABELS=0
50CONFIG_CC_ALIGN_LOOPS=0
51CONFIG_CC_ALIGN_JUMPS=0
52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
54
55#
56# Loadable module support
57#
58# CONFIG_MODULES is not set
59
60#
61# Block layer
62#
63# CONFIG_LBD is not set
64
65#
66# IO Schedulers
67#
68CONFIG_IOSCHED_NOOP=y
69CONFIG_IOSCHED_AS=y
70CONFIG_IOSCHED_DEADLINE=y
71CONFIG_IOSCHED_CFQ=y
72CONFIG_DEFAULT_AS=y
73# CONFIG_DEFAULT_DEADLINE is not set
74# CONFIG_DEFAULT_CFQ is not set
75# CONFIG_DEFAULT_NOOP is not set
76CONFIG_DEFAULT_IOSCHED="anticipatory"
77
78#
79# Processor
80#
81# CONFIG_6xx is not set
82# CONFIG_40x is not set
83# CONFIG_44x is not set
84# CONFIG_POWER3 is not set
85# CONFIG_POWER4 is not set
86# CONFIG_8xx is not set
87# CONFIG_E200 is not set
88CONFIG_E500=y
89CONFIG_BOOKE=y
90CONFIG_FSL_BOOKE=y
91# CONFIG_PHYS_64BIT is not set
92CONFIG_SPE=y
93CONFIG_MATH_EMULATION=y
94# CONFIG_KEXEC is not set
95# CONFIG_CPU_FREQ is not set
96# CONFIG_WANT_EARLY_SERIAL is not set
97CONFIG_PPC_GEN550=y
98CONFIG_85xx=y
99CONFIG_PPC_INDIRECT_PCI_BE=y
100
101#
102# Freescale 85xx options
103#
104# CONFIG_MPC8540_ADS is not set
105# CONFIG_MPC8548_CDS is not set
106# CONFIG_MPC8555_CDS is not set
107# CONFIG_MPC8560_ADS is not set
108# CONFIG_SBC8560 is not set
109# CONFIG_STX_GP3 is not set
110# CONFIG_TQM8540 is not set
111CONFIG_TQM8541=y
112# CONFIG_TQM8555 is not set
113# CONFIG_TQM8560 is not set
114CONFIG_MPC8555=y
115
116#
117# Platform options
118#
119CONFIG_CPM2=y
120# CONFIG_PC_KEYBOARD is not set
121# CONFIG_HIGHMEM is not set
122# CONFIG_HZ_100 is not set
123CONFIG_HZ_250=y
124# CONFIG_HZ_1000 is not set
125CONFIG_HZ=250
126CONFIG_PREEMPT_NONE=y
127# CONFIG_PREEMPT_VOLUNTARY is not set
128# CONFIG_PREEMPT is not set
129CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set
132# CONFIG_SPARSEMEM_MANUAL is not set
133CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4
137CONFIG_BINFMT_ELF=y
138# CONFIG_BINFMT_MISC is not set
139# CONFIG_CMDLINE_BOOL is not set
140# CONFIG_PM is not set
141# CONFIG_SOFTWARE_SUSPEND is not set
142CONFIG_SECCOMP=y
143CONFIG_ISA_DMA_API=y
144
145#
146# Bus options
147#
148CONFIG_PPC_I8259=y
149CONFIG_PPC_INDIRECT_PCI=y
150CONFIG_PCI=y
151CONFIG_PCI_DOMAINS=y
152# CONFIG_PCI_LEGACY_PROC is not set
153
154#
155# PCCARD (PCMCIA/CardBus) support
156#
157# CONFIG_PCCARD is not set
158
159#
160# Advanced setup
161#
162# CONFIG_ADVANCED_OPTIONS is not set
163
164#
165# Default settings for advanced configuration options are used
166#
167CONFIG_HIGHMEM_START=0xfe000000
168CONFIG_LOWMEM_SIZE=0x30000000
169CONFIG_KERNEL_START=0xc0000000
170CONFIG_TASK_SIZE=0x80000000
171CONFIG_BOOT_LOAD=0x00800000
172
173#
174# Networking
175#
176CONFIG_NET=y
177
178#
179# Networking options
180#
181CONFIG_PACKET=y
182# CONFIG_PACKET_MMAP is not set
183CONFIG_UNIX=y
184# CONFIG_NET_KEY is not set
185CONFIG_INET=y
186CONFIG_IP_MULTICAST=y
187# CONFIG_IP_ADVANCED_ROUTER is not set
188CONFIG_IP_FIB_HASH=y
189CONFIG_IP_PNP=y
190CONFIG_IP_PNP_DHCP=y
191CONFIG_IP_PNP_BOOTP=y
192# CONFIG_IP_PNP_RARP is not set
193# CONFIG_NET_IPIP is not set
194# CONFIG_NET_IPGRE is not set
195# CONFIG_IP_MROUTE is not set
196# CONFIG_ARPD is not set
197CONFIG_SYN_COOKIES=y
198# CONFIG_INET_AH is not set
199# CONFIG_INET_ESP is not set
200# CONFIG_INET_IPCOMP is not set
201# CONFIG_INET_TUNNEL is not set
202CONFIG_INET_DIAG=y
203CONFIG_INET_TCP_DIAG=y
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_BIC=y
206# CONFIG_IPV6 is not set
207# CONFIG_NETFILTER is not set
208
209#
210# DCCP Configuration (EXPERIMENTAL)
211#
212# CONFIG_IP_DCCP is not set
213
214#
215# SCTP Configuration (EXPERIMENTAL)
216#
217# CONFIG_IP_SCTP is not set
218# CONFIG_ATM is not set
219# CONFIG_BRIDGE is not set
220# CONFIG_VLAN_8021Q is not set
221# CONFIG_DECNET is not set
222# CONFIG_LLC2 is not set
223# CONFIG_IPX is not set
224# CONFIG_ATALK is not set
225# CONFIG_X25 is not set
226# CONFIG_LAPB is not set
227# CONFIG_NET_DIVERT is not set
228# CONFIG_ECONET is not set
229# CONFIG_WAN_ROUTER is not set
230
231#
232# QoS and/or fair queueing
233#
234# CONFIG_NET_SCHED is not set
235
236#
237# Network testing
238#
239# CONFIG_NET_PKTGEN is not set
240# CONFIG_HAMRADIO is not set
241# CONFIG_IRDA is not set
242# CONFIG_BT is not set
243# CONFIG_IEEE80211 is not set
244
245#
246# Device Drivers
247#
248
249#
250# Generic Driver Options
251#
252CONFIG_STANDALONE=y
253CONFIG_PREVENT_FIRMWARE_BUILD=y
254# CONFIG_FW_LOADER is not set
255
256#
257# Connector - unified userspace <-> kernelspace linker
258#
259# CONFIG_CONNECTOR is not set
260
261#
262# Memory Technology Devices (MTD)
263#
264CONFIG_MTD=y
265# CONFIG_MTD_DEBUG is not set
266CONFIG_MTD_CONCAT=y
267CONFIG_MTD_PARTITIONS=y
268# CONFIG_MTD_REDBOOT_PARTS is not set
269CONFIG_MTD_CMDLINE_PARTS=y
270
271#
272# User Modules And Translation Layers
273#
274CONFIG_MTD_CHAR=y
275CONFIG_MTD_BLOCK=y
276# CONFIG_FTL is not set
277# CONFIG_NFTL is not set
278# CONFIG_INFTL is not set
279# CONFIG_RFD_FTL is not set
280
281#
282# RAM/ROM/Flash chip drivers
283#
284CONFIG_MTD_CFI=y
285# CONFIG_MTD_JEDECPROBE is not set
286CONFIG_MTD_GEN_PROBE=y
287# CONFIG_MTD_CFI_ADV_OPTIONS is not set
288CONFIG_MTD_MAP_BANK_WIDTH_1=y
289CONFIG_MTD_MAP_BANK_WIDTH_2=y
290CONFIG_MTD_MAP_BANK_WIDTH_4=y
291# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
292# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
293# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
294CONFIG_MTD_CFI_I1=y
295CONFIG_MTD_CFI_I2=y
296# CONFIG_MTD_CFI_I4 is not set
297# CONFIG_MTD_CFI_I8 is not set
298# CONFIG_MTD_CFI_INTELEXT is not set
299CONFIG_MTD_CFI_AMDSTD=y
300CONFIG_MTD_CFI_AMDSTD_RETRY=0
301# CONFIG_MTD_CFI_STAA is not set
302CONFIG_MTD_CFI_UTIL=y
303# CONFIG_MTD_RAM is not set
304# CONFIG_MTD_ROM is not set
305# CONFIG_MTD_ABSENT is not set
306
307#
308# Mapping drivers for chip access
309#
310# CONFIG_MTD_COMPLEX_MAPPINGS is not set
311# CONFIG_MTD_PHYSMAP is not set
312CONFIG_MTD_TQM85xx=y
313# CONFIG_MTD_PLATRAM is not set
314
315#
316# Self-contained MTD device drivers
317#
318# CONFIG_MTD_PMC551 is not set
319# CONFIG_MTD_SLRAM is not set
320# CONFIG_MTD_PHRAM is not set
321# CONFIG_MTD_MTDRAM is not set
322# CONFIG_MTD_BLKMTD is not set
323# CONFIG_MTD_BLOCK2MTD is not set
324
325#
326# Disk-On-Chip Device Drivers
327#
328# CONFIG_MTD_DOC2000 is not set
329# CONFIG_MTD_DOC2001 is not set
330# CONFIG_MTD_DOC2001PLUS is not set
331
332#
333# NAND Flash Device Drivers
334#
335# CONFIG_MTD_NAND is not set
336
337#
338# OneNAND Flash Device Drivers
339#
340# CONFIG_MTD_ONENAND is not set
341
342#
343# Parallel port support
344#
345# CONFIG_PARPORT is not set
346
347#
348# Plug and Play support
349#
350
351#
352# Block devices
353#
354# CONFIG_BLK_DEV_FD is not set
355# CONFIG_BLK_CPQ_DA is not set
356# CONFIG_BLK_CPQ_CISS_DA is not set
357# CONFIG_BLK_DEV_DAC960 is not set
358# CONFIG_BLK_DEV_UMEM is not set
359# CONFIG_BLK_DEV_COW_COMMON is not set
360CONFIG_BLK_DEV_LOOP=y
361# CONFIG_BLK_DEV_CRYPTOLOOP is not set
362# CONFIG_BLK_DEV_NBD is not set
363# CONFIG_BLK_DEV_SX8 is not set
364CONFIG_BLK_DEV_RAM=y
365CONFIG_BLK_DEV_RAM_COUNT=16
366CONFIG_BLK_DEV_RAM_SIZE=32768
367CONFIG_BLK_DEV_INITRD=y
368# CONFIG_CDROM_PKTCDVD is not set
369# CONFIG_ATA_OVER_ETH is not set
370
371#
372# ATA/ATAPI/MFM/RLL support
373#
374CONFIG_IDE=y
375CONFIG_BLK_DEV_IDE=y
376
377#
378# Please see Documentation/ide.txt for help/info on IDE drives
379#
380# CONFIG_BLK_DEV_IDE_SATA is not set
381CONFIG_BLK_DEV_IDEDISK=y
382# CONFIG_IDEDISK_MULTI_MODE is not set
383# CONFIG_BLK_DEV_IDECD is not set
384# CONFIG_BLK_DEV_IDETAPE is not set
385# CONFIG_BLK_DEV_IDEFLOPPY is not set
386# CONFIG_IDE_TASK_IOCTL is not set
387
388#
389# IDE chipset support/bugfixes
390#
391CONFIG_IDE_GENERIC=y
392CONFIG_BLK_DEV_IDEPCI=y
393CONFIG_IDEPCI_SHARE_IRQ=y
394# CONFIG_BLK_DEV_OFFBOARD is not set
395CONFIG_BLK_DEV_GENERIC=y
396# CONFIG_BLK_DEV_OPTI621 is not set
397# CONFIG_BLK_DEV_SL82C105 is not set
398CONFIG_BLK_DEV_IDEDMA_PCI=y
399# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
400CONFIG_IDEDMA_PCI_AUTO=y
401# CONFIG_IDEDMA_ONLYDISK is not set
402# CONFIG_BLK_DEV_AEC62XX is not set
403# CONFIG_BLK_DEV_ALI15X3 is not set
404# CONFIG_BLK_DEV_AMD74XX is not set
405# CONFIG_BLK_DEV_CMD64X is not set
406# CONFIG_BLK_DEV_TRIFLEX is not set
407# CONFIG_BLK_DEV_CY82C693 is not set
408# CONFIG_BLK_DEV_CS5520 is not set
409# CONFIG_BLK_DEV_CS5530 is not set
410# CONFIG_BLK_DEV_HPT34X is not set
411# CONFIG_BLK_DEV_HPT366 is not set
412# CONFIG_BLK_DEV_SC1200 is not set
413# CONFIG_BLK_DEV_PIIX is not set
414# CONFIG_BLK_DEV_IT821X is not set
415# CONFIG_BLK_DEV_NS87415 is not set
416# CONFIG_BLK_DEV_PDC202XX_OLD is not set
417# CONFIG_BLK_DEV_PDC202XX_NEW is not set
418# CONFIG_BLK_DEV_SVWKS is not set
419# CONFIG_BLK_DEV_SIIMAGE is not set
420# CONFIG_BLK_DEV_SLC90E66 is not set
421# CONFIG_BLK_DEV_TRM290 is not set
422CONFIG_BLK_DEV_VIA82CXXX=y
423# CONFIG_IDE_ARM is not set
424CONFIG_BLK_DEV_IDEDMA=y
425# CONFIG_IDEDMA_IVB is not set
426CONFIG_IDEDMA_AUTO=y
427# CONFIG_BLK_DEV_HD is not set
428
429#
430# SCSI device support
431#
432# CONFIG_RAID_ATTRS is not set
433# CONFIG_SCSI is not set
434
435#
436# Multi-device support (RAID and LVM)
437#
438# CONFIG_MD is not set
439
440#
441# Fusion MPT device support
442#
443# CONFIG_FUSION is not set
444
445#
446# IEEE 1394 (FireWire) support
447#
448# CONFIG_IEEE1394 is not set
449
450#
451# I2O device support
452#
453# CONFIG_I2O is not set
454
455#
456# Macintosh device drivers
457#
458# CONFIG_WINDFARM is not set
459
460#
461# Network device support
462#
463CONFIG_NETDEVICES=y
464# CONFIG_DUMMY is not set
465# CONFIG_BONDING is not set
466# CONFIG_EQUALIZER is not set
467# CONFIG_TUN is not set
468
469#
470# ARCnet devices
471#
472# CONFIG_ARCNET is not set
473
474#
475# PHY device support
476#
477CONFIG_PHYLIB=y
478
479#
480# MII PHY device drivers
481#
482# CONFIG_MARVELL_PHY is not set
483# CONFIG_DAVICOM_PHY is not set
484# CONFIG_QSEMI_PHY is not set
485# CONFIG_LXT_PHY is not set
486# CONFIG_CICADA_PHY is not set
487
488#
489# Ethernet (10 or 100Mbit)
490#
491CONFIG_NET_ETHERNET=y
492CONFIG_MII=y
493# CONFIG_HAPPYMEAL is not set
494# CONFIG_SUNGEM is not set
495# CONFIG_CASSINI is not set
496# CONFIG_NET_VENDOR_3COM is not set
497
498#
499# Tulip family network device support
500#
501# CONFIG_NET_TULIP is not set
502# CONFIG_HP100 is not set
503CONFIG_NET_PCI=y
504# CONFIG_PCNET32 is not set
505# CONFIG_AMD8111_ETH is not set
506# CONFIG_ADAPTEC_STARFIRE is not set
507# CONFIG_B44 is not set
508# CONFIG_FORCEDETH is not set
509# CONFIG_DGRS is not set
510# CONFIG_EEPRO100 is not set
511CONFIG_E100=y
512# CONFIG_FEALNX is not set
513# CONFIG_NATSEMI is not set
514# CONFIG_NE2K_PCI is not set
515# CONFIG_8139CP is not set
516# CONFIG_8139TOO is not set
517# CONFIG_SIS900 is not set
518# CONFIG_EPIC100 is not set
519# CONFIG_SUNDANCE is not set
520# CONFIG_TLAN is not set
521# CONFIG_VIA_RHINE is not set
522# CONFIG_FS_ENET is not set
523
524#
525# Ethernet (1000 Mbit)
526#
527# CONFIG_ACENIC is not set
528# CONFIG_DL2K is not set
529# CONFIG_E1000 is not set
530# CONFIG_NS83820 is not set
531# CONFIG_HAMACHI is not set
532# CONFIG_YELLOWFIN is not set
533# CONFIG_R8169 is not set
534# CONFIG_SIS190 is not set
535# CONFIG_SKGE is not set
536# CONFIG_SK98LIN is not set
537# CONFIG_VIA_VELOCITY is not set
538# CONFIG_TIGON3 is not set
539# CONFIG_BNX2 is not set
540CONFIG_GIANFAR=y
541CONFIG_GFAR_NAPI=y
542
543#
544# Ethernet (10000 Mbit)
545#
546# CONFIG_CHELSIO_T1 is not set
547# CONFIG_IXGB is not set
548# CONFIG_S2IO is not set
549
550#
551# Token Ring devices
552#
553# CONFIG_TR is not set
554
555#
556# Wireless LAN (non-hamradio)
557#
558# CONFIG_NET_RADIO is not set
559
560#
561# Wan interfaces
562#
563# CONFIG_WAN is not set
564# CONFIG_FDDI is not set
565# CONFIG_HIPPI is not set
566# CONFIG_PPP is not set
567# CONFIG_SLIP is not set
568# CONFIG_SHAPER is not set
569# CONFIG_NETCONSOLE is not set
570# CONFIG_NETPOLL is not set
571# CONFIG_NET_POLL_CONTROLLER is not set
572
573#
574# ISDN subsystem
575#
576# CONFIG_ISDN is not set
577
578#
579# Telephony Support
580#
581# CONFIG_PHONE is not set
582
583#
584# Input device support
585#
586CONFIG_INPUT=y
587
588#
589# Userland interfaces
590#
591# CONFIG_INPUT_MOUSEDEV is not set
592# CONFIG_INPUT_JOYDEV is not set
593# CONFIG_INPUT_TSDEV is not set
594# CONFIG_INPUT_EVDEV is not set
595# CONFIG_INPUT_EVBUG is not set
596
597#
598# Input Device Drivers
599#
600# CONFIG_INPUT_KEYBOARD is not set
601# CONFIG_INPUT_MOUSE is not set
602# CONFIG_INPUT_JOYSTICK is not set
603# CONFIG_INPUT_TOUCHSCREEN is not set
604# CONFIG_INPUT_MISC is not set
605
606#
607# Hardware I/O ports
608#
609# CONFIG_SERIO is not set
610# CONFIG_GAMEPORT is not set
611
612#
613# Character devices
614#
615# CONFIG_VT is not set
616# CONFIG_SERIAL_NONSTANDARD is not set
617
618#
619# Serial drivers
620#
621CONFIG_SERIAL_8250=y
622CONFIG_SERIAL_8250_CONSOLE=y
623CONFIG_SERIAL_8250_NR_UARTS=4
624# CONFIG_SERIAL_8250_EXTENDED is not set
625
626#
627# Non-8250 serial port support
628#
629CONFIG_SERIAL_CORE=y
630CONFIG_SERIAL_CORE_CONSOLE=y
631# CONFIG_SERIAL_CPM is not set
632# CONFIG_SERIAL_JSM is not set
633CONFIG_UNIX98_PTYS=y
634CONFIG_LEGACY_PTYS=y
635CONFIG_LEGACY_PTY_COUNT=256
636
637#
638# IPMI
639#
640# CONFIG_IPMI_HANDLER is not set
641
642#
643# Watchdog Cards
644#
645# CONFIG_WATCHDOG is not set
646# CONFIG_NVRAM is not set
647CONFIG_GEN_RTC=y
648# CONFIG_GEN_RTC_X is not set
649# CONFIG_DTLK is not set
650# CONFIG_R3964 is not set
651# CONFIG_APPLICOM is not set
652
653#
654# Ftape, the floppy tape device driver
655#
656# CONFIG_AGP is not set
657# CONFIG_DRM is not set
658# CONFIG_RAW_DRIVER is not set
659
660#
661# TPM devices
662#
663# CONFIG_TCG_TPM is not set
664# CONFIG_TELCLOCK is not set
665
666#
667# I2C support
668#
669CONFIG_I2C=y
670CONFIG_I2C_CHARDEV=y
671
672#
673# I2C Algorithms
674#
675# CONFIG_I2C_ALGOBIT is not set
676# CONFIG_I2C_ALGOPCF is not set
677# CONFIG_I2C_ALGOPCA is not set
678
679#
680# I2C Hardware Bus support
681#
682# CONFIG_I2C_ALI1535 is not set
683# CONFIG_I2C_ALI1563 is not set
684# CONFIG_I2C_ALI15X3 is not set
685# CONFIG_I2C_AMD756 is not set
686# CONFIG_I2C_AMD8111 is not set
687# CONFIG_I2C_I801 is not set
688# CONFIG_I2C_I810 is not set
689# CONFIG_I2C_PIIX4 is not set
690CONFIG_I2C_MPC=y
691# CONFIG_I2C_MPC8260 is not set
692# CONFIG_I2C_NFORCE2 is not set
693# CONFIG_I2C_PARPORT_LIGHT is not set
694# CONFIG_I2C_PROSAVAGE is not set
695# CONFIG_I2C_SAVAGE4 is not set
696# CONFIG_SCx200_ACB is not set
697# CONFIG_I2C_SIS5595 is not set
698# CONFIG_I2C_SIS630 is not set
699# CONFIG_I2C_SIS96X is not set
700# CONFIG_I2C_VIA is not set
701# CONFIG_I2C_VIAPRO is not set
702# CONFIG_I2C_VOODOO3 is not set
703# CONFIG_I2C_PCA_ISA is not set
704
705#
706# Miscellaneous I2C Chip support
707#
708CONFIG_SENSORS_DS1337=y
709# CONFIG_SENSORS_DS1374 is not set
710# CONFIG_SENSORS_EEPROM is not set
711# CONFIG_SENSORS_MAX6900 is not set
712# CONFIG_SENSORS_PCF8574 is not set
713# CONFIG_SENSORS_PCF8563 is not set
714# CONFIG_SENSORS_PCA9539 is not set
715# CONFIG_SENSORS_PCF8591 is not set
716# CONFIG_SENSORS_RTC8564 is not set
717# CONFIG_SENSORS_M41T00 is not set
718# CONFIG_SENSORS_MAX6875 is not set
719# CONFIG_RTC_X1205_I2C is not set
720# CONFIG_I2C_DEBUG_CORE is not set
721# CONFIG_I2C_DEBUG_ALGO is not set
722# CONFIG_I2C_DEBUG_BUS is not set
723# CONFIG_I2C_DEBUG_CHIP is not set
724
725#
726# Dallas's 1-wire bus
727#
728# CONFIG_W1 is not set
729
730#
731# Hardware Monitoring support
732#
733CONFIG_HWMON=y
734# CONFIG_HWMON_VID is not set
735# CONFIG_SENSORS_ADM1021 is not set
736# CONFIG_SENSORS_ADM1025 is not set
737# CONFIG_SENSORS_ADM1026 is not set
738# CONFIG_SENSORS_ADM1031 is not set
739# CONFIG_SENSORS_ADM9240 is not set
740# CONFIG_SENSORS_ASB100 is not set
741# CONFIG_SENSORS_ATXP1 is not set
742# CONFIG_SENSORS_DS1621 is not set
743# CONFIG_SENSORS_FSCHER is not set
744# CONFIG_SENSORS_FSCPOS is not set
745# CONFIG_SENSORS_GL518SM is not set
746# CONFIG_SENSORS_GL520SM is not set
747# CONFIG_SENSORS_IT87 is not set
748# CONFIG_SENSORS_LM63 is not set
749CONFIG_SENSORS_LM75=y
750# CONFIG_SENSORS_LM77 is not set
751# CONFIG_SENSORS_LM78 is not set
752# CONFIG_SENSORS_LM80 is not set
753# CONFIG_SENSORS_LM83 is not set
754# CONFIG_SENSORS_LM85 is not set
755# CONFIG_SENSORS_LM87 is not set
756# CONFIG_SENSORS_LM90 is not set
757# CONFIG_SENSORS_LM92 is not set
758# CONFIG_SENSORS_MAX1619 is not set
759# CONFIG_SENSORS_PC87360 is not set
760# CONFIG_SENSORS_SIS5595 is not set
761# CONFIG_SENSORS_SMSC47M1 is not set
762# CONFIG_SENSORS_SMSC47B397 is not set
763# CONFIG_SENSORS_VIA686A is not set
764# CONFIG_SENSORS_W83781D is not set
765# CONFIG_SENSORS_W83792D is not set
766# CONFIG_SENSORS_W83L785TS is not set
767# CONFIG_SENSORS_W83627HF is not set
768# CONFIG_SENSORS_W83627EHF is not set
769CONFIG_HWMON_DEBUG_CHIP=y
770
771#
772# Misc devices
773#
774
775#
776# Multimedia Capabilities Port drivers
777#
778
779#
780# Multimedia devices
781#
782# CONFIG_VIDEO_DEV is not set
783
784#
785# Digital Video Broadcasting Devices
786#
787# CONFIG_DVB is not set
788
789#
790# Graphics support
791#
792# CONFIG_FB is not set
793
794#
795# Sound
796#
797# CONFIG_SOUND is not set
798
799#
800# USB support
801#
802CONFIG_USB_ARCH_HAS_HCD=y
803CONFIG_USB_ARCH_HAS_OHCI=y
804# CONFIG_USB is not set
805
806#
807# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
808#
809
810#
811# USB Gadget Support
812#
813# CONFIG_USB_GADGET is not set
814
815#
816# MMC/SD Card support
817#
818# CONFIG_MMC is not set
819
820#
821# InfiniBand support
822#
823# CONFIG_INFINIBAND is not set
824
825#
826# SN Devices
827#
828
829#
830# File systems
831#
832CONFIG_EXT2_FS=y
833# CONFIG_EXT2_FS_XATTR is not set
834# CONFIG_EXT2_FS_XIP is not set
835CONFIG_EXT3_FS=y
836CONFIG_EXT3_FS_XATTR=y
837# CONFIG_EXT3_FS_POSIX_ACL is not set
838# CONFIG_EXT3_FS_SECURITY is not set
839CONFIG_JBD=y
840# CONFIG_JBD_DEBUG is not set
841CONFIG_FS_MBCACHE=y
842# CONFIG_REISERFS_FS is not set
843# CONFIG_JFS_FS is not set
844# CONFIG_FS_POSIX_ACL is not set
845# CONFIG_XFS_FS is not set
846# CONFIG_MINIX_FS is not set
847# CONFIG_ROMFS_FS is not set
848CONFIG_INOTIFY=y
849# CONFIG_QUOTA is not set
850CONFIG_DNOTIFY=y
851# CONFIG_AUTOFS_FS is not set
852# CONFIG_AUTOFS4_FS is not set
853# CONFIG_FUSE_FS is not set
854
855#
856# CD-ROM/DVD Filesystems
857#
858# CONFIG_ISO9660_FS is not set
859# CONFIG_UDF_FS is not set
860
861#
862# DOS/FAT/NT Filesystems
863#
864# CONFIG_MSDOS_FS is not set
865# CONFIG_VFAT_FS is not set
866# CONFIG_NTFS_FS is not set
867
868#
869# Pseudo filesystems
870#
871CONFIG_PROC_FS=y
872CONFIG_PROC_KCORE=y
873CONFIG_SYSFS=y
874CONFIG_TMPFS=y
875# CONFIG_HUGETLB_PAGE is not set
876CONFIG_RAMFS=y
877# CONFIG_RELAYFS_FS is not set
878
879#
880# Miscellaneous filesystems
881#
882# CONFIG_ADFS_FS is not set
883# CONFIG_AFFS_FS is not set
884# CONFIG_HFS_FS is not set
885# CONFIG_HFSPLUS_FS is not set
886# CONFIG_BEFS_FS is not set
887# CONFIG_BFS_FS is not set
888# CONFIG_EFS_FS is not set
889# CONFIG_JFFS_FS is not set
890CONFIG_JFFS2_FS=y
891CONFIG_JFFS2_FS_DEBUG=0
892CONFIG_JFFS2_FS_WRITEBUFFER=y
893# CONFIG_JFFS2_SUMMARY is not set
894# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
895CONFIG_JFFS2_ZLIB=y
896CONFIG_JFFS2_RTIME=y
897# CONFIG_JFFS2_RUBIN is not set
898CONFIG_CRAMFS=y
899# CONFIG_VXFS_FS is not set
900# CONFIG_HPFS_FS is not set
901# CONFIG_QNX4FS_FS is not set
902# CONFIG_SYSV_FS is not set
903# CONFIG_UFS_FS is not set
904
905#
906# Network File Systems
907#
908CONFIG_NFS_FS=y
909# CONFIG_NFS_V3 is not set
910# CONFIG_NFS_V4 is not set
911# CONFIG_NFS_DIRECTIO is not set
912# CONFIG_NFSD is not set
913CONFIG_ROOT_NFS=y
914CONFIG_LOCKD=y
915CONFIG_NFS_COMMON=y
916CONFIG_SUNRPC=y
917# CONFIG_RPCSEC_GSS_KRB5 is not set
918# CONFIG_RPCSEC_GSS_SPKM3 is not set
919# CONFIG_SMB_FS is not set
920# CONFIG_CIFS is not set
921# CONFIG_NCP_FS is not set
922# CONFIG_CODA_FS is not set
923# CONFIG_AFS_FS is not set
924# CONFIG_9P_FS is not set
925
926#
927# Partition Types
928#
929CONFIG_PARTITION_ADVANCED=y
930# CONFIG_ACORN_PARTITION is not set
931# CONFIG_OSF_PARTITION is not set
932# CONFIG_AMIGA_PARTITION is not set
933# CONFIG_ATARI_PARTITION is not set
934# CONFIG_MAC_PARTITION is not set
935# CONFIG_MSDOS_PARTITION is not set
936# CONFIG_LDM_PARTITION is not set
937# CONFIG_SGI_PARTITION is not set
938# CONFIG_ULTRIX_PARTITION is not set
939# CONFIG_SUN_PARTITION is not set
940# CONFIG_EFI_PARTITION is not set
941
942#
943# Native Language Support
944#
945# CONFIG_NLS is not set
946# CONFIG_SCC_ENET is not set
947# CONFIG_FEC_ENET is not set
948
949#
950# CPM2 Options
951#
952
953#
954# Library routines
955#
956# CONFIG_CRC_CCITT is not set
957# CONFIG_CRC16 is not set
958CONFIG_CRC32=y
959# CONFIG_LIBCRC32C is not set
960CONFIG_ZLIB_INFLATE=y
961CONFIG_ZLIB_DEFLATE=y
962# CONFIG_PROFILING is not set
963
964#
965# Kernel hacking
966#
967# CONFIG_PRINTK_TIME is not set
968# CONFIG_DEBUG_KERNEL is not set
969CONFIG_LOG_BUF_SHIFT=14
970# CONFIG_KGDB_CONSOLE is not set
971# CONFIG_SERIAL_TEXT_DEBUG is not set
972
973#
974# Security options
975#
976# CONFIG_KEYS is not set
977# CONFIG_SECURITY is not set
978
979#
980# Cryptographic options
981#
982# CONFIG_CRYPTO is not set
983
984#
985# Hardware crypto devices
986#
diff --git a/arch/ppc/configs/TQM8555_defconfig b/arch/ppc/configs/TQM8555_defconfig
new file mode 100644
index 0000000000..730b3db2e4
--- /dev/null
+++ b/arch/ppc/configs/TQM8555_defconfig
@@ -0,0 +1,983 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15-rc2
4# Thu Nov 24 17:10:52 2005
5#
6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y
8CONFIG_RWSEM_XCHGADD_ALGORITHM=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_PPC=y
11CONFIG_PPC32=y
12CONFIG_GENERIC_NVRAM=y
13CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
15
16#
17# Code maturity level options
18#
19CONFIG_EXPERIMENTAL=y
20CONFIG_CLEAN_COMPILE=y
21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
23
24#
25# General setup
26#
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SWAP=y
30CONFIG_SYSVIPC=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33CONFIG_SYSCTL=y
34# CONFIG_AUDIT is not set
35# CONFIG_HOTPLUG is not set
36CONFIG_KOBJECT_UEVENT=y
37# CONFIG_IKCONFIG is not set
38CONFIG_INITRAMFS_SOURCE=""
39CONFIG_EMBEDDED=y
40# CONFIG_KALLSYMS is not set
41CONFIG_PRINTK=y
42CONFIG_BUG=y
43CONFIG_BASE_FULL=y
44CONFIG_FUTEX=y
45# CONFIG_EPOLL is not set
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SHMEM=y
48CONFIG_CC_ALIGN_FUNCTIONS=0
49CONFIG_CC_ALIGN_LABELS=0
50CONFIG_CC_ALIGN_LOOPS=0
51CONFIG_CC_ALIGN_JUMPS=0
52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
54
55#
56# Loadable module support
57#
58# CONFIG_MODULES is not set
59
60#
61# Block layer
62#
63# CONFIG_LBD is not set
64
65#
66# IO Schedulers
67#
68CONFIG_IOSCHED_NOOP=y
69CONFIG_IOSCHED_AS=y
70CONFIG_IOSCHED_DEADLINE=y
71CONFIG_IOSCHED_CFQ=y
72CONFIG_DEFAULT_AS=y
73# CONFIG_DEFAULT_DEADLINE is not set
74# CONFIG_DEFAULT_CFQ is not set
75# CONFIG_DEFAULT_NOOP is not set
76CONFIG_DEFAULT_IOSCHED="anticipatory"
77
78#
79# Processor
80#
81# CONFIG_6xx is not set
82# CONFIG_40x is not set
83# CONFIG_44x is not set
84# CONFIG_POWER3 is not set
85# CONFIG_POWER4 is not set
86# CONFIG_8xx is not set
87# CONFIG_E200 is not set
88CONFIG_E500=y
89CONFIG_BOOKE=y
90CONFIG_FSL_BOOKE=y
91# CONFIG_PHYS_64BIT is not set
92CONFIG_SPE=y
93CONFIG_MATH_EMULATION=y
94# CONFIG_KEXEC is not set
95# CONFIG_CPU_FREQ is not set
96# CONFIG_WANT_EARLY_SERIAL is not set
97CONFIG_PPC_GEN550=y
98CONFIG_85xx=y
99CONFIG_PPC_INDIRECT_PCI_BE=y
100
101#
102# Freescale 85xx options
103#
104# CONFIG_MPC8540_ADS is not set
105# CONFIG_MPC8548_CDS is not set
106# CONFIG_MPC8555_CDS is not set
107# CONFIG_MPC8560_ADS is not set
108# CONFIG_SBC8560 is not set
109# CONFIG_STX_GP3 is not set
110# CONFIG_TQM8540 is not set
111# CONFIG_TQM8541 is not set
112CONFIG_TQM8555=y
113# CONFIG_TQM8560 is not set
114CONFIG_MPC8555=y
115
116#
117# Platform options
118#
119CONFIG_CPM2=y
120# CONFIG_PC_KEYBOARD is not set
121# CONFIG_HIGHMEM is not set
122# CONFIG_HZ_100 is not set
123CONFIG_HZ_250=y
124# CONFIG_HZ_1000 is not set
125CONFIG_HZ=250
126CONFIG_PREEMPT_NONE=y
127# CONFIG_PREEMPT_VOLUNTARY is not set
128# CONFIG_PREEMPT is not set
129CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set
132# CONFIG_SPARSEMEM_MANUAL is not set
133CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4
137CONFIG_BINFMT_ELF=y
138# CONFIG_BINFMT_MISC is not set
139# CONFIG_CMDLINE_BOOL is not set
140# CONFIG_PM is not set
141# CONFIG_SOFTWARE_SUSPEND is not set
142CONFIG_SECCOMP=y
143CONFIG_ISA_DMA_API=y
144
145#
146# Bus options
147#
148CONFIG_PPC_I8259=y
149CONFIG_PPC_INDIRECT_PCI=y
150CONFIG_PCI=y
151CONFIG_PCI_DOMAINS=y
152# CONFIG_PCI_LEGACY_PROC is not set
153
154#
155# PCCARD (PCMCIA/CardBus) support
156#
157# CONFIG_PCCARD is not set
158
159#
160# Advanced setup
161#
162# CONFIG_ADVANCED_OPTIONS is not set
163
164#
165# Default settings for advanced configuration options are used
166#
167CONFIG_HIGHMEM_START=0xfe000000
168CONFIG_LOWMEM_SIZE=0x30000000
169CONFIG_KERNEL_START=0xc0000000
170CONFIG_TASK_SIZE=0x80000000
171CONFIG_BOOT_LOAD=0x00800000
172
173#
174# Networking
175#
176CONFIG_NET=y
177
178#
179# Networking options
180#
181CONFIG_PACKET=y
182# CONFIG_PACKET_MMAP is not set
183CONFIG_UNIX=y
184# CONFIG_NET_KEY is not set
185CONFIG_INET=y
186CONFIG_IP_MULTICAST=y
187# CONFIG_IP_ADVANCED_ROUTER is not set
188CONFIG_IP_FIB_HASH=y
189CONFIG_IP_PNP=y
190CONFIG_IP_PNP_DHCP=y
191CONFIG_IP_PNP_BOOTP=y
192# CONFIG_IP_PNP_RARP is not set
193# CONFIG_NET_IPIP is not set
194# CONFIG_NET_IPGRE is not set
195# CONFIG_IP_MROUTE is not set
196# CONFIG_ARPD is not set
197CONFIG_SYN_COOKIES=y
198# CONFIG_INET_AH is not set
199# CONFIG_INET_ESP is not set
200# CONFIG_INET_IPCOMP is not set
201# CONFIG_INET_TUNNEL is not set
202CONFIG_INET_DIAG=y
203CONFIG_INET_TCP_DIAG=y
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_BIC=y
206# CONFIG_IPV6 is not set
207# CONFIG_NETFILTER is not set
208
209#
210# DCCP Configuration (EXPERIMENTAL)
211#
212# CONFIG_IP_DCCP is not set
213
214#
215# SCTP Configuration (EXPERIMENTAL)
216#
217# CONFIG_IP_SCTP is not set
218# CONFIG_ATM is not set
219# CONFIG_BRIDGE is not set
220# CONFIG_VLAN_8021Q is not set
221# CONFIG_DECNET is not set
222# CONFIG_LLC2 is not set
223# CONFIG_IPX is not set
224# CONFIG_ATALK is not set
225# CONFIG_X25 is not set
226# CONFIG_LAPB is not set
227# CONFIG_NET_DIVERT is not set
228# CONFIG_ECONET is not set
229# CONFIG_WAN_ROUTER is not set
230
231#
232# QoS and/or fair queueing
233#
234# CONFIG_NET_SCHED is not set
235
236#
237# Network testing
238#
239# CONFIG_NET_PKTGEN is not set
240# CONFIG_HAMRADIO is not set
241# CONFIG_IRDA is not set
242# CONFIG_BT is not set
243# CONFIG_IEEE80211 is not set
244
245#
246# Device Drivers
247#
248
249#
250# Generic Driver Options
251#
252CONFIG_STANDALONE=y
253CONFIG_PREVENT_FIRMWARE_BUILD=y
254# CONFIG_FW_LOADER is not set
255
256#
257# Connector - unified userspace <-> kernelspace linker
258#
259# CONFIG_CONNECTOR is not set
260
261#
262# Memory Technology Devices (MTD)
263#
264CONFIG_MTD=y
265# CONFIG_MTD_DEBUG is not set
266CONFIG_MTD_CONCAT=y
267CONFIG_MTD_PARTITIONS=y
268# CONFIG_MTD_REDBOOT_PARTS is not set
269CONFIG_MTD_CMDLINE_PARTS=y
270
271#
272# User Modules And Translation Layers
273#
274CONFIG_MTD_CHAR=y
275CONFIG_MTD_BLOCK=y
276# CONFIG_FTL is not set
277# CONFIG_NFTL is not set
278# CONFIG_INFTL is not set
279# CONFIG_RFD_FTL is not set
280
281#
282# RAM/ROM/Flash chip drivers
283#
284CONFIG_MTD_CFI=y
285# CONFIG_MTD_JEDECPROBE is not set
286CONFIG_MTD_GEN_PROBE=y
287# CONFIG_MTD_CFI_ADV_OPTIONS is not set
288CONFIG_MTD_MAP_BANK_WIDTH_1=y
289CONFIG_MTD_MAP_BANK_WIDTH_2=y
290CONFIG_MTD_MAP_BANK_WIDTH_4=y
291# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
292# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
293# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
294CONFIG_MTD_CFI_I1=y
295CONFIG_MTD_CFI_I2=y
296# CONFIG_MTD_CFI_I4 is not set
297# CONFIG_MTD_CFI_I8 is not set
298# CONFIG_MTD_CFI_INTELEXT is not set
299CONFIG_MTD_CFI_AMDSTD=y
300CONFIG_MTD_CFI_AMDSTD_RETRY=0
301# CONFIG_MTD_CFI_STAA is not set
302CONFIG_MTD_CFI_UTIL=y
303# CONFIG_MTD_RAM is not set
304# CONFIG_MTD_ROM is not set
305# CONFIG_MTD_ABSENT is not set
306
307#
308# Mapping drivers for chip access
309#
310# CONFIG_MTD_COMPLEX_MAPPINGS is not set
311# CONFIG_MTD_PHYSMAP is not set
312CONFIG_MTD_TQM85xx=y
313# CONFIG_MTD_PLATRAM is not set
314
315#
316# Self-contained MTD device drivers
317#
318# CONFIG_MTD_PMC551 is not set
319# CONFIG_MTD_SLRAM is not set
320# CONFIG_MTD_PHRAM is not set
321# CONFIG_MTD_MTDRAM is not set
322# CONFIG_MTD_BLKMTD is not set
323# CONFIG_MTD_BLOCK2MTD is not set
324
325#
326# Disk-On-Chip Device Drivers
327#
328# CONFIG_MTD_DOC2000 is not set
329# CONFIG_MTD_DOC2001 is not set
330# CONFIG_MTD_DOC2001PLUS is not set
331
332#
333# NAND Flash Device Drivers
334#
335# CONFIG_MTD_NAND is not set
336
337#
338# OneNAND Flash Device Drivers
339#
340# CONFIG_MTD_ONENAND is not set
341
342#
343# Parallel port support
344#
345# CONFIG_PARPORT is not set
346
347#
348# Plug and Play support
349#
350
351#
352# Block devices
353#
354# CONFIG_BLK_DEV_FD is not set
355# CONFIG_BLK_CPQ_DA is not set
356# CONFIG_BLK_CPQ_CISS_DA is not set
357# CONFIG_BLK_DEV_DAC960 is not set
358# CONFIG_BLK_DEV_UMEM is not set
359# CONFIG_BLK_DEV_COW_COMMON is not set
360CONFIG_BLK_DEV_LOOP=y
361# CONFIG_BLK_DEV_CRYPTOLOOP is not set
362# CONFIG_BLK_DEV_NBD is not set
363# CONFIG_BLK_DEV_SX8 is not set
364CONFIG_BLK_DEV_RAM=y
365CONFIG_BLK_DEV_RAM_COUNT=16
366CONFIG_BLK_DEV_RAM_SIZE=32768
367CONFIG_BLK_DEV_INITRD=y
368# CONFIG_CDROM_PKTCDVD is not set
369# CONFIG_ATA_OVER_ETH is not set
370
371#
372# ATA/ATAPI/MFM/RLL support
373#
374CONFIG_IDE=y
375CONFIG_BLK_DEV_IDE=y
376
377#
378# Please see Documentation/ide.txt for help/info on IDE drives
379#
380# CONFIG_BLK_DEV_IDE_SATA is not set
381CONFIG_BLK_DEV_IDEDISK=y
382# CONFIG_IDEDISK_MULTI_MODE is not set
383# CONFIG_BLK_DEV_IDECD is not set
384# CONFIG_BLK_DEV_IDETAPE is not set
385# CONFIG_BLK_DEV_IDEFLOPPY is not set
386# CONFIG_IDE_TASK_IOCTL is not set
387
388#
389# IDE chipset support/bugfixes
390#
391CONFIG_IDE_GENERIC=y
392CONFIG_BLK_DEV_IDEPCI=y
393CONFIG_IDEPCI_SHARE_IRQ=y
394# CONFIG_BLK_DEV_OFFBOARD is not set
395CONFIG_BLK_DEV_GENERIC=y
396# CONFIG_BLK_DEV_OPTI621 is not set
397# CONFIG_BLK_DEV_SL82C105 is not set
398CONFIG_BLK_DEV_IDEDMA_PCI=y
399# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
400CONFIG_IDEDMA_PCI_AUTO=y
401# CONFIG_IDEDMA_ONLYDISK is not set
402# CONFIG_BLK_DEV_AEC62XX is not set
403# CONFIG_BLK_DEV_ALI15X3 is not set
404# CONFIG_BLK_DEV_AMD74XX is not set
405# CONFIG_BLK_DEV_CMD64X is not set
406# CONFIG_BLK_DEV_TRIFLEX is not set
407# CONFIG_BLK_DEV_CY82C693 is not set
408# CONFIG_BLK_DEV_CS5520 is not set
409# CONFIG_BLK_DEV_CS5530 is not set
410# CONFIG_BLK_DEV_HPT34X is not set
411# CONFIG_BLK_DEV_HPT366 is not set
412# CONFIG_BLK_DEV_SC1200 is not set
413# CONFIG_BLK_DEV_PIIX is not set
414# CONFIG_BLK_DEV_IT821X is not set
415# CONFIG_BLK_DEV_NS87415 is not set
416# CONFIG_BLK_DEV_PDC202XX_OLD is not set
417# CONFIG_BLK_DEV_PDC202XX_NEW is not set
418# CONFIG_BLK_DEV_SVWKS is not set
419# CONFIG_BLK_DEV_SIIMAGE is not set
420# CONFIG_BLK_DEV_SLC90E66 is not set
421# CONFIG_BLK_DEV_TRM290 is not set
422CONFIG_BLK_DEV_VIA82CXXX=y
423# CONFIG_IDE_ARM is not set
424CONFIG_BLK_DEV_IDEDMA=y
425# CONFIG_IDEDMA_IVB is not set
426CONFIG_IDEDMA_AUTO=y
427# CONFIG_BLK_DEV_HD is not set
428
429#
430# SCSI device support
431#
432# CONFIG_RAID_ATTRS is not set
433# CONFIG_SCSI is not set
434
435#
436# Multi-device support (RAID and LVM)
437#
438# CONFIG_MD is not set
439
440#
441# Fusion MPT device support
442#
443# CONFIG_FUSION is not set
444
445#
446# IEEE 1394 (FireWire) support
447#
448# CONFIG_IEEE1394 is not set
449
450#
451# I2O device support
452#
453# CONFIG_I2O is not set
454
455#
456# Macintosh device drivers
457#
458# CONFIG_WINDFARM is not set
459
460#
461# Network device support
462#
463CONFIG_NETDEVICES=y
464# CONFIG_DUMMY is not set
465# CONFIG_BONDING is not set
466# CONFIG_EQUALIZER is not set
467# CONFIG_TUN is not set
468
469#
470# ARCnet devices
471#
472# CONFIG_ARCNET is not set
473
474#
475# PHY device support
476#
477CONFIG_PHYLIB=y
478
479#
480# MII PHY device drivers
481#
482# CONFIG_MARVELL_PHY is not set
483# CONFIG_DAVICOM_PHY is not set
484# CONFIG_QSEMI_PHY is not set
485# CONFIG_LXT_PHY is not set
486# CONFIG_CICADA_PHY is not set
487
488#
489# Ethernet (10 or 100Mbit)
490#
491CONFIG_NET_ETHERNET=y
492CONFIG_MII=y
493# CONFIG_HAPPYMEAL is not set
494# CONFIG_SUNGEM is not set
495# CONFIG_CASSINI is not set
496# CONFIG_NET_VENDOR_3COM is not set
497
498#
499# Tulip family network device support
500#
501# CONFIG_NET_TULIP is not set
502# CONFIG_HP100 is not set
503CONFIG_NET_PCI=y
504# CONFIG_PCNET32 is not set
505# CONFIG_AMD8111_ETH is not set
506# CONFIG_ADAPTEC_STARFIRE is not set
507# CONFIG_B44 is not set
508# CONFIG_FORCEDETH is not set
509# CONFIG_DGRS is not set
510# CONFIG_EEPRO100 is not set
511CONFIG_E100=y
512# CONFIG_FEALNX is not set
513# CONFIG_NATSEMI is not set
514# CONFIG_NE2K_PCI is not set
515# CONFIG_8139CP is not set
516# CONFIG_8139TOO is not set
517# CONFIG_SIS900 is not set
518# CONFIG_EPIC100 is not set
519# CONFIG_SUNDANCE is not set
520# CONFIG_TLAN is not set
521# CONFIG_VIA_RHINE is not set
522# CONFIG_FS_ENET is not set
523
524#
525# Ethernet (1000 Mbit)
526#
527# CONFIG_ACENIC is not set
528# CONFIG_DL2K is not set
529# CONFIG_E1000 is not set
530# CONFIG_NS83820 is not set
531# CONFIG_HAMACHI is not set
532# CONFIG_YELLOWFIN is not set
533# CONFIG_R8169 is not set
534# CONFIG_SIS190 is not set
535# CONFIG_SKGE is not set
536# CONFIG_SK98LIN is not set
537# CONFIG_VIA_VELOCITY is not set
538# CONFIG_TIGON3 is not set
539# CONFIG_BNX2 is not set
540CONFIG_GIANFAR=y
541CONFIG_GFAR_NAPI=y
542
543#
544# Ethernet (10000 Mbit)
545#
546# CONFIG_CHELSIO_T1 is not set
547# CONFIG_IXGB is not set
548# CONFIG_S2IO is not set
549
550#
551# Token Ring devices
552#
553# CONFIG_TR is not set
554
555#
556# Wireless LAN (non-hamradio)
557#
558# CONFIG_NET_RADIO is not set
559
560#
561# Wan interfaces
562#
563# CONFIG_WAN is not set
564# CONFIG_FDDI is not set
565# CONFIG_HIPPI is not set
566# CONFIG_PPP is not set
567# CONFIG_SLIP is not set
568# CONFIG_SHAPER is not set
569# CONFIG_NETCONSOLE is not set
570# CONFIG_NETPOLL is not set
571# CONFIG_NET_POLL_CONTROLLER is not set
572
573#
574# ISDN subsystem
575#
576# CONFIG_ISDN is not set
577
578#
579# Telephony Support
580#
581# CONFIG_PHONE is not set
582
583#
584# Input device support
585#
586CONFIG_INPUT=y
587
588#
589# Userland interfaces
590#
591# CONFIG_INPUT_MOUSEDEV is not set
592# CONFIG_INPUT_JOYDEV is not set
593# CONFIG_INPUT_TSDEV is not set
594# CONFIG_INPUT_EVDEV is not set
595# CONFIG_INPUT_EVBUG is not set
596
597#
598# Input Device Drivers
599#
600# CONFIG_INPUT_KEYBOARD is not set
601# CONFIG_INPUT_MOUSE is not set
602# CONFIG_INPUT_JOYSTICK is not set
603# CONFIG_INPUT_TOUCHSCREEN is not set
604# CONFIG_INPUT_MISC is not set
605
606#
607# Hardware I/O ports
608#
609# CONFIG_SERIO is not set
610# CONFIG_GAMEPORT is not set
611
612#
613# Character devices
614#
615# CONFIG_VT is not set
616# CONFIG_SERIAL_NONSTANDARD is not set
617
618#
619# Serial drivers
620#
621CONFIG_SERIAL_8250=y
622CONFIG_SERIAL_8250_CONSOLE=y
623CONFIG_SERIAL_8250_NR_UARTS=4
624# CONFIG_SERIAL_8250_EXTENDED is not set
625
626#
627# Non-8250 serial port support
628#
629CONFIG_SERIAL_CORE=y
630CONFIG_SERIAL_CORE_CONSOLE=y
631# CONFIG_SERIAL_CPM is not set
632# CONFIG_SERIAL_JSM is not set
633CONFIG_UNIX98_PTYS=y
634CONFIG_LEGACY_PTYS=y
635CONFIG_LEGACY_PTY_COUNT=256
636
637#
638# IPMI
639#
640# CONFIG_IPMI_HANDLER is not set
641
642#
643# Watchdog Cards
644#
645# CONFIG_WATCHDOG is not set
646# CONFIG_NVRAM is not set
647CONFIG_GEN_RTC=y
648# CONFIG_GEN_RTC_X is not set
649# CONFIG_DTLK is not set
650# CONFIG_R3964 is not set
651# CONFIG_APPLICOM is not set
652
653#
654# Ftape, the floppy tape device driver
655#
656# CONFIG_AGP is not set
657# CONFIG_DRM is not set
658# CONFIG_RAW_DRIVER is not set
659
660#
661# TPM devices
662#
663# CONFIG_TCG_TPM is not set
664# CONFIG_TELCLOCK is not set
665
666#
667# I2C support
668#
669CONFIG_I2C=y
670CONFIG_I2C_CHARDEV=y
671
672#
673# I2C Algorithms
674#
675# CONFIG_I2C_ALGOBIT is not set
676# CONFIG_I2C_ALGOPCF is not set
677# CONFIG_I2C_ALGOPCA is not set
678
679#
680# I2C Hardware Bus support
681#
682# CONFIG_I2C_ALI1535 is not set
683# CONFIG_I2C_ALI1563 is not set
684# CONFIG_I2C_ALI15X3 is not set
685# CONFIG_I2C_AMD756 is not set
686# CONFIG_I2C_AMD8111 is not set
687# CONFIG_I2C_I801 is not set
688# CONFIG_I2C_I810 is not set
689# CONFIG_I2C_PIIX4 is not set
690CONFIG_I2C_MPC=y
691# CONFIG_I2C_NFORCE2 is not set
692# CONFIG_I2C_PARPORT_LIGHT is not set
693# CONFIG_I2C_PROSAVAGE is not set
694# CONFIG_I2C_SAVAGE4 is not set
695# CONFIG_SCx200_ACB is not set
696# CONFIG_I2C_SIS5595 is not set
697# CONFIG_I2C_SIS630 is not set
698# CONFIG_I2C_SIS96X is not set
699# CONFIG_I2C_VIA is not set
700# CONFIG_I2C_VIAPRO is not set
701# CONFIG_I2C_VOODOO3 is not set
702# CONFIG_I2C_PCA_ISA is not set
703
704#
705# Miscellaneous I2C Chip support
706#
707CONFIG_SENSORS_DS1337=y
708# CONFIG_SENSORS_DS1374 is not set
709# CONFIG_SENSORS_EEPROM is not set
710# CONFIG_SENSORS_PCF8574 is not set
711# CONFIG_SENSORS_PCA9539 is not set
712# CONFIG_SENSORS_PCF8591 is not set
713# CONFIG_SENSORS_RTC8564 is not set
714# CONFIG_SENSORS_M41T00 is not set
715# CONFIG_SENSORS_MAX6875 is not set
716# CONFIG_RTC_X1205_I2C is not set
717# CONFIG_I2C_DEBUG_CORE is not set
718# CONFIG_I2C_DEBUG_ALGO is not set
719# CONFIG_I2C_DEBUG_BUS is not set
720# CONFIG_I2C_DEBUG_CHIP is not set
721
722#
723# Dallas's 1-wire bus
724#
725# CONFIG_W1 is not set
726
727#
728# Hardware Monitoring support
729#
730CONFIG_HWMON=y
731# CONFIG_HWMON_VID is not set
732# CONFIG_SENSORS_ADM1021 is not set
733# CONFIG_SENSORS_ADM1025 is not set
734# CONFIG_SENSORS_ADM1026 is not set
735# CONFIG_SENSORS_ADM1031 is not set
736# CONFIG_SENSORS_ADM9240 is not set
737# CONFIG_SENSORS_ASB100 is not set
738# CONFIG_SENSORS_ATXP1 is not set
739# CONFIG_SENSORS_DS1621 is not set
740# CONFIG_SENSORS_FSCHER is not set
741# CONFIG_SENSORS_FSCPOS is not set
742# CONFIG_SENSORS_GL518SM is not set
743# CONFIG_SENSORS_GL520SM is not set
744# CONFIG_SENSORS_IT87 is not set
745# CONFIG_SENSORS_LM63 is not set
746CONFIG_SENSORS_LM75=y
747# CONFIG_SENSORS_LM77 is not set
748# CONFIG_SENSORS_LM78 is not set
749# CONFIG_SENSORS_LM80 is not set
750# CONFIG_SENSORS_LM83 is not set
751# CONFIG_SENSORS_LM85 is not set
752# CONFIG_SENSORS_LM87 is not set
753# CONFIG_SENSORS_LM90 is not set
754# CONFIG_SENSORS_LM92 is not set
755# CONFIG_SENSORS_MAX1619 is not set
756# CONFIG_SENSORS_PC87360 is not set
757# CONFIG_SENSORS_SIS5595 is not set
758# CONFIG_SENSORS_SMSC47M1 is not set
759# CONFIG_SENSORS_SMSC47B397 is not set
760# CONFIG_SENSORS_VIA686A is not set
761# CONFIG_SENSORS_W83781D is not set
762# CONFIG_SENSORS_W83792D is not set
763# CONFIG_SENSORS_W83L785TS is not set
764# CONFIG_SENSORS_W83627HF is not set
765# CONFIG_SENSORS_W83627EHF is not set
766CONFIG_HWMON_DEBUG_CHIP=y
767
768#
769# Misc devices
770#
771
772#
773# Multimedia Capabilities Port drivers
774#
775
776#
777# Multimedia devices
778#
779# CONFIG_VIDEO_DEV is not set
780
781#
782# Digital Video Broadcasting Devices
783#
784# CONFIG_DVB is not set
785
786#
787# Graphics support
788#
789# CONFIG_FB is not set
790
791#
792# Sound
793#
794# CONFIG_SOUND is not set
795
796#
797# USB support
798#
799CONFIG_USB_ARCH_HAS_HCD=y
800CONFIG_USB_ARCH_HAS_OHCI=y
801# CONFIG_USB is not set
802
803#
804# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
805#
806
807#
808# USB Gadget Support
809#
810# CONFIG_USB_GADGET is not set
811
812#
813# MMC/SD Card support
814#
815# CONFIG_MMC is not set
816
817#
818# InfiniBand support
819#
820# CONFIG_INFINIBAND is not set
821
822#
823# SN Devices
824#
825
826#
827# File systems
828#
829CONFIG_EXT2_FS=y
830# CONFIG_EXT2_FS_XATTR is not set
831# CONFIG_EXT2_FS_XIP is not set
832CONFIG_EXT3_FS=y
833CONFIG_EXT3_FS_XATTR=y
834# CONFIG_EXT3_FS_POSIX_ACL is not set
835# CONFIG_EXT3_FS_SECURITY is not set
836CONFIG_JBD=y
837# CONFIG_JBD_DEBUG is not set
838CONFIG_FS_MBCACHE=y
839# CONFIG_REISERFS_FS is not set
840# CONFIG_JFS_FS is not set
841# CONFIG_FS_POSIX_ACL is not set
842# CONFIG_XFS_FS is not set
843# CONFIG_MINIX_FS is not set
844# CONFIG_ROMFS_FS is not set
845CONFIG_INOTIFY=y
846# CONFIG_QUOTA is not set
847CONFIG_DNOTIFY=y
848# CONFIG_AUTOFS_FS is not set
849# CONFIG_AUTOFS4_FS is not set
850# CONFIG_FUSE_FS is not set
851
852#
853# CD-ROM/DVD Filesystems
854#
855# CONFIG_ISO9660_FS is not set
856# CONFIG_UDF_FS is not set
857
858#
859# DOS/FAT/NT Filesystems
860#
861# CONFIG_MSDOS_FS is not set
862# CONFIG_VFAT_FS is not set
863# CONFIG_NTFS_FS is not set
864
865#
866# Pseudo filesystems
867#
868CONFIG_PROC_FS=y
869CONFIG_PROC_KCORE=y
870CONFIG_SYSFS=y
871CONFIG_TMPFS=y
872# CONFIG_HUGETLB_PAGE is not set
873CONFIG_RAMFS=y
874# CONFIG_RELAYFS_FS is not set
875
876#
877# Miscellaneous filesystems
878#
879# CONFIG_ADFS_FS is not set
880# CONFIG_AFFS_FS is not set
881# CONFIG_HFS_FS is not set
882# CONFIG_HFSPLUS_FS is not set
883# CONFIG_BEFS_FS is not set
884# CONFIG_BFS_FS is not set
885# CONFIG_EFS_FS is not set
886# CONFIG_JFFS_FS is not set
887CONFIG_JFFS2_FS=y
888CONFIG_JFFS2_FS_DEBUG=0
889CONFIG_JFFS2_FS_WRITEBUFFER=y
890# CONFIG_JFFS2_SUMMARY is not set
891# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
892CONFIG_JFFS2_ZLIB=y
893CONFIG_JFFS2_RTIME=y
894# CONFIG_JFFS2_RUBIN is not set
895CONFIG_CRAMFS=y
896# CONFIG_VXFS_FS is not set
897# CONFIG_HPFS_FS is not set
898# CONFIG_QNX4FS_FS is not set
899# CONFIG_SYSV_FS is not set
900# CONFIG_UFS_FS is not set
901
902#
903# Network File Systems
904#
905CONFIG_NFS_FS=y
906# CONFIG_NFS_V3 is not set
907# CONFIG_NFS_V4 is not set
908# CONFIG_NFS_DIRECTIO is not set
909# CONFIG_NFSD is not set
910CONFIG_ROOT_NFS=y
911CONFIG_LOCKD=y
912CONFIG_NFS_COMMON=y
913CONFIG_SUNRPC=y
914# CONFIG_RPCSEC_GSS_KRB5 is not set
915# CONFIG_RPCSEC_GSS_SPKM3 is not set
916# CONFIG_SMB_FS is not set
917# CONFIG_CIFS is not set
918# CONFIG_NCP_FS is not set
919# CONFIG_CODA_FS is not set
920# CONFIG_AFS_FS is not set
921# CONFIG_9P_FS is not set
922
923#
924# Partition Types
925#
926CONFIG_PARTITION_ADVANCED=y
927# CONFIG_ACORN_PARTITION is not set
928# CONFIG_OSF_PARTITION is not set
929# CONFIG_AMIGA_PARTITION is not set
930# CONFIG_ATARI_PARTITION is not set
931# CONFIG_MAC_PARTITION is not set
932# CONFIG_MSDOS_PARTITION is not set
933# CONFIG_LDM_PARTITION is not set
934# CONFIG_SGI_PARTITION is not set
935# CONFIG_ULTRIX_PARTITION is not set
936# CONFIG_SUN_PARTITION is not set
937# CONFIG_EFI_PARTITION is not set
938
939#
940# Native Language Support
941#
942# CONFIG_NLS is not set
943# CONFIG_SCC_ENET is not set
944# CONFIG_FEC_ENET is not set
945
946#
947# CPM2 Options
948#
949
950#
951# Library routines
952#
953# CONFIG_CRC_CCITT is not set
954# CONFIG_CRC16 is not set
955CONFIG_CRC32=y
956# CONFIG_LIBCRC32C is not set
957CONFIG_ZLIB_INFLATE=y
958CONFIG_ZLIB_DEFLATE=y
959# CONFIG_PROFILING is not set
960
961#
962# Kernel hacking
963#
964# CONFIG_PRINTK_TIME is not set
965# CONFIG_DEBUG_KERNEL is not set
966CONFIG_LOG_BUF_SHIFT=14
967# CONFIG_KGDB_CONSOLE is not set
968# CONFIG_SERIAL_TEXT_DEBUG is not set
969
970#
971# Security options
972#
973# CONFIG_KEYS is not set
974# CONFIG_SECURITY is not set
975
976#
977# Cryptographic options
978#
979# CONFIG_CRYPTO is not set
980
981#
982# Hardware crypto devices
983#
diff --git a/arch/ppc/configs/TQM8560_defconfig b/arch/ppc/configs/TQM8560_defconfig
new file mode 100644
index 0000000000..1d90207282
--- /dev/null
+++ b/arch/ppc/configs/TQM8560_defconfig
@@ -0,0 +1,992 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15-rc2
4# Wed Nov 30 16:47:53 2005
5#
6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y
8CONFIG_RWSEM_XCHGADD_ALGORITHM=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_PPC=y
11CONFIG_PPC32=y
12CONFIG_GENERIC_NVRAM=y
13CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
15
16#
17# Code maturity level options
18#
19CONFIG_EXPERIMENTAL=y
20CONFIG_CLEAN_COMPILE=y
21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
23
24#
25# General setup
26#
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SWAP=y
30CONFIG_SYSVIPC=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33CONFIG_SYSCTL=y
34# CONFIG_AUDIT is not set
35# CONFIG_HOTPLUG is not set
36CONFIG_KOBJECT_UEVENT=y
37# CONFIG_IKCONFIG is not set
38CONFIG_INITRAMFS_SOURCE=""
39CONFIG_EMBEDDED=y
40# CONFIG_KALLSYMS is not set
41CONFIG_PRINTK=y
42CONFIG_BUG=y
43CONFIG_BASE_FULL=y
44CONFIG_FUTEX=y
45# CONFIG_EPOLL is not set
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SHMEM=y
48CONFIG_CC_ALIGN_FUNCTIONS=0
49CONFIG_CC_ALIGN_LABELS=0
50CONFIG_CC_ALIGN_LOOPS=0
51CONFIG_CC_ALIGN_JUMPS=0
52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
54
55#
56# Loadable module support
57#
58# CONFIG_MODULES is not set
59
60#
61# Block layer
62#
63# CONFIG_LBD is not set
64
65#
66# IO Schedulers
67#
68CONFIG_IOSCHED_NOOP=y
69CONFIG_IOSCHED_AS=y
70CONFIG_IOSCHED_DEADLINE=y
71CONFIG_IOSCHED_CFQ=y
72CONFIG_DEFAULT_AS=y
73# CONFIG_DEFAULT_DEADLINE is not set
74# CONFIG_DEFAULT_CFQ is not set
75# CONFIG_DEFAULT_NOOP is not set
76CONFIG_DEFAULT_IOSCHED="anticipatory"
77
78#
79# Processor
80#
81# CONFIG_6xx is not set
82# CONFIG_40x is not set
83# CONFIG_44x is not set
84# CONFIG_POWER3 is not set
85# CONFIG_POWER4 is not set
86# CONFIG_8xx is not set
87# CONFIG_E200 is not set
88CONFIG_E500=y
89CONFIG_BOOKE=y
90CONFIG_FSL_BOOKE=y
91# CONFIG_PHYS_64BIT is not set
92CONFIG_SPE=y
93CONFIG_MATH_EMULATION=y
94# CONFIG_KEXEC is not set
95# CONFIG_CPU_FREQ is not set
96# CONFIG_WANT_EARLY_SERIAL is not set
97CONFIG_85xx=y
98CONFIG_PPC_INDIRECT_PCI_BE=y
99
100#
101# Freescale 85xx options
102#
103# CONFIG_MPC8540_ADS is not set
104# CONFIG_MPC8548_CDS is not set
105# CONFIG_MPC8555_CDS is not set
106# CONFIG_MPC8560_ADS is not set
107# CONFIG_SBC8560 is not set
108# CONFIG_STX_GP3 is not set
109# CONFIG_TQM8540 is not set
110# CONFIG_TQM8541 is not set
111# CONFIG_TQM8555 is not set
112CONFIG_TQM8560=y
113CONFIG_MPC8560=y
114
115#
116# Platform options
117#
118CONFIG_CPM2=y
119# CONFIG_PC_KEYBOARD is not set
120# CONFIG_HIGHMEM is not set
121# CONFIG_HZ_100 is not set
122CONFIG_HZ_250=y
123# CONFIG_HZ_1000 is not set
124CONFIG_HZ=250
125CONFIG_PREEMPT_NONE=y
126# CONFIG_PREEMPT_VOLUNTARY is not set
127# CONFIG_PREEMPT is not set
128CONFIG_SELECT_MEMORY_MODEL=y
129CONFIG_FLATMEM_MANUAL=y
130# CONFIG_DISCONTIGMEM_MANUAL is not set
131# CONFIG_SPARSEMEM_MANUAL is not set
132CONFIG_FLATMEM=y
133CONFIG_FLAT_NODE_MEM_MAP=y
134# CONFIG_SPARSEMEM_STATIC is not set
135CONFIG_SPLIT_PTLOCK_CPUS=4
136CONFIG_BINFMT_ELF=y
137# CONFIG_BINFMT_MISC is not set
138# CONFIG_CMDLINE_BOOL is not set
139# CONFIG_PM is not set
140# CONFIG_SOFTWARE_SUSPEND is not set
141CONFIG_SECCOMP=y
142CONFIG_ISA_DMA_API=y
143
144#
145# Bus options
146#
147CONFIG_PPC_I8259=y
148CONFIG_PPC_INDIRECT_PCI=y
149CONFIG_PCI=y
150CONFIG_PCI_DOMAINS=y
151# CONFIG_PCI_LEGACY_PROC is not set
152
153#
154# PCCARD (PCMCIA/CardBus) support
155#
156# CONFIG_PCCARD is not set
157# CONFIG_RAPIDIO is not set
158
159#
160# Advanced setup
161#
162# CONFIG_ADVANCED_OPTIONS is not set
163
164#
165# Default settings for advanced configuration options are used
166#
167CONFIG_HIGHMEM_START=0xfe000000
168CONFIG_LOWMEM_SIZE=0x30000000
169CONFIG_KERNEL_START=0xc0000000
170CONFIG_TASK_SIZE=0x80000000
171CONFIG_BOOT_LOAD=0x00800000
172
173#
174# Networking
175#
176CONFIG_NET=y
177
178#
179# Networking options
180#
181CONFIG_PACKET=y
182# CONFIG_PACKET_MMAP is not set
183CONFIG_UNIX=y
184# CONFIG_NET_KEY is not set
185CONFIG_INET=y
186CONFIG_IP_MULTICAST=y
187# CONFIG_IP_ADVANCED_ROUTER is not set
188CONFIG_IP_FIB_HASH=y
189CONFIG_IP_PNP=y
190CONFIG_IP_PNP_DHCP=y
191CONFIG_IP_PNP_BOOTP=y
192# CONFIG_IP_PNP_RARP is not set
193# CONFIG_NET_IPIP is not set
194# CONFIG_NET_IPGRE is not set
195# CONFIG_IP_MROUTE is not set
196# CONFIG_ARPD is not set
197CONFIG_SYN_COOKIES=y
198# CONFIG_INET_AH is not set
199# CONFIG_INET_ESP is not set
200# CONFIG_INET_IPCOMP is not set
201# CONFIG_INET_TUNNEL is not set
202CONFIG_INET_DIAG=y
203CONFIG_INET_TCP_DIAG=y
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_BIC=y
206# CONFIG_IPV6 is not set
207# CONFIG_NETFILTER is not set
208
209#
210# DCCP Configuration (EXPERIMENTAL)
211#
212# CONFIG_IP_DCCP is not set
213
214#
215# SCTP Configuration (EXPERIMENTAL)
216#
217# CONFIG_IP_SCTP is not set
218# CONFIG_ATM is not set
219# CONFIG_BRIDGE is not set
220# CONFIG_VLAN_8021Q is not set
221# CONFIG_DECNET is not set
222# CONFIG_LLC2 is not set
223# CONFIG_IPX is not set
224# CONFIG_ATALK is not set
225# CONFIG_X25 is not set
226# CONFIG_LAPB is not set
227# CONFIG_NET_DIVERT is not set
228# CONFIG_ECONET is not set
229# CONFIG_WAN_ROUTER is not set
230
231#
232# QoS and/or fair queueing
233#
234# CONFIG_NET_SCHED is not set
235
236#
237# Network testing
238#
239# CONFIG_NET_PKTGEN is not set
240# CONFIG_HAMRADIO is not set
241# CONFIG_IRDA is not set
242# CONFIG_BT is not set
243# CONFIG_IEEE80211 is not set
244
245#
246# Device Drivers
247#
248
249#
250# Generic Driver Options
251#
252CONFIG_STANDALONE=y
253CONFIG_PREVENT_FIRMWARE_BUILD=y
254# CONFIG_FW_LOADER is not set
255
256#
257# Connector - unified userspace <-> kernelspace linker
258#
259# CONFIG_CONNECTOR is not set
260
261#
262# Memory Technology Devices (MTD)
263#
264CONFIG_MTD=y
265# CONFIG_MTD_DEBUG is not set
266CONFIG_MTD_CONCAT=y
267CONFIG_MTD_PARTITIONS=y
268# CONFIG_MTD_REDBOOT_PARTS is not set
269CONFIG_MTD_CMDLINE_PARTS=y
270
271#
272# User Modules And Translation Layers
273#
274CONFIG_MTD_CHAR=y
275CONFIG_MTD_BLOCK=y
276# CONFIG_FTL is not set
277# CONFIG_NFTL is not set
278# CONFIG_INFTL is not set
279# CONFIG_RFD_FTL is not set
280
281#
282# RAM/ROM/Flash chip drivers
283#
284CONFIG_MTD_CFI=y
285# CONFIG_MTD_JEDECPROBE is not set
286CONFIG_MTD_GEN_PROBE=y
287# CONFIG_MTD_CFI_ADV_OPTIONS is not set
288CONFIG_MTD_MAP_BANK_WIDTH_1=y
289CONFIG_MTD_MAP_BANK_WIDTH_2=y
290CONFIG_MTD_MAP_BANK_WIDTH_4=y
291# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
292# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
293# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
294CONFIG_MTD_CFI_I1=y
295CONFIG_MTD_CFI_I2=y
296# CONFIG_MTD_CFI_I4 is not set
297# CONFIG_MTD_CFI_I8 is not set
298# CONFIG_MTD_CFI_INTELEXT is not set
299CONFIG_MTD_CFI_AMDSTD=y
300CONFIG_MTD_CFI_AMDSTD_RETRY=0
301# CONFIG_MTD_CFI_STAA is not set
302CONFIG_MTD_CFI_UTIL=y
303# CONFIG_MTD_RAM is not set
304# CONFIG_MTD_ROM is not set
305# CONFIG_MTD_ABSENT is not set
306
307#
308# Mapping drivers for chip access
309#
310# CONFIG_MTD_COMPLEX_MAPPINGS is not set
311# CONFIG_MTD_PHYSMAP is not set
312CONFIG_MTD_TQM85xx=y
313# CONFIG_MTD_PLATRAM is not set
314
315#
316# Self-contained MTD device drivers
317#
318# CONFIG_MTD_PMC551 is not set
319# CONFIG_MTD_SLRAM is not set
320# CONFIG_MTD_PHRAM is not set
321# CONFIG_MTD_MTDRAM is not set
322# CONFIG_MTD_BLKMTD is not set
323# CONFIG_MTD_BLOCK2MTD is not set
324
325#
326# Disk-On-Chip Device Drivers
327#
328# CONFIG_MTD_DOC2000 is not set
329# CONFIG_MTD_DOC2001 is not set
330# CONFIG_MTD_DOC2001PLUS is not set
331
332#
333# NAND Flash Device Drivers
334#
335# CONFIG_MTD_NAND is not set
336
337#
338# OneNAND Flash Device Drivers
339#
340# CONFIG_MTD_ONENAND is not set
341
342#
343# Parallel port support
344#
345# CONFIG_PARPORT is not set
346
347#
348# Plug and Play support
349#
350
351#
352# Block devices
353#
354# CONFIG_BLK_DEV_FD is not set
355# CONFIG_BLK_CPQ_DA is not set
356# CONFIG_BLK_CPQ_CISS_DA is not set
357# CONFIG_BLK_DEV_DAC960 is not set
358# CONFIG_BLK_DEV_UMEM is not set
359# CONFIG_BLK_DEV_COW_COMMON is not set
360CONFIG_BLK_DEV_LOOP=y
361# CONFIG_BLK_DEV_CRYPTOLOOP is not set
362# CONFIG_BLK_DEV_NBD is not set
363# CONFIG_BLK_DEV_SX8 is not set
364CONFIG_BLK_DEV_RAM=y
365CONFIG_BLK_DEV_RAM_COUNT=16
366CONFIG_BLK_DEV_RAM_SIZE=32768
367CONFIG_BLK_DEV_INITRD=y
368# CONFIG_CDROM_PKTCDVD is not set
369# CONFIG_ATA_OVER_ETH is not set
370
371#
372# ATA/ATAPI/MFM/RLL support
373#
374CONFIG_IDE=y
375CONFIG_BLK_DEV_IDE=y
376
377#
378# Please see Documentation/ide.txt for help/info on IDE drives
379#
380# CONFIG_BLK_DEV_IDE_SATA is not set
381CONFIG_BLK_DEV_IDEDISK=y
382# CONFIG_IDEDISK_MULTI_MODE is not set
383# CONFIG_BLK_DEV_IDECD is not set
384# CONFIG_BLK_DEV_IDETAPE is not set
385# CONFIG_BLK_DEV_IDEFLOPPY is not set
386# CONFIG_IDE_TASK_IOCTL is not set
387
388#
389# IDE chipset support/bugfixes
390#
391CONFIG_IDE_GENERIC=y
392CONFIG_BLK_DEV_IDEPCI=y
393CONFIG_IDEPCI_SHARE_IRQ=y
394# CONFIG_BLK_DEV_OFFBOARD is not set
395CONFIG_BLK_DEV_GENERIC=y
396# CONFIG_BLK_DEV_OPTI621 is not set
397# CONFIG_BLK_DEV_SL82C105 is not set
398CONFIG_BLK_DEV_IDEDMA_PCI=y
399# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
400CONFIG_IDEDMA_PCI_AUTO=y
401# CONFIG_IDEDMA_ONLYDISK is not set
402# CONFIG_BLK_DEV_AEC62XX is not set
403# CONFIG_BLK_DEV_ALI15X3 is not set
404# CONFIG_BLK_DEV_AMD74XX is not set
405# CONFIG_BLK_DEV_CMD64X is not set
406# CONFIG_BLK_DEV_TRIFLEX is not set
407# CONFIG_BLK_DEV_CY82C693 is not set
408# CONFIG_BLK_DEV_CS5520 is not set
409# CONFIG_BLK_DEV_CS5530 is not set
410# CONFIG_BLK_DEV_HPT34X is not set
411# CONFIG_BLK_DEV_HPT366 is not set
412# CONFIG_BLK_DEV_SC1200 is not set
413# CONFIG_BLK_DEV_PIIX is not set
414# CONFIG_BLK_DEV_IT821X is not set
415# CONFIG_BLK_DEV_NS87415 is not set
416# CONFIG_BLK_DEV_PDC202XX_OLD is not set
417# CONFIG_BLK_DEV_PDC202XX_NEW is not set
418# CONFIG_BLK_DEV_SVWKS is not set
419# CONFIG_BLK_DEV_SIIMAGE is not set
420# CONFIG_BLK_DEV_SLC90E66 is not set
421# CONFIG_BLK_DEV_TRM290 is not set
422CONFIG_BLK_DEV_VIA82CXXX=y
423# CONFIG_IDE_ARM is not set
424CONFIG_BLK_DEV_IDEDMA=y
425# CONFIG_IDEDMA_IVB is not set
426CONFIG_IDEDMA_AUTO=y
427# CONFIG_BLK_DEV_HD is not set
428
429#
430# SCSI device support
431#
432# CONFIG_RAID_ATTRS is not set
433# CONFIG_SCSI is not set
434
435#
436# Multi-device support (RAID and LVM)
437#
438# CONFIG_MD is not set
439
440#
441# Fusion MPT device support
442#
443# CONFIG_FUSION is not set
444
445#
446# IEEE 1394 (FireWire) support
447#
448# CONFIG_IEEE1394 is not set
449
450#
451# I2O device support
452#
453# CONFIG_I2O is not set
454
455#
456# Macintosh device drivers
457#
458# CONFIG_WINDFARM is not set
459
460#
461# Network device support
462#
463CONFIG_NETDEVICES=y
464# CONFIG_DUMMY is not set
465# CONFIG_BONDING is not set
466# CONFIG_EQUALIZER is not set
467# CONFIG_TUN is not set
468
469#
470# ARCnet devices
471#
472# CONFIG_ARCNET is not set
473
474#
475# PHY device support
476#
477CONFIG_PHYLIB=y
478
479#
480# MII PHY device drivers
481#
482# CONFIG_MARVELL_PHY is not set
483# CONFIG_DAVICOM_PHY is not set
484# CONFIG_QSEMI_PHY is not set
485# CONFIG_LXT_PHY is not set
486# CONFIG_CICADA_PHY is not set
487
488#
489# Ethernet (10 or 100Mbit)
490#
491CONFIG_NET_ETHERNET=y
492CONFIG_MII=y
493# CONFIG_HAPPYMEAL is not set
494# CONFIG_SUNGEM is not set
495# CONFIG_CASSINI is not set
496# CONFIG_NET_VENDOR_3COM is not set
497
498#
499# Tulip family network device support
500#
501# CONFIG_NET_TULIP is not set
502# CONFIG_HP100 is not set
503CONFIG_NET_PCI=y
504# CONFIG_PCNET32 is not set
505# CONFIG_AMD8111_ETH is not set
506# CONFIG_ADAPTEC_STARFIRE is not set
507# CONFIG_B44 is not set
508# CONFIG_FORCEDETH is not set
509# CONFIG_DGRS is not set
510# CONFIG_EEPRO100 is not set
511CONFIG_E100=y
512# CONFIG_FEALNX is not set
513# CONFIG_NATSEMI is not set
514# CONFIG_NE2K_PCI is not set
515# CONFIG_8139CP is not set
516# CONFIG_8139TOO is not set
517# CONFIG_SIS900 is not set
518# CONFIG_EPIC100 is not set
519# CONFIG_SUNDANCE is not set
520# CONFIG_TLAN is not set
521# CONFIG_VIA_RHINE is not set
522# CONFIG_FS_ENET is not set
523
524#
525# Ethernet (1000 Mbit)
526#
527# CONFIG_ACENIC is not set
528# CONFIG_DL2K is not set
529# CONFIG_E1000 is not set
530# CONFIG_NS83820 is not set
531# CONFIG_HAMACHI is not set
532# CONFIG_YELLOWFIN is not set
533# CONFIG_R8169 is not set
534# CONFIG_SIS190 is not set
535# CONFIG_SKGE is not set
536# CONFIG_SK98LIN is not set
537# CONFIG_VIA_VELOCITY is not set
538# CONFIG_TIGON3 is not set
539# CONFIG_BNX2 is not set
540CONFIG_GIANFAR=y
541CONFIG_GFAR_NAPI=y
542
543#
544# Ethernet (10000 Mbit)
545#
546# CONFIG_CHELSIO_T1 is not set
547# CONFIG_IXGB is not set
548# CONFIG_S2IO is not set
549
550#
551# Token Ring devices
552#
553# CONFIG_TR is not set
554
555#
556# Wireless LAN (non-hamradio)
557#
558# CONFIG_NET_RADIO is not set
559
560#
561# Wan interfaces
562#
563# CONFIG_WAN is not set
564# CONFIG_FDDI is not set
565# CONFIG_HIPPI is not set
566# CONFIG_PPP is not set
567# CONFIG_SLIP is not set
568# CONFIG_SHAPER is not set
569# CONFIG_NETCONSOLE is not set
570# CONFIG_NETPOLL is not set
571# CONFIG_NET_POLL_CONTROLLER is not set
572
573#
574# ISDN subsystem
575#
576# CONFIG_ISDN is not set
577
578#
579# Telephony Support
580#
581# CONFIG_PHONE is not set
582
583#
584# Input device support
585#
586CONFIG_INPUT=y
587
588#
589# Userland interfaces
590#
591# CONFIG_INPUT_MOUSEDEV is not set
592# CONFIG_INPUT_JOYDEV is not set
593# CONFIG_INPUT_TSDEV is not set
594# CONFIG_INPUT_EVDEV is not set
595# CONFIG_INPUT_EVBUG is not set
596
597#
598# Input Device Drivers
599#
600# CONFIG_INPUT_KEYBOARD is not set
601# CONFIG_INPUT_MOUSE is not set
602# CONFIG_INPUT_JOYSTICK is not set
603# CONFIG_INPUT_TOUCHSCREEN is not set
604# CONFIG_INPUT_MISC is not set
605
606#
607# Hardware I/O ports
608#
609# CONFIG_SERIO is not set
610# CONFIG_GAMEPORT is not set
611
612#
613# Character devices
614#
615# CONFIG_VT is not set
616# CONFIG_SERIAL_NONSTANDARD is not set
617
618#
619# Serial drivers
620#
621CONFIG_SERIAL_8250=y
622CONFIG_SERIAL_8250_CONSOLE=y
623CONFIG_SERIAL_8250_NR_UARTS=4
624# CONFIG_SERIAL_8250_EXTENDED is not set
625
626#
627# Non-8250 serial port support
628#
629CONFIG_SERIAL_CORE=y
630CONFIG_SERIAL_CORE_CONSOLE=y
631CONFIG_SERIAL_CPM=y
632CONFIG_SERIAL_CPM_CONSOLE=y
633CONFIG_SERIAL_CPM_SCC1=y
634# CONFIG_SERIAL_CPM_SCC2 is not set
635# CONFIG_SERIAL_CPM_SCC3 is not set
636# CONFIG_SERIAL_CPM_SCC4 is not set
637# CONFIG_SERIAL_CPM_SMC1 is not set
638# CONFIG_SERIAL_CPM_SMC2 is not set
639# CONFIG_SERIAL_JSM is not set
640CONFIG_UNIX98_PTYS=y
641CONFIG_LEGACY_PTYS=y
642CONFIG_LEGACY_PTY_COUNT=256
643
644#
645# IPMI
646#
647# CONFIG_IPMI_HANDLER is not set
648
649#
650# Watchdog Cards
651#
652# CONFIG_WATCHDOG is not set
653# CONFIG_NVRAM is not set
654CONFIG_GEN_RTC=y
655# CONFIG_GEN_RTC_X is not set
656# CONFIG_DTLK is not set
657# CONFIG_R3964 is not set
658# CONFIG_APPLICOM is not set
659
660#
661# Ftape, the floppy tape device driver
662#
663# CONFIG_AGP is not set
664# CONFIG_DRM is not set
665# CONFIG_RAW_DRIVER is not set
666
667#
668# TPM devices
669#
670# CONFIG_TCG_TPM is not set
671# CONFIG_TELCLOCK is not set
672
673#
674# I2C support
675#
676CONFIG_I2C=y
677CONFIG_I2C_CHARDEV=y
678
679#
680# I2C Algorithms
681#
682# CONFIG_I2C_ALGOBIT is not set
683# CONFIG_I2C_ALGOPCF is not set
684# CONFIG_I2C_ALGOPCA is not set
685
686#
687# I2C Hardware Bus support
688#
689# CONFIG_I2C_ALI1535 is not set
690# CONFIG_I2C_ALI1563 is not set
691# CONFIG_I2C_ALI15X3 is not set
692# CONFIG_I2C_AMD756 is not set
693# CONFIG_I2C_AMD8111 is not set
694# CONFIG_I2C_I801 is not set
695# CONFIG_I2C_I810 is not set
696# CONFIG_I2C_PIIX4 is not set
697CONFIG_I2C_MPC=y
698# CONFIG_I2C_MPC8260 is not set
699# CONFIG_I2C_NFORCE2 is not set
700# CONFIG_I2C_PARPORT_LIGHT is not set
701# CONFIG_I2C_PROSAVAGE is not set
702# CONFIG_I2C_SAVAGE4 is not set
703# CONFIG_SCx200_ACB is not set
704# CONFIG_I2C_SIS5595 is not set
705# CONFIG_I2C_SIS630 is not set
706# CONFIG_I2C_SIS96X is not set
707# CONFIG_I2C_VIA is not set
708# CONFIG_I2C_VIAPRO is not set
709# CONFIG_I2C_VOODOO3 is not set
710# CONFIG_I2C_PCA_ISA is not set
711
712#
713# Miscellaneous I2C Chip support
714#
715CONFIG_SENSORS_DS1337=y
716# CONFIG_SENSORS_DS1374 is not set
717# CONFIG_SENSORS_EEPROM is not set
718# CONFIG_SENSORS_MAX6900 is not set
719# CONFIG_SENSORS_PCF8574 is not set
720# CONFIG_SENSORS_PCF8563 is not set
721# CONFIG_SENSORS_PCA9539 is not set
722# CONFIG_SENSORS_PCF8591 is not set
723# CONFIG_SENSORS_RTC8564 is not set
724# CONFIG_SENSORS_M41T00 is not set
725# CONFIG_SENSORS_MAX6875 is not set
726# CONFIG_RTC_X1205_I2C is not set
727# CONFIG_I2C_DEBUG_CORE is not set
728# CONFIG_I2C_DEBUG_ALGO is not set
729# CONFIG_I2C_DEBUG_BUS is not set
730# CONFIG_I2C_DEBUG_CHIP is not set
731
732#
733# Dallas's 1-wire bus
734#
735# CONFIG_W1 is not set
736
737#
738# Hardware Monitoring support
739#
740CONFIG_HWMON=y
741# CONFIG_HWMON_VID is not set
742# CONFIG_SENSORS_ADM1021 is not set
743# CONFIG_SENSORS_ADM1025 is not set
744# CONFIG_SENSORS_ADM1026 is not set
745# CONFIG_SENSORS_ADM1031 is not set
746# CONFIG_SENSORS_ADM9240 is not set
747# CONFIG_SENSORS_ASB100 is not set
748# CONFIG_SENSORS_ATXP1 is not set
749# CONFIG_SENSORS_DS1621 is not set
750# CONFIG_SENSORS_FSCHER is not set
751# CONFIG_SENSORS_FSCPOS is not set
752# CONFIG_SENSORS_GL518SM is not set
753# CONFIG_SENSORS_GL520SM is not set
754# CONFIG_SENSORS_IT87 is not set
755# CONFIG_SENSORS_LM63 is not set
756CONFIG_SENSORS_LM75=y
757# CONFIG_SENSORS_LM77 is not set
758# CONFIG_SENSORS_LM78 is not set
759# CONFIG_SENSORS_LM80 is not set
760# CONFIG_SENSORS_LM83 is not set
761# CONFIG_SENSORS_LM85 is not set
762# CONFIG_SENSORS_LM87 is not set
763# CONFIG_SENSORS_LM90 is not set
764# CONFIG_SENSORS_LM92 is not set
765# CONFIG_SENSORS_MAX1619 is not set
766# CONFIG_SENSORS_PC87360 is not set
767# CONFIG_SENSORS_SIS5595 is not set
768# CONFIG_SENSORS_SMSC47M1 is not set
769# CONFIG_SENSORS_SMSC47B397 is not set
770# CONFIG_SENSORS_VIA686A is not set
771# CONFIG_SENSORS_W83781D is not set
772# CONFIG_SENSORS_W83792D is not set
773# CONFIG_SENSORS_W83L785TS is not set
774# CONFIG_SENSORS_W83627HF is not set
775# CONFIG_SENSORS_W83627EHF is not set
776CONFIG_HWMON_DEBUG_CHIP=y
777
778#
779# Misc devices
780#
781
782#
783# Multimedia Capabilities Port drivers
784#
785
786#
787# Multimedia devices
788#
789# CONFIG_VIDEO_DEV is not set
790
791#
792# Digital Video Broadcasting Devices
793#
794# CONFIG_DVB is not set
795
796#
797# Graphics support
798#
799# CONFIG_FB is not set
800
801#
802# Sound
803#
804# CONFIG_SOUND is not set
805
806#
807# USB support
808#
809CONFIG_USB_ARCH_HAS_HCD=y
810CONFIG_USB_ARCH_HAS_OHCI=y
811# CONFIG_USB is not set
812
813#
814# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
815#
816
817#
818# USB Gadget Support
819#
820# CONFIG_USB_GADGET is not set
821
822#
823# MMC/SD Card support
824#
825# CONFIG_MMC is not set
826
827#
828# InfiniBand support
829#
830# CONFIG_INFINIBAND is not set
831
832#
833# SN Devices
834#
835
836#
837# File systems
838#
839CONFIG_EXT2_FS=y
840# CONFIG_EXT2_FS_XATTR is not set
841# CONFIG_EXT2_FS_XIP is not set
842CONFIG_EXT3_FS=y
843CONFIG_EXT3_FS_XATTR=y
844# CONFIG_EXT3_FS_POSIX_ACL is not set
845# CONFIG_EXT3_FS_SECURITY is not set
846CONFIG_JBD=y
847# CONFIG_JBD_DEBUG is not set
848CONFIG_FS_MBCACHE=y
849# CONFIG_REISERFS_FS is not set
850# CONFIG_JFS_FS is not set
851# CONFIG_FS_POSIX_ACL is not set
852# CONFIG_XFS_FS is not set
853# CONFIG_MINIX_FS is not set
854# CONFIG_ROMFS_FS is not set
855CONFIG_INOTIFY=y
856# CONFIG_QUOTA is not set
857CONFIG_DNOTIFY=y
858# CONFIG_AUTOFS_FS is not set
859# CONFIG_AUTOFS4_FS is not set
860# CONFIG_FUSE_FS is not set
861
862#
863# CD-ROM/DVD Filesystems
864#
865# CONFIG_ISO9660_FS is not set
866# CONFIG_UDF_FS is not set
867
868#
869# DOS/FAT/NT Filesystems
870#
871# CONFIG_MSDOS_FS is not set
872# CONFIG_VFAT_FS is not set
873# CONFIG_NTFS_FS is not set
874
875#
876# Pseudo filesystems
877#
878CONFIG_PROC_FS=y
879CONFIG_PROC_KCORE=y
880CONFIG_SYSFS=y
881CONFIG_TMPFS=y
882# CONFIG_HUGETLB_PAGE is not set
883CONFIG_RAMFS=y
884# CONFIG_RELAYFS_FS is not set
885
886#
887# Miscellaneous filesystems
888#
889# CONFIG_ADFS_FS is not set
890# CONFIG_AFFS_FS is not set
891# CONFIG_HFS_FS is not set
892# CONFIG_HFSPLUS_FS is not set
893# CONFIG_BEFS_FS is not set
894# CONFIG_BFS_FS is not set
895# CONFIG_EFS_FS is not set
896# CONFIG_JFFS_FS is not set
897CONFIG_JFFS2_FS=y
898CONFIG_JFFS2_FS_DEBUG=0
899CONFIG_JFFS2_FS_WRITEBUFFER=y
900# CONFIG_JFFS2_SUMMARY is not set
901# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
902CONFIG_JFFS2_ZLIB=y
903CONFIG_JFFS2_RTIME=y
904# CONFIG_JFFS2_RUBIN is not set
905CONFIG_CRAMFS=y
906# CONFIG_VXFS_FS is not set
907# CONFIG_HPFS_FS is not set
908# CONFIG_QNX4FS_FS is not set
909# CONFIG_SYSV_FS is not set
910# CONFIG_UFS_FS is not set
911
912#
913# Network File Systems
914#
915CONFIG_NFS_FS=y
916# CONFIG_NFS_V3 is not set
917# CONFIG_NFS_V4 is not set
918# CONFIG_NFS_DIRECTIO is not set
919# CONFIG_NFSD is not set
920CONFIG_ROOT_NFS=y
921CONFIG_LOCKD=y
922CONFIG_NFS_COMMON=y
923CONFIG_SUNRPC=y
924# CONFIG_RPCSEC_GSS_KRB5 is not set
925# CONFIG_RPCSEC_GSS_SPKM3 is not set
926# CONFIG_SMB_FS is not set
927# CONFIG_CIFS is not set
928# CONFIG_NCP_FS is not set
929# CONFIG_CODA_FS is not set
930# CONFIG_AFS_FS is not set
931# CONFIG_9P_FS is not set
932
933#
934# Partition Types
935#
936CONFIG_PARTITION_ADVANCED=y
937# CONFIG_ACORN_PARTITION is not set
938# CONFIG_OSF_PARTITION is not set
939# CONFIG_AMIGA_PARTITION is not set
940# CONFIG_ATARI_PARTITION is not set
941# CONFIG_MAC_PARTITION is not set
942# CONFIG_MSDOS_PARTITION is not set
943# CONFIG_LDM_PARTITION is not set
944# CONFIG_SGI_PARTITION is not set
945# CONFIG_ULTRIX_PARTITION is not set
946# CONFIG_SUN_PARTITION is not set
947# CONFIG_EFI_PARTITION is not set
948
949#
950# Native Language Support
951#
952# CONFIG_NLS is not set
953# CONFIG_SCC_ENET is not set
954# CONFIG_FEC_ENET is not set
955
956#
957# CPM2 Options
958#
959
960#
961# Library routines
962#
963# CONFIG_CRC_CCITT is not set
964# CONFIG_CRC16 is not set
965CONFIG_CRC32=y
966# CONFIG_LIBCRC32C is not set
967CONFIG_ZLIB_INFLATE=y
968CONFIG_ZLIB_DEFLATE=y
969# CONFIG_PROFILING is not set
970
971#
972# Kernel hacking
973#
974# CONFIG_PRINTK_TIME is not set
975# CONFIG_DEBUG_KERNEL is not set
976CONFIG_LOG_BUF_SHIFT=14
977# CONFIG_KGDB_CONSOLE is not set
978
979#
980# Security options
981#
982# CONFIG_KEYS is not set
983# CONFIG_SECURITY is not set
984
985#
986# Cryptographic options
987#
988# CONFIG_CRYPTO is not set
989
990#
991# Hardware crypto devices
992#
diff --git a/arch/ppc/configs/bamboo_defconfig b/arch/ppc/configs/bamboo_defconfig
index 0ba4e70d50..41fd3938fa 100644
--- a/arch/ppc/configs/bamboo_defconfig
+++ b/arch/ppc/configs/bamboo_defconfig
@@ -499,6 +499,7 @@ CONFIG_NATSEMI=y
499# CONFIG_DL2K is not set 499# CONFIG_DL2K is not set
500CONFIG_E1000=y 500CONFIG_E1000=y
501# CONFIG_E1000_NAPI is not set 501# CONFIG_E1000_NAPI is not set
502# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
502# CONFIG_NS83820 is not set 503# CONFIG_NS83820 is not set
503# CONFIG_HAMACHI is not set 504# CONFIG_HAMACHI is not set
504# CONFIG_YELLOWFIN is not set 505# CONFIG_YELLOWFIN is not set
diff --git a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig
index 0f3bb9af9c..7311fe6b42 100644
--- a/arch/ppc/configs/katana_defconfig
+++ b/arch/ppc/configs/katana_defconfig
@@ -488,6 +488,7 @@ CONFIG_E100=y
488# CONFIG_DL2K is not set 488# CONFIG_DL2K is not set
489CONFIG_E1000=y 489CONFIG_E1000=y
490# CONFIG_E1000_NAPI is not set 490# CONFIG_E1000_NAPI is not set
491# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
491# CONFIG_NS83820 is not set 492# CONFIG_NS83820 is not set
492# CONFIG_HAMACHI is not set 493# CONFIG_HAMACHI is not set
493# CONFIG_YELLOWFIN is not set 494# CONFIG_YELLOWFIN is not set
diff --git a/arch/ppc/configs/mpc834x_sys_defconfig b/arch/ppc/configs/mpc834x_sys_defconfig
index 673dc64ebc..b96a6d6dad 100644
--- a/arch/ppc/configs/mpc834x_sys_defconfig
+++ b/arch/ppc/configs/mpc834x_sys_defconfig
@@ -402,6 +402,7 @@ CONFIG_E100=y
402# CONFIG_DL2K is not set 402# CONFIG_DL2K is not set
403CONFIG_E1000=y 403CONFIG_E1000=y
404# CONFIG_E1000_NAPI is not set 404# CONFIG_E1000_NAPI is not set
405# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
405# CONFIG_NS83820 is not set 406# CONFIG_NS83820 is not set
406# CONFIG_HAMACHI is not set 407# CONFIG_HAMACHI is not set
407# CONFIG_YELLOWFIN is not set 408# CONFIG_YELLOWFIN is not set
diff --git a/arch/ppc/configs/power3_defconfig b/arch/ppc/configs/power3_defconfig
index 93da595a47..a1ef929bca 100644
--- a/arch/ppc/configs/power3_defconfig
+++ b/arch/ppc/configs/power3_defconfig
@@ -442,6 +442,7 @@ CONFIG_E100=y
442# CONFIG_DL2K is not set 442# CONFIG_DL2K is not set
443CONFIG_E1000=y 443CONFIG_E1000=y
444# CONFIG_E1000_NAPI is not set 444# CONFIG_E1000_NAPI is not set
445# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
445# CONFIG_NS83820 is not set 446# CONFIG_NS83820 is not set
446# CONFIG_HAMACHI is not set 447# CONFIG_HAMACHI is not set
447# CONFIG_YELLOWFIN is not set 448# CONFIG_YELLOWFIN is not set
diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile
index 17a4da65e2..e399bbb969 100644
--- a/arch/ppc/kernel/Makefile
+++ b/arch/ppc/kernel/Makefile
@@ -9,16 +9,13 @@ extra-$(CONFIG_44x) := head_44x.o
9extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o 9extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
10extra-$(CONFIG_8xx) := head_8xx.o 10extra-$(CONFIG_8xx) := head_8xx.o
11extra-$(CONFIG_6xx) += idle_6xx.o 11extra-$(CONFIG_6xx) += idle_6xx.o
12extra-$(CONFIG_POWER4) += idle_power4.o
13extra-y += vmlinux.lds 12extra-y += vmlinux.lds
14 13
15obj-y := entry.o traps.o idle.o time.o misc.o \ 14obj-y := entry.o traps.o idle.o time.o misc.o \
16 process.o align.o \
17 setup.o \ 15 setup.o \
18 ppc_htab.o 16 ppc_htab.o
19obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o 17obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
20obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o 18obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o
21obj-$(CONFIG_POWER4) += cpu_setup_power4.o
22obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o 19obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o
23obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o 20obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o
24obj-$(CONFIG_PCI) += pci.o 21obj-$(CONFIG_PCI) += pci.o
@@ -38,16 +35,14 @@ endif
38# These are here while we do the architecture merge 35# These are here while we do the architecture merge
39 36
40else 37else
41obj-y := idle.o align.o 38obj-y := idle.o
42obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o 39obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
43obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o 40obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o
44obj-$(CONFIG_MODULES) += module.o 41obj-$(CONFIG_MODULES) += module.o
45obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o 42obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o
46obj-$(CONFIG_PCI) += pci.o
47obj-$(CONFIG_KGDB) += ppc-stub.o 43obj-$(CONFIG_KGDB) += ppc-stub.o
48obj-$(CONFIG_TAU) += temp.o 44obj-$(CONFIG_TAU) += temp.o
49ifndef CONFIG_E200 45ifndef CONFIG_E200
50obj-$(CONFIG_FSL_BOOKE) += perfmon_fsl_booke.o 46obj-$(CONFIG_FSL_BOOKE) += perfmon_fsl_booke.o
51endif 47endif
52obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
53endif 48endif
diff --git a/arch/ppc/kernel/align.c b/arch/ppc/kernel/align.c
deleted file mode 100644
index ab398c4b70..0000000000
--- a/arch/ppc/kernel/align.c
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * align.c - handle alignment exceptions for the Power PC.
3 *
4 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
5 * Copyright (c) 1998-1999 TiVo, Inc.
6 * PowerPC 403GCX modifications.
7 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
8 * PowerPC 403GCX/405GP modifications.
9 */
10#include <linux/config.h>
11#include <linux/kernel.h>
12#include <linux/mm.h>
13#include <asm/ptrace.h>
14#include <asm/processor.h>
15#include <asm/uaccess.h>
16#include <asm/system.h>
17#include <asm/cache.h>
18
19struct aligninfo {
20 unsigned char len;
21 unsigned char flags;
22};
23
24#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
25#define OPCD(inst) (((inst) & 0xFC000000) >> 26)
26#define RS(inst) (((inst) & 0x03E00000) >> 21)
27#define RA(inst) (((inst) & 0x001F0000) >> 16)
28#define IS_XFORM(code) ((code) == 31)
29#endif
30
31#define INVALID { 0, 0 }
32
33#define LD 1 /* load */
34#define ST 2 /* store */
35#define SE 4 /* sign-extend value */
36#define F 8 /* to/from fp regs */
37#define U 0x10 /* update index register */
38#define M 0x20 /* multiple load/store */
39#define S 0x40 /* single-precision fp, or byte-swap value */
40#define SX 0x40 /* byte count in XER */
41#define HARD 0x80 /* string, stwcx. */
42
43#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
44
45/*
46 * The PowerPC stores certain bits of the instruction that caused the
47 * alignment exception in the DSISR register. This array maps those
48 * bits to information about the operand length and what the
49 * instruction would do.
50 */
51static struct aligninfo aligninfo[128] = {
52 { 4, LD }, /* 00 0 0000: lwz / lwarx */
53 INVALID, /* 00 0 0001 */
54 { 4, ST }, /* 00 0 0010: stw */
55 INVALID, /* 00 0 0011 */
56 { 2, LD }, /* 00 0 0100: lhz */
57 { 2, LD+SE }, /* 00 0 0101: lha */
58 { 2, ST }, /* 00 0 0110: sth */
59 { 4, LD+M }, /* 00 0 0111: lmw */
60 { 4, LD+F+S }, /* 00 0 1000: lfs */
61 { 8, LD+F }, /* 00 0 1001: lfd */
62 { 4, ST+F+S }, /* 00 0 1010: stfs */
63 { 8, ST+F }, /* 00 0 1011: stfd */
64 INVALID, /* 00 0 1100 */
65 INVALID, /* 00 0 1101: ld/ldu/lwa */
66 INVALID, /* 00 0 1110 */
67 INVALID, /* 00 0 1111: std/stdu */
68 { 4, LD+U }, /* 00 1 0000: lwzu */
69 INVALID, /* 00 1 0001 */
70 { 4, ST+U }, /* 00 1 0010: stwu */
71 INVALID, /* 00 1 0011 */
72 { 2, LD+U }, /* 00 1 0100: lhzu */
73 { 2, LD+SE+U }, /* 00 1 0101: lhau */
74 { 2, ST+U }, /* 00 1 0110: sthu */
75 { 4, ST+M }, /* 00 1 0111: stmw */
76 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
77 { 8, LD+F+U }, /* 00 1 1001: lfdu */
78 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
79 { 8, ST+F+U }, /* 00 1 1011: stfdu */
80 INVALID, /* 00 1 1100 */
81 INVALID, /* 00 1 1101 */
82 INVALID, /* 00 1 1110 */
83 INVALID, /* 00 1 1111 */
84 INVALID, /* 01 0 0000: ldx */
85 INVALID, /* 01 0 0001 */
86 INVALID, /* 01 0 0010: stdx */
87 INVALID, /* 01 0 0011 */
88 INVALID, /* 01 0 0100 */
89 INVALID, /* 01 0 0101: lwax */
90 INVALID, /* 01 0 0110 */
91 INVALID, /* 01 0 0111 */
92 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
93 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
94 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
95 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
96 INVALID, /* 01 0 1100 */
97 INVALID, /* 01 0 1101 */
98 INVALID, /* 01 0 1110 */
99 INVALID, /* 01 0 1111 */
100 INVALID, /* 01 1 0000: ldux */
101 INVALID, /* 01 1 0001 */
102 INVALID, /* 01 1 0010: stdux */
103 INVALID, /* 01 1 0011 */
104 INVALID, /* 01 1 0100 */
105 INVALID, /* 01 1 0101: lwaux */
106 INVALID, /* 01 1 0110 */
107 INVALID, /* 01 1 0111 */
108 INVALID, /* 01 1 1000 */
109 INVALID, /* 01 1 1001 */
110 INVALID, /* 01 1 1010 */
111 INVALID, /* 01 1 1011 */
112 INVALID, /* 01 1 1100 */
113 INVALID, /* 01 1 1101 */
114 INVALID, /* 01 1 1110 */
115 INVALID, /* 01 1 1111 */
116 INVALID, /* 10 0 0000 */
117 INVALID, /* 10 0 0001 */
118 { 0, ST+HARD }, /* 10 0 0010: stwcx. */
119 INVALID, /* 10 0 0011 */
120 INVALID, /* 10 0 0100 */
121 INVALID, /* 10 0 0101 */
122 INVALID, /* 10 0 0110 */
123 INVALID, /* 10 0 0111 */
124 { 4, LD+S }, /* 10 0 1000: lwbrx */
125 INVALID, /* 10 0 1001 */
126 { 4, ST+S }, /* 10 0 1010: stwbrx */
127 INVALID, /* 10 0 1011 */
128 { 2, LD+S }, /* 10 0 1100: lhbrx */
129 INVALID, /* 10 0 1101 */
130 { 2, ST+S }, /* 10 0 1110: sthbrx */
131 INVALID, /* 10 0 1111 */
132 INVALID, /* 10 1 0000 */
133 INVALID, /* 10 1 0001 */
134 INVALID, /* 10 1 0010 */
135 INVALID, /* 10 1 0011 */
136 INVALID, /* 10 1 0100 */
137 INVALID, /* 10 1 0101 */
138 INVALID, /* 10 1 0110 */
139 INVALID, /* 10 1 0111 */
140 INVALID, /* 10 1 1000 */
141 INVALID, /* 10 1 1001 */
142 INVALID, /* 10 1 1010 */
143 INVALID, /* 10 1 1011 */
144 INVALID, /* 10 1 1100 */
145 INVALID, /* 10 1 1101 */
146 INVALID, /* 10 1 1110 */
147 { 0, ST+HARD }, /* 10 1 1111: dcbz */
148 { 4, LD }, /* 11 0 0000: lwzx */
149 INVALID, /* 11 0 0001 */
150 { 4, ST }, /* 11 0 0010: stwx */
151 INVALID, /* 11 0 0011 */
152 { 2, LD }, /* 11 0 0100: lhzx */
153 { 2, LD+SE }, /* 11 0 0101: lhax */
154 { 2, ST }, /* 11 0 0110: sthx */
155 INVALID, /* 11 0 0111 */
156 { 4, LD+F+S }, /* 11 0 1000: lfsx */
157 { 8, LD+F }, /* 11 0 1001: lfdx */
158 { 4, ST+F+S }, /* 11 0 1010: stfsx */
159 { 8, ST+F }, /* 11 0 1011: stfdx */
160 INVALID, /* 11 0 1100 */
161 INVALID, /* 11 0 1101: lmd */
162 INVALID, /* 11 0 1110 */
163 INVALID, /* 11 0 1111: stmd */
164 { 4, LD+U }, /* 11 1 0000: lwzux */
165 INVALID, /* 11 1 0001 */
166 { 4, ST+U }, /* 11 1 0010: stwux */
167 INVALID, /* 11 1 0011 */
168 { 2, LD+U }, /* 11 1 0100: lhzux */
169 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
170 { 2, ST+U }, /* 11 1 0110: sthux */
171 INVALID, /* 11 1 0111 */
172 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
173 { 8, LD+F+U }, /* 11 1 1001: lfdux */
174 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
175 { 8, ST+F+U }, /* 11 1 1011: stfdux */
176 INVALID, /* 11 1 1100 */
177 INVALID, /* 11 1 1101 */
178 INVALID, /* 11 1 1110 */
179 INVALID, /* 11 1 1111 */
180};
181
182#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
183
184int
185fix_alignment(struct pt_regs *regs)
186{
187 int instr, nb, flags;
188#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
189 int opcode, f1, f2, f3;
190#endif
191 int i, t;
192 int reg, areg;
193 int offset, nb0;
194 unsigned char __user *addr;
195 unsigned char *rptr;
196 union {
197 long l;
198 float f;
199 double d;
200 unsigned char v[8];
201 } data;
202
203 CHECK_FULL_REGS(regs);
204
205#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
206 /* The 4xx-family & Book-E processors have no DSISR register,
207 * so we emulate it.
208 * The POWER4 has a DSISR register but doesn't set it on
209 * an alignment fault. -- paulus
210 */
211
212 if (__get_user(instr, (unsigned int __user *) regs->nip))
213 return 0;
214 opcode = OPCD(instr);
215 reg = RS(instr);
216 areg = RA(instr);
217
218 if (!IS_XFORM(opcode)) {
219 f1 = 0;
220 f2 = (instr & 0x04000000) >> 26;
221 f3 = (instr & 0x78000000) >> 27;
222 } else {
223 f1 = (instr & 0x00000006) >> 1;
224 f2 = (instr & 0x00000040) >> 6;
225 f3 = (instr & 0x00000780) >> 7;
226 }
227
228 instr = ((f1 << 5) | (f2 << 4) | f3);
229#else
230 reg = (regs->dsisr >> 5) & 0x1f; /* source/dest register */
231 areg = regs->dsisr & 0x1f; /* register to update */
232 instr = (regs->dsisr >> 10) & 0x7f;
233#endif
234
235 nb = aligninfo[instr].len;
236 if (nb == 0) {
237 long __user *p;
238 int i;
239
240 if (instr != DCBZ)
241 return 0; /* too hard or invalid instruction */
242 /*
243 * The dcbz (data cache block zero) instruction
244 * gives an alignment fault if used on non-cacheable
245 * memory. We handle the fault mainly for the
246 * case when we are running with the cache disabled
247 * for debugging.
248 */
249 p = (long __user *) (regs->dar & -L1_CACHE_BYTES);
250 if (user_mode(regs)
251 && !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))
252 return -EFAULT;
253 for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
254 if (__put_user(0, p+i))
255 return -EFAULT;
256 return 1;
257 }
258
259 flags = aligninfo[instr].flags;
260 if ((flags & (LD|ST)) == 0)
261 return 0;
262
263 /* For the 4xx-family & Book-E processors, the 'dar' field of the
264 * pt_regs structure is overloaded and is really from the DEAR.
265 */
266
267 addr = (unsigned char __user *)regs->dar;
268
269 if (flags & M) {
270 /* lmw, stmw, lswi/x, stswi/x */
271 nb0 = 0;
272 if (flags & HARD) {
273 if (flags & SX) {
274 nb = regs->xer & 127;
275 if (nb == 0)
276 return 1;
277 } else {
278 if (__get_user(instr,
279 (unsigned int __user *)regs->nip))
280 return 0;
281 nb = (instr >> 11) & 0x1f;
282 if (nb == 0)
283 nb = 32;
284 }
285 if (nb + reg * 4 > 128) {
286 nb0 = nb + reg * 4 - 128;
287 nb = 128 - reg * 4;
288 }
289 } else {
290 /* lwm, stmw */
291 nb = (32 - reg) * 4;
292 }
293
294 if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
295 return -EFAULT; /* bad address */
296
297 rptr = (unsigned char *) &regs->gpr[reg];
298 if (flags & LD) {
299 for (i = 0; i < nb; ++i)
300 if (__get_user(rptr[i], addr+i))
301 return -EFAULT;
302 if (nb0 > 0) {
303 rptr = (unsigned char *) &regs->gpr[0];
304 addr += nb;
305 for (i = 0; i < nb0; ++i)
306 if (__get_user(rptr[i], addr+i))
307 return -EFAULT;
308 }
309 for (; (i & 3) != 0; ++i)
310 rptr[i] = 0;
311 } else {
312 for (i = 0; i < nb; ++i)
313 if (__put_user(rptr[i], addr+i))
314 return -EFAULT;
315 if (nb0 > 0) {
316 rptr = (unsigned char *) &regs->gpr[0];
317 addr += nb;
318 for (i = 0; i < nb0; ++i)
319 if (__put_user(rptr[i], addr+i))
320 return -EFAULT;
321 }
322 }
323 return 1;
324 }
325
326 offset = 0;
327 if (nb < 4) {
328 /* read/write the least significant bits */
329 data.l = 0;
330 offset = 4 - nb;
331 }
332
333 /* Verify the address of the operand */
334 if (user_mode(regs)) {
335 if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
336 return -EFAULT; /* bad address */
337 }
338
339 if (flags & F) {
340 preempt_disable();
341 if (regs->msr & MSR_FP)
342 giveup_fpu(current);
343 preempt_enable();
344 }
345
346 /* If we read the operand, copy it in, else get register values */
347 if (flags & LD) {
348 for (i = 0; i < nb; ++i)
349 if (__get_user(data.v[offset+i], addr+i))
350 return -EFAULT;
351 } else if (flags & F) {
352 data.d = current->thread.fpr[reg];
353 } else {
354 data.l = regs->gpr[reg];
355 }
356
357 switch (flags & ~U) {
358 case LD+SE: /* sign extend */
359 if (data.v[2] >= 0x80)
360 data.v[0] = data.v[1] = -1;
361 break;
362
363 case LD+S: /* byte-swap */
364 case ST+S:
365 if (nb == 2) {
366 SWAP(data.v[2], data.v[3]);
367 } else {
368 SWAP(data.v[0], data.v[3]);
369 SWAP(data.v[1], data.v[2]);
370 }
371 break;
372
373 /* Single-precision FP load and store require conversions... */
374 case LD+F+S:
375#ifdef CONFIG_PPC_FPU
376 preempt_disable();
377 enable_kernel_fp();
378 cvt_fd(&data.f, &data.d, &current->thread);
379 preempt_enable();
380#else
381 return 0;
382#endif
383 break;
384 case ST+F+S:
385#ifdef CONFIG_PPC_FPU
386 preempt_disable();
387 enable_kernel_fp();
388 cvt_df(&data.d, &data.f, &current->thread);
389 preempt_enable();
390#else
391 return 0;
392#endif
393 break;
394 }
395
396 if (flags & ST) {
397 for (i = 0; i < nb; ++i)
398 if (__put_user(data.v[offset+i], addr+i))
399 return -EFAULT;
400 } else if (flags & F) {
401 current->thread.fpr[reg] = data.d;
402 } else {
403 regs->gpr[reg] = data.l;
404 }
405
406 if (flags & U)
407 regs->gpr[areg] = regs->dar;
408
409 return 1;
410}
diff --git a/arch/ppc/kernel/asm-offsets.c b/arch/ppc/kernel/asm-offsets.c
index fe0e767fb9..7964bf660e 100644
--- a/arch/ppc/kernel/asm-offsets.c
+++ b/arch/ppc/kernel/asm-offsets.c
@@ -131,7 +131,7 @@ main(void)
131 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); 131 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
132 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); 132 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
133 133
134 DEFINE(TI_SC_NOERR, offsetof(struct thread_info, syscall_noerror)); 134 DEFINE(TI_SIGFRAME, offsetof(struct thread_info, nvgprs_frame));
135 DEFINE(TI_TASK, offsetof(struct thread_info, task)); 135 DEFINE(TI_TASK, offsetof(struct thread_info, task));
136 DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain)); 136 DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain));
137 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); 137 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index f044edbb45..a48b950722 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -200,8 +200,6 @@ _GLOBAL(DoSyscall)
200 bl do_show_syscall 200 bl do_show_syscall
201#endif /* SHOW_SYSCALLS */ 201#endif /* SHOW_SYSCALLS */
202 rlwinm r10,r1,0,0,18 /* current_thread_info() */ 202 rlwinm r10,r1,0,0,18 /* current_thread_info() */
203 li r11,0
204 stb r11,TI_SC_NOERR(r10)
205 lwz r11,TI_FLAGS(r10) 203 lwz r11,TI_FLAGS(r10)
206 andi. r11,r11,_TIF_SYSCALL_T_OR_A 204 andi. r11,r11,_TIF_SYSCALL_T_OR_A
207 bne- syscall_dotrace 205 bne- syscall_dotrace
@@ -222,25 +220,21 @@ ret_from_syscall:
222 bl do_show_syscall_exit 220 bl do_show_syscall_exit
223#endif 221#endif
224 mr r6,r3 222 mr r6,r3
225 li r11,-_LAST_ERRNO
226 cmplw 0,r3,r11
227 rlwinm r12,r1,0,0,18 /* current_thread_info() */ 223 rlwinm r12,r1,0,0,18 /* current_thread_info() */
228 blt+ 30f
229 lbz r11,TI_SC_NOERR(r12)
230 cmpwi r11,0
231 bne 30f
232 neg r3,r3
233 lwz r10,_CCR(r1) /* Set SO bit in CR */
234 oris r10,r10,0x1000
235 stw r10,_CCR(r1)
236
237 /* disable interrupts so current_thread_info()->flags can't change */ 224 /* disable interrupts so current_thread_info()->flags can't change */
23830: LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ 225 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
239 SYNC 226 SYNC
240 MTMSRD(r10) 227 MTMSRD(r10)
241 lwz r9,TI_FLAGS(r12) 228 lwz r9,TI_FLAGS(r12)
242 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SIGPENDING|_TIF_NEED_RESCHED) 229 li r8,-_LAST_ERRNO
230 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL)
243 bne- syscall_exit_work 231 bne- syscall_exit_work
232 cmplw 0,r3,r8
233 blt+ syscall_exit_cont
234 lwz r11,_CCR(r1) /* Load CR */
235 neg r3,r3
236 oris r11,r11,0x1000 /* Set SO bit in CR */
237 stw r11,_CCR(r1)
244syscall_exit_cont: 238syscall_exit_cont:
245#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 239#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
246 /* If the process has its own DBCR0 value, load it up. The single 240 /* If the process has its own DBCR0 value, load it up. The single
@@ -292,46 +286,113 @@ syscall_dotrace:
292 b syscall_dotrace_cont 286 b syscall_dotrace_cont
293 287
294syscall_exit_work: 288syscall_exit_work:
295 stw r6,RESULT(r1) /* Save result */ 289 andi. r0,r9,_TIF_RESTOREALL
290 bne- 2f
291 cmplw 0,r3,r8
292 blt+ 1f
293 andi. r0,r9,_TIF_NOERROR
294 bne- 1f
295 lwz r11,_CCR(r1) /* Load CR */
296 neg r3,r3
297 oris r11,r11,0x1000 /* Set SO bit in CR */
298 stw r11,_CCR(r1)
299
3001: stw r6,RESULT(r1) /* Save result */
296 stw r3,GPR3(r1) /* Update return value */ 301 stw r3,GPR3(r1) /* Update return value */
297 andi. r0,r9,_TIF_SYSCALL_T_OR_A 3022: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
298 beq 5f 303 beq 4f
299 ori r10,r10,MSR_EE 304
300 SYNC 305 /* Clear per-syscall TIF flags if any are set, but _leave_
301 MTMSRD(r10) /* re-enable interrupts */ 306 _TIF_SAVE_NVGPRS set in r9 since we haven't dealt with that
307 yet. */
308
309 li r11,_TIF_PERSYSCALL_MASK
310 addi r12,r12,TI_FLAGS
3113: lwarx r8,0,r12
312 andc r8,r8,r11
313#ifdef CONFIG_IBM405_ERR77
314 dcbt 0,r12
315#endif
316 stwcx. r8,0,r12
317 bne- 3b
318 subi r12,r12,TI_FLAGS
319
3204: /* Anything which requires enabling interrupts? */
321 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SAVE_NVGPRS)
322 beq 7f
323
324 /* Save NVGPRS if they're not saved already */
302 lwz r4,TRAP(r1) 325 lwz r4,TRAP(r1)
303 andi. r4,r4,1 326 andi. r4,r4,1
304 beq 4f 327 beq 5f
305 SAVE_NVGPRS(r1) 328 SAVE_NVGPRS(r1)
306 li r4,0xc00 329 li r4,0xc00
307 stw r4,TRAP(r1) 330 stw r4,TRAP(r1)
3084: 331
332 /* Re-enable interrupts */
3335: ori r10,r10,MSR_EE
334 SYNC
335 MTMSRD(r10)
336
337 andi. r0,r9,_TIF_SAVE_NVGPRS
338 bne save_user_nvgprs
339
340save_user_nvgprs_cont:
341 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
342 beq 7f
343
309 addi r3,r1,STACK_FRAME_OVERHEAD 344 addi r3,r1,STACK_FRAME_OVERHEAD
310 bl do_syscall_trace_leave 345 bl do_syscall_trace_leave
311 REST_NVGPRS(r1) 346 REST_NVGPRS(r1)
3122: 347
313 lwz r3,GPR3(r1) 3486: lwz r3,GPR3(r1)
314 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ 349 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
315 SYNC 350 SYNC
316 MTMSRD(r10) /* disable interrupts again */ 351 MTMSRD(r10) /* disable interrupts again */
317 rlwinm r12,r1,0,0,18 /* current_thread_info() */ 352 rlwinm r12,r1,0,0,18 /* current_thread_info() */
318 lwz r9,TI_FLAGS(r12) 353 lwz r9,TI_FLAGS(r12)
3195: 3547:
320 andi. r0,r9,_TIF_NEED_RESCHED 355 andi. r0,r9,_TIF_NEED_RESCHED
321 bne 1f 356 bne 8f
322 lwz r5,_MSR(r1) 357 lwz r5,_MSR(r1)
323 andi. r5,r5,MSR_PR 358 andi. r5,r5,MSR_PR
324 beq syscall_exit_cont 359 beq ret_from_except
325 andi. r0,r9,_TIF_SIGPENDING 360 andi. r0,r9,_TIF_SIGPENDING
326 beq syscall_exit_cont 361 beq ret_from_except
327 b do_user_signal 362 b do_user_signal
3281: 3638:
329 ori r10,r10,MSR_EE 364 ori r10,r10,MSR_EE
330 SYNC 365 SYNC
331 MTMSRD(r10) /* re-enable interrupts */ 366 MTMSRD(r10) /* re-enable interrupts */
332 bl schedule 367 bl schedule
333 b 2b 368 b 6b
369
370save_user_nvgprs:
371 lwz r8,TI_SIGFRAME(r12)
372
373.macro savewords start, end
374 1: stw \start,4*(\start)(r8)
375 .section __ex_table,"a"
376 .align 2
377 .long 1b,save_user_nvgprs_fault
378 .previous
379 .if \end - \start
380 savewords "(\start+1)",\end
381 .endif
382.endm
383 savewords 14,31
384 b save_user_nvgprs_cont
385
386
387save_user_nvgprs_fault:
388 li r3,11 /* SIGSEGV */
389 lwz r4,TI_TASK(r12)
390 bl force_sigsegv
334 391
392 rlwinm r12,r1,0,0,18 /* current_thread_info() */
393 lwz r9,TI_FLAGS(r12)
394 b save_user_nvgprs_cont
395
335#ifdef SHOW_SYSCALLS 396#ifdef SHOW_SYSCALLS
336do_show_syscall: 397do_show_syscall:
337#ifdef SHOW_SYSCALLS_TASK 398#ifdef SHOW_SYSCALLS_TASK
@@ -401,28 +462,10 @@ show_syscalls_task:
401#endif /* SHOW_SYSCALLS */ 462#endif /* SHOW_SYSCALLS */
402 463
403/* 464/*
404 * The sigsuspend and rt_sigsuspend system calls can call do_signal 465 * The fork/clone functions need to copy the full register set into
405 * and thus put the process into the stopped state where we might 466 * the child process. Therefore we need to save all the nonvolatile
406 * want to examine its user state with ptrace. Therefore we need 467 * registers (r13 - r31) before calling the C code.
407 * to save all the nonvolatile registers (r13 - r31) before calling
408 * the C code.
409 */ 468 */
410 .globl ppc_sigsuspend
411ppc_sigsuspend:
412 SAVE_NVGPRS(r1)
413 lwz r0,TRAP(r1)
414 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
415 stw r0,TRAP(r1) /* register set saved */
416 b sys_sigsuspend
417
418 .globl ppc_rt_sigsuspend
419ppc_rt_sigsuspend:
420 SAVE_NVGPRS(r1)
421 lwz r0,TRAP(r1)
422 rlwinm r0,r0,0,0,30
423 stw r0,TRAP(r1)
424 b sys_rt_sigsuspend
425
426 .globl ppc_fork 469 .globl ppc_fork
427ppc_fork: 470ppc_fork:
428 SAVE_NVGPRS(r1) 471 SAVE_NVGPRS(r1)
@@ -447,14 +490,6 @@ ppc_clone:
447 stw r0,TRAP(r1) /* register set saved */ 490 stw r0,TRAP(r1) /* register set saved */
448 b sys_clone 491 b sys_clone
449 492
450 .globl ppc_swapcontext
451ppc_swapcontext:
452 SAVE_NVGPRS(r1)
453 lwz r0,TRAP(r1)
454 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
455 stw r0,TRAP(r1) /* register set saved */
456 b sys_swapcontext
457
458/* 493/*
459 * Top-level page fault handling. 494 * Top-level page fault handling.
460 * This is in assembler because if do_page_fault tells us that 495 * This is in assembler because if do_page_fault tells us that
@@ -626,16 +661,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
626 .long ret_from_except 661 .long ret_from_except
627#endif 662#endif
628 663
629 .globl sigreturn_exit
630sigreturn_exit:
631 subi r1,r3,STACK_FRAME_OVERHEAD
632 rlwinm r12,r1,0,0,18 /* current_thread_info() */
633 lwz r9,TI_FLAGS(r12)
634 andi. r0,r9,_TIF_SYSCALL_T_OR_A
635 beq+ ret_from_except_full
636 bl do_syscall_trace_leave
637 /* fall through */
638
639 .globl ret_from_except_full 664 .globl ret_from_except_full
640ret_from_except_full: 665ret_from_except_full:
641 REST_NVGPRS(r1) 666 REST_NVGPRS(r1)
@@ -658,7 +683,7 @@ user_exc_return: /* r10 contains MSR_KERNEL here */
658 /* Check current_thread_info()->flags */ 683 /* Check current_thread_info()->flags */
659 rlwinm r9,r1,0,0,18 684 rlwinm r9,r1,0,0,18
660 lwz r9,TI_FLAGS(r9) 685 lwz r9,TI_FLAGS(r9)
661 andi. r0,r9,(_TIF_SIGPENDING|_TIF_NEED_RESCHED) 686 andi. r0,r9,(_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL)
662 bne do_work 687 bne do_work
663 688
664restore_user: 689restore_user:
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index de09787422..3e6ca7f584 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -375,6 +375,8 @@ DataStoreTLBMiss:
375 lis r11, swapper_pg_dir@h 375 lis r11, swapper_pg_dir@h
376 ori r11, r11, swapper_pg_dir@l 376 ori r11, r11, swapper_pg_dir@l
377 rlwimi r10, r11, 0, 2, 19 377 rlwimi r10, r11, 0, 2, 19
378 stw r12, 16(r0)
379 b LoadLargeDTLB
3783: 3803:
379 lwz r11, 0(r10) /* Get the level 1 entry */ 381 lwz r11, 0(r10) /* Get the level 1 entry */
380 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 382 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
@@ -430,6 +432,81 @@ DataStoreTLBMiss:
430InstructionTLBError: 432InstructionTLBError:
431 b InstructionAccess 433 b InstructionAccess
432 434
435LoadLargeDTLB:
436 li r12, 0
437 lwz r11, 0(r10) /* Get the level 1 entry */
438 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
439 beq 3f /* If zero, don't try to find a pte */
440
441 /* We have a pte table, so load fetch the pte from the table.
442 */
443 ori r11, r11, 1 /* Set valid bit in physical L2 page */
444 DO_8xx_CPU6(0x3b80, r3)
445 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
446 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
447 lwz r10, 0(r10) /* Get the pte */
448
449 /* Insert the Guarded flag into the TWC from the Linux PTE.
450 * It is bit 27 of both the Linux PTE and the TWC (at least
451 * I got that right :-). It will be better when we can put
452 * this into the Linux pgd/pmd and load it in the operation
453 * above.
454 */
455 rlwimi r11, r10, 0, 27, 27
456
457 rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */
458 mfspr r3, SPRN_MD_EPN
459 rlwinm r3, r3, 0, 0, 9 /* extract virtual address */
460 tophys(r3, r3)
461 cmpw r3, r12 /* only use 8M page if it is a direct
462 kernel mapping */
463 bne 1f
464 ori r11, r11, MD_PS8MEG
465 li r12, 1
466 b 2f
4671:
468 li r12, 0 /* can't use 8MB TLB, so zero r12. */
4692:
470 DO_8xx_CPU6(0x3b80, r3)
471 mtspr SPRN_MD_TWC, r11
472
473 /* The Linux PTE won't go exactly into the MMU TLB.
474 * Software indicator bits 21, 22 and 28 must be clear.
475 * Software indicator bits 24, 25, 26, and 27 must be
476 * set. All other Linux PTE bits control the behavior
477 * of the MMU.
478 */
4793: li r11, 0x00f0
480 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
481 cmpwi r12, 1
482 bne 4f
483 ori r10, r10, 0x8
484
485 mfspr r12, SPRN_MD_EPN
486 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
487 ori r3, r3, 0x0fff
488 and r12, r3, r12
489 DO_8xx_CPU6(0x3780, r3)
490 mtspr SPRN_MD_EPN, r12
491
492 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
493 ori r3, r3, 0x0fff
494 and r10, r3, r10
4954:
496 DO_8xx_CPU6(0x3d80, r3)
497 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
498
499 mfspr r10, SPRN_M_TW /* Restore registers */
500 lwz r11, 0(r0)
501 mtcr r11
502 lwz r11, 4(r0)
503
504 lwz r12, 16(r0)
505#ifdef CONFIG_8xx_CPU6
506 lwz r3, 8(r0)
507#endif
508 rfi
509
433/* This is the data TLB error on the MPC8xx. This could be due to 510/* This is the data TLB error on the MPC8xx. This could be due to
434 * many reasons, including a dirty update to a pte. We can catch that 511 * many reasons, including a dirty update to a pte. We can catch that
435 * one here, but anything else is an error. First, we track down the 512 * one here, but anything else is an error. First, we track down the
diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
index 5063c603fa..8d60fa99fc 100644
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -24,7 +24,7 @@
24 * Copyright 2002-2004 MontaVista Software, Inc. 24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 * Copyright 2004 Freescale Semiconductor, Inc 26 * Copyright 2004 Freescale Semiconductor, Inc
27 * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com> 27 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
28 * 28 *
29 * This program is free software; you can redistribute it and/or modify it 29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the 30 * under the terms of the GNU General Public License as published by the
diff --git a/arch/ppc/kernel/idle.c b/arch/ppc/kernel/idle.c
index 821a75e456..1be3ca5bae 100644
--- a/arch/ppc/kernel/idle.c
+++ b/arch/ppc/kernel/idle.c
@@ -37,7 +37,6 @@
37void default_idle(void) 37void default_idle(void)
38{ 38{
39 void (*powersave)(void); 39 void (*powersave)(void);
40 int cpu = smp_processor_id();
41 40
42 powersave = ppc_md.power_save; 41 powersave = ppc_md.power_save;
43 42
@@ -47,7 +46,8 @@ void default_idle(void)
47#ifdef CONFIG_SMP 46#ifdef CONFIG_SMP
48 else { 47 else {
49 set_thread_flag(TIF_POLLING_NRFLAG); 48 set_thread_flag(TIF_POLLING_NRFLAG);
50 while (!need_resched() && !cpu_is_offline(cpu)) 49 while (!need_resched() &&
50 !cpu_is_offline(smp_processor_id()))
51 barrier(); 51 barrier();
52 clear_thread_flag(TIF_POLLING_NRFLAG); 52 clear_thread_flag(TIF_POLLING_NRFLAG);
53 } 53 }
diff --git a/arch/ppc/kernel/machine_kexec.c b/arch/ppc/kernel/machine_kexec.c
index a882b0dbe8..84d65a8719 100644
--- a/arch/ppc/kernel/machine_kexec.c
+++ b/arch/ppc/kernel/machine_kexec.c
@@ -28,12 +28,6 @@ typedef NORET_TYPE void (*relocate_new_kernel_t)(
28const extern unsigned char relocate_new_kernel[]; 28const extern unsigned char relocate_new_kernel[];
29const extern unsigned int relocate_new_kernel_size; 29const extern unsigned int relocate_new_kernel_size;
30 30
31/*
32 * Provide a dummy crash_notes definition while crash dump arrives to ppc.
33 * This prevents breakage of crash_notes attribute in kernel/ksysfs.c.
34 */
35note_buf_t crash_notes[NR_CPUS];
36
37void machine_shutdown(void) 31void machine_shutdown(void)
38{ 32{
39 if (ppc_md.machine_shutdown) 33 if (ppc_md.machine_shutdown)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 5e61124581..c3427eed83 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -204,78 +204,6 @@ _GLOBAL(call_setup_cpu)
204 mtctr r5 204 mtctr r5
205 bctr 205 bctr
206 206
207#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
208
209/* This gets called by via-pmu.c to switch the PLL selection
210 * on 750fx CPU. This function should really be moved to some
211 * other place (as most of the cpufreq code in via-pmu
212 */
213_GLOBAL(low_choose_750fx_pll)
214 /* Clear MSR:EE */
215 mfmsr r7
216 rlwinm r0,r7,0,17,15
217 mtmsr r0
218
219 /* If switching to PLL1, disable HID0:BTIC */
220 cmplwi cr0,r3,0
221 beq 1f
222 mfspr r5,SPRN_HID0
223 rlwinm r5,r5,0,27,25
224 sync
225 mtspr SPRN_HID0,r5
226 isync
227 sync
228
2291:
230 /* Calc new HID1 value */
231 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
232 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
233 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
234 or r4,r4,r5
235 mtspr SPRN_HID1,r4
236
237 /* Store new HID1 image */
238 rlwinm r6,r1,0,0,18
239 lwz r6,TI_CPU(r6)
240 slwi r6,r6,2
241 addis r6,r6,nap_save_hid1@ha
242 stw r4,nap_save_hid1@l(r6)
243
244 /* If switching to PLL0, enable HID0:BTIC */
245 cmplwi cr0,r3,0
246 bne 1f
247 mfspr r5,SPRN_HID0
248 ori r5,r5,HID0_BTIC
249 sync
250 mtspr SPRN_HID0,r5
251 isync
252 sync
253
2541:
255 /* Return */
256 mtmsr r7
257 blr
258
259_GLOBAL(low_choose_7447a_dfs)
260 /* Clear MSR:EE */
261 mfmsr r7
262 rlwinm r0,r7,0,17,15
263 mtmsr r0
264
265 /* Calc new HID1 value */
266 mfspr r4,SPRN_HID1
267 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
268 sync
269 mtspr SPRN_HID1,r4
270 sync
271 isync
272
273 /* Return */
274 mtmsr r7
275 blr
276
277#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
278
279/* 207/*
280 * complement mask on the msr then "or" some values on. 208 * complement mask on the msr then "or" some values on.
281 * _nmask_and_or_msr(nmask, value_to_or) 209 * _nmask_and_or_msr(nmask, value_to_or)
@@ -1197,7 +1125,7 @@ _GLOBAL(sys_call_table)
1197 .long sys_ssetmask 1125 .long sys_ssetmask
1198 .long sys_setreuid /* 70 */ 1126 .long sys_setreuid /* 70 */
1199 .long sys_setregid 1127 .long sys_setregid
1200 .long ppc_sigsuspend 1128 .long sys_sigsuspend
1201 .long sys_sigpending 1129 .long sys_sigpending
1202 .long sys_sethostname 1130 .long sys_sethostname
1203 .long sys_setrlimit /* 75 */ 1131 .long sys_setrlimit /* 75 */
@@ -1303,7 +1231,7 @@ _GLOBAL(sys_call_table)
1303 .long sys_rt_sigpending /* 175 */ 1231 .long sys_rt_sigpending /* 175 */
1304 .long sys_rt_sigtimedwait 1232 .long sys_rt_sigtimedwait
1305 .long sys_rt_sigqueueinfo 1233 .long sys_rt_sigqueueinfo
1306 .long ppc_rt_sigsuspend 1234 .long sys_rt_sigsuspend
1307 .long sys_pread64 1235 .long sys_pread64
1308 .long sys_pwrite64 /* 180 */ 1236 .long sys_pwrite64 /* 180 */
1309 .long sys_chown 1237 .long sys_chown
@@ -1374,7 +1302,7 @@ _GLOBAL(sys_call_table)
1374 .long sys_clock_gettime 1302 .long sys_clock_gettime
1375 .long sys_clock_getres 1303 .long sys_clock_getres
1376 .long sys_clock_nanosleep 1304 .long sys_clock_nanosleep
1377 .long ppc_swapcontext 1305 .long sys_swapcontext
1378 .long sys_tgkill /* 250 */ 1306 .long sys_tgkill /* 250 */
1379 .long sys_utimes 1307 .long sys_utimes
1380 .long sys_statfs64 1308 .long sys_statfs64
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
index 48ed58f995..04d04c5bfd 100644
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Common pmac/prep/chrp pci routines. -- Cort 2 * Common prep/chrp pci routines. -- Cort
3 */ 3 */
4 4
5#include <linux/config.h> 5#include <linux/config.h>
@@ -45,14 +45,12 @@ static void update_bridge_base(struct pci_bus *bus, int i);
45static void pcibios_fixup_resources(struct pci_dev* dev); 45static void pcibios_fixup_resources(struct pci_dev* dev);
46static void fixup_broken_pcnet32(struct pci_dev* dev); 46static void fixup_broken_pcnet32(struct pci_dev* dev);
47static int reparent_resources(struct resource *parent, struct resource *res); 47static int reparent_resources(struct resource *parent, struct resource *res);
48static void fixup_rev1_53c810(struct pci_dev* dev);
49static void fixup_cpc710_pci64(struct pci_dev* dev); 48static void fixup_cpc710_pci64(struct pci_dev* dev);
50#ifdef CONFIG_PPC_OF 49#ifdef CONFIG_PPC_OF
51static u8* pci_to_OF_bus_map; 50static u8* pci_to_OF_bus_map;
52#endif 51#endif
53 52
54/* By default, we don't re-assign bus numbers. We do this only on 53/* By default, we don't re-assign bus numbers.
55 * some pmacs
56 */ 54 */
57int pci_assign_all_buses; 55int pci_assign_all_buses;
58 56
@@ -504,7 +502,7 @@ pcibios_allocate_resources(int pass)
504 u16 command; 502 u16 command;
505 struct resource *r; 503 struct resource *r;
506 504
507 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 505 for_each_pci_dev(dev) {
508 pci_read_config_word(dev, PCI_COMMAND, &command); 506 pci_read_config_word(dev, PCI_COMMAND, &command);
509 for (idx = 0; idx < 6; idx++) { 507 for (idx = 0; idx < 6; idx++) {
510 r = &dev->resource[idx]; 508 r = &dev->resource[idx];
@@ -541,7 +539,7 @@ pcibios_assign_resources(void)
541 int idx; 539 int idx;
542 struct resource *r; 540 struct resource *r;
543 541
544 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 542 for_each_pci_dev(dev) {
545 int class = dev->class >> 8; 543 int class = dev->class >> 8;
546 544
547 /* Don't touch classless devices and host bridges */ 545 /* Don't touch classless devices and host bridges */
@@ -781,17 +779,6 @@ pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
781 return NULL; 779 return NULL;
782 780
783 /* Fixup bus number according to what OF think it is. */ 781 /* Fixup bus number according to what OF think it is. */
784#ifdef CONFIG_PPC_PMAC
785 /* The G5 need a special case here. Basically, we don't remap all
786 * busses on it so we don't create the pci-OF-map. However, we do
787 * remap the AGP bus and so have to deal with it. A future better
788 * fix has to be done by making the remapping per-host and always
789 * filling the pci_to_OF map. --BenH
790 */
791 if (_machine == _MACH_Pmac && busnr >= 0xf0)
792 busnr -= 0xf0;
793 else
794#endif
795 if (pci_to_OF_bus_map) 782 if (pci_to_OF_bus_map)
796 busnr = pci_to_OF_bus_map[busnr]; 783 busnr = pci_to_OF_bus_map[busnr];
797 if (busnr == 0xff) 784 if (busnr == 0xff)
@@ -816,8 +803,7 @@ EXPORT_SYMBOL(pci_device_to_OF_node);
816 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 803 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
817 * config cycles. 804 * config cycles.
818 */ 805 */
819struct pci_controller* 806struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
820pci_find_hose_for_OF_device(struct device_node* node)
821{ 807{
822 if (!have_of) 808 if (!have_of)
823 return NULL; 809 return NULL;
@@ -869,14 +855,15 @@ pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
869 */ 855 */
870 if (!pci_to_OF_bus_map) 856 if (!pci_to_OF_bus_map)
871 return 0; 857 return 0;
872 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 858
873 if (pci_to_OF_bus_map[dev->bus->number] != *bus) 859 for_each_pci_dev(dev)
874 continue; 860 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
875 if (dev->devfn != *devfn) 861 dev->devfn == *devfn) {
876 continue; 862 *bus = dev->bus->number;
877 *bus = dev->bus->number; 863 pci_dev_put(dev);
878 return 0; 864 return 0;
879 } 865 }
866
880 return -ENODEV; 867 return -ENODEV;
881} 868}
882EXPORT_SYMBOL(pci_device_from_OF_node); 869EXPORT_SYMBOL(pci_device_from_OF_node);
@@ -943,7 +930,7 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose,
943 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) { 930 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
944 res = NULL; 931 res = NULL;
945 size = ranges[na+4]; 932 size = ranges[na+4];
946 switch (ranges[0] >> 24) { 933 switch ((ranges[0] >> 24) & 0x3) {
947 case 1: /* I/O space */ 934 case 1: /* I/O space */
948 if (ranges[2] != 0) 935 if (ranges[2] != 0)
949 break; 936 break;
@@ -957,6 +944,8 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose,
957 res = &hose->io_resource; 944 res = &hose->io_resource;
958 res->flags = IORESOURCE_IO; 945 res->flags = IORESOURCE_IO;
959 res->start = ranges[2]; 946 res->start = ranges[2];
947 DBG("PCI: IO 0x%lx -> 0x%lx\n",
948 res->start, res->start + size - 1);
960 break; 949 break;
961 case 2: /* memory space */ 950 case 2: /* memory space */
962 memno = 0; 951 memno = 0;
@@ -974,7 +963,11 @@ pci_process_bridge_OF_ranges(struct pci_controller *hose,
974 if (memno < 3) { 963 if (memno < 3) {
975 res = &hose->mem_resources[memno]; 964 res = &hose->mem_resources[memno];
976 res->flags = IORESOURCE_MEM; 965 res->flags = IORESOURCE_MEM;
966 if(ranges[0] & 0x40000000)
967 res->flags |= IORESOURCE_PREFETCH;
977 res->start = ranges[na+2]; 968 res->start = ranges[na+2];
969 DBG("PCI: MEM[%d] 0x%lx -> 0x%lx\n", memno,
970 res->start, res->start + size - 1);
978 } 971 }
979 break; 972 break;
980 } 973 }
@@ -1035,216 +1028,6 @@ void pcibios_add_platform_entries(struct pci_dev *pdev)
1035} 1028}
1036 1029
1037 1030
1038#ifdef CONFIG_PPC_PMAC
1039/*
1040 * This set of routines checks for PCI<->PCI bridges that have closed
1041 * IO resources and have child devices. It tries to re-open an IO
1042 * window on them.
1043 *
1044 * This is a _temporary_ fix to workaround a problem with Apple's OF
1045 * closing IO windows on P2P bridges when the OF drivers of cards
1046 * below this bridge don't claim any IO range (typically ATI or
1047 * Adaptec).
1048 *
1049 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1050 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1051 * ordering when creating the host bus resources, and maybe a few more
1052 * minor tweaks
1053 */
1054
1055/* Initialize bridges with base/limit values we have collected */
1056static void __init
1057do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1058{
1059 struct pci_dev *bridge = bus->self;
1060 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1061 u32 l;
1062 u16 w;
1063 struct resource res;
1064
1065 if (bus->resource[0] == NULL)
1066 return;
1067 res = *(bus->resource[0]);
1068
1069 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1070 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1071 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1072 DBG(" IO window: %08lx-%08lx\n", res.start, res.end);
1073
1074 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1075 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1076 l &= 0xffff000f;
1077 l |= (res.start >> 8) & 0x00f0;
1078 l |= res.end & 0xf000;
1079 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1080
1081 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1082 l = (res.start >> 16) | (res.end & 0xffff0000);
1083 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1084 }
1085
1086 pci_read_config_word(bridge, PCI_COMMAND, &w);
1087 w |= PCI_COMMAND_IO;
1088 pci_write_config_word(bridge, PCI_COMMAND, w);
1089
1090#if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1091 if (enable_vga) {
1092 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1093 w |= PCI_BRIDGE_CTL_VGA;
1094 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1095 }
1096#endif
1097}
1098
1099/* This function is pretty basic and actually quite broken for the
1100 * general case, it's enough for us right now though. It's supposed
1101 * to tell us if we need to open an IO range at all or not and what
1102 * size.
1103 */
1104static int __init
1105check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1106{
1107 struct pci_dev *dev;
1108 int i;
1109 int rc = 0;
1110
1111#define push_end(res, size) do { unsigned long __sz = (size) ; \
1112 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1113 } while (0)
1114
1115 list_for_each_entry(dev, &bus->devices, bus_list) {
1116 u16 class = dev->class >> 8;
1117
1118 if (class == PCI_CLASS_DISPLAY_VGA ||
1119 class == PCI_CLASS_NOT_DEFINED_VGA)
1120 *found_vga = 1;
1121 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1122 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1123 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1124 push_end(res, 0xfff);
1125
1126 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1127 struct resource *r;
1128 unsigned long r_size;
1129
1130 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1131 && i >= PCI_BRIDGE_RESOURCES)
1132 continue;
1133 r = &dev->resource[i];
1134 r_size = r->end - r->start;
1135 if (r_size < 0xfff)
1136 r_size = 0xfff;
1137 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1138 rc = 1;
1139 push_end(res, r_size);
1140 }
1141 }
1142 }
1143
1144 return rc;
1145}
1146
1147/* Here we scan all P2P bridges of a given level that have a closed
1148 * IO window. Note that the test for the presence of a VGA card should
1149 * be improved to take into account already configured P2P bridges,
1150 * currently, we don't see them and might end up configuring 2 bridges
1151 * with VGA pass through enabled
1152 */
1153static void __init
1154do_fixup_p2p_level(struct pci_bus *bus)
1155{
1156 struct pci_bus *b;
1157 int i, parent_io;
1158 int has_vga = 0;
1159
1160 for (parent_io=0; parent_io<4; parent_io++)
1161 if (bus->resource[parent_io]
1162 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1163 break;
1164 if (parent_io >= 4)
1165 return;
1166
1167 list_for_each_entry(b, &bus->children, node) {
1168 struct pci_dev *d = b->self;
1169 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1170 struct resource *res = b->resource[0];
1171 struct resource tmp_res;
1172 unsigned long max;
1173 int found_vga = 0;
1174
1175 memset(&tmp_res, 0, sizeof(tmp_res));
1176 tmp_res.start = bus->resource[parent_io]->start;
1177
1178 /* We don't let low addresses go through that closed P2P bridge, well,
1179 * that may not be necessary but I feel safer that way
1180 */
1181 if (tmp_res.start == 0)
1182 tmp_res.start = 0x1000;
1183
1184 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1185 res != bus->resource[parent_io] &&
1186 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1187 check_for_io_childs(b, &tmp_res, &found_vga)) {
1188 u8 io_base_lo;
1189
1190 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1191
1192 if (found_vga) {
1193 if (has_vga) {
1194 printk(KERN_WARNING "Skipping VGA, already active"
1195 " on bus segment\n");
1196 found_vga = 0;
1197 } else
1198 has_vga = 1;
1199 }
1200 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1201
1202 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1203 max = ((unsigned long) hose->io_base_virt
1204 - isa_io_base) + 0xffffffff;
1205 else
1206 max = ((unsigned long) hose->io_base_virt
1207 - isa_io_base) + 0xffff;
1208
1209 *res = tmp_res;
1210 res->flags = IORESOURCE_IO;
1211 res->name = b->name;
1212
1213 /* Find a resource in the parent where we can allocate */
1214 for (i = 0 ; i < 4; i++) {
1215 struct resource *r = bus->resource[i];
1216 if (!r)
1217 continue;
1218 if ((r->flags & IORESOURCE_IO) == 0)
1219 continue;
1220 DBG("Trying to allocate from %08lx, size %08lx from parent"
1221 " res %d: %08lx -> %08lx\n",
1222 res->start, res->end, i, r->start, r->end);
1223
1224 if (allocate_resource(r, res, res->end + 1, res->start, max,
1225 res->end + 1, NULL, NULL) < 0) {
1226 DBG("Failed !\n");
1227 continue;
1228 }
1229 do_update_p2p_io_resource(b, found_vga);
1230 break;
1231 }
1232 }
1233 do_fixup_p2p_level(b);
1234 }
1235}
1236
1237static void
1238pcibios_fixup_p2p_bridges(void)
1239{
1240 struct pci_bus *b;
1241
1242 list_for_each_entry(b, &pci_root_buses, node)
1243 do_fixup_p2p_level(b);
1244}
1245
1246#endif /* CONFIG_PPC_PMAC */
1247
1248static int __init 1031static int __init
1249pcibios_init(void) 1032pcibios_init(void)
1250{ 1033{
@@ -1285,9 +1068,6 @@ pcibios_init(void)
1285 pcibios_allocate_bus_resources(&pci_root_buses); 1068 pcibios_allocate_bus_resources(&pci_root_buses);
1286 pcibios_allocate_resources(0); 1069 pcibios_allocate_resources(0);
1287 pcibios_allocate_resources(1); 1070 pcibios_allocate_resources(1);
1288#ifdef CONFIG_PPC_PMAC
1289 pcibios_fixup_p2p_bridges();
1290#endif /* CONFIG_PPC_PMAC */
1291 pcibios_assign_resources(); 1071 pcibios_assign_resources();
1292 1072
1293 /* Call machine dependent post-init code */ 1073 /* Call machine dependent post-init code */
@@ -1717,17 +1497,6 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1717 struct pci_controller* hose; 1497 struct pci_controller* hose;
1718 long result = -EOPNOTSUPP; 1498 long result = -EOPNOTSUPP;
1719 1499
1720 /* Argh ! Please forgive me for that hack, but that's the
1721 * simplest way to get existing XFree to not lockup on some
1722 * G5 machines... So when something asks for bus 0 io base
1723 * (bus 0 is HT root), we return the AGP one instead.
1724 */
1725#ifdef CONFIG_PPC_PMAC
1726 if (_machine == _MACH_Pmac && machine_is_compatible("MacRISC4"))
1727 if (bus == 0)
1728 bus = 0xf0;
1729#endif /* CONFIG_PPC_PMAC */
1730
1731 hose = pci_bus_to_hose(bus); 1500 hose = pci_bus_to_hose(bus);
1732 if (!hose) 1501 if (!hose)
1733 return -ENODEV; 1502 return -ENODEV;
@@ -1807,6 +1576,23 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1807EXPORT_SYMBOL(pci_iomap); 1576EXPORT_SYMBOL(pci_iomap);
1808EXPORT_SYMBOL(pci_iounmap); 1577EXPORT_SYMBOL(pci_iounmap);
1809 1578
1579unsigned long pci_address_to_pio(phys_addr_t address)
1580{
1581 struct pci_controller* hose = hose_head;
1582
1583 for (; hose; hose = hose->next) {
1584 unsigned int size = hose->io_resource.end -
1585 hose->io_resource.start + 1;
1586 if (address >= hose->io_base_phys &&
1587 address < (hose->io_base_phys + size)) {
1588 unsigned long base =
1589 (unsigned long)hose->io_base_virt - _IO_BASE;
1590 return base + (address - hose->io_base_phys);
1591 }
1592 }
1593 return (unsigned int)-1;
1594}
1595EXPORT_SYMBOL(pci_address_to_pio);
1810 1596
1811/* 1597/*
1812 * Null PCI config access functions, for the case when we can't 1598 * Null PCI config access functions, for the case when we can't
diff --git a/arch/ppc/kernel/ppc_htab.c b/arch/ppc/kernel/ppc_htab.c
index ca81002599..2f5c765027 100644
--- a/arch/ppc/kernel/ppc_htab.c
+++ b/arch/ppc/kernel/ppc_htab.c
@@ -16,6 +16,7 @@
16#include <linux/proc_fs.h> 16#include <linux/proc_fs.h>
17#include <linux/stat.h> 17#include <linux/stat.h>
18#include <linux/sysctl.h> 18#include <linux/sysctl.h>
19#include <linux/capability.h>
19#include <linux/ctype.h> 20#include <linux/ctype.h>
20#include <linux/threads.h> 21#include <linux/threads.h>
21#include <linux/smp_lock.h> 22#include <linux/smp_lock.h>
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index 66073f7751..3a6e4bcb3c 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -34,7 +34,6 @@
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/pci-bridge.h> 35#include <asm/pci-bridge.h>
36#include <asm/irq.h> 36#include <asm/irq.h>
37#include <asm/pmac_feature.h>
38#include <asm/dma.h> 37#include <asm/dma.h>
39#include <asm/machdep.h> 38#include <asm/machdep.h>
40#include <asm/hw_irq.h> 39#include <asm/hw_irq.h>
@@ -58,7 +57,6 @@ extern void machine_check_exception(struct pt_regs *regs);
58extern void alignment_exception(struct pt_regs *regs); 57extern void alignment_exception(struct pt_regs *regs);
59extern void program_check_exception(struct pt_regs *regs); 58extern void program_check_exception(struct pt_regs *regs);
60extern void single_step_exception(struct pt_regs *regs); 59extern void single_step_exception(struct pt_regs *regs);
61extern int pmac_newworld;
62extern int sys_sigreturn(struct pt_regs *regs); 60extern int sys_sigreturn(struct pt_regs *regs);
63 61
64long long __ashrdi3(long long, int); 62long long __ashrdi3(long long, int);
@@ -82,10 +80,6 @@ EXPORT_SYMBOL(ppc_n_lost_interrupts);
82EXPORT_SYMBOL(ISA_DMA_THRESHOLD); 80EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
83EXPORT_SYMBOL(DMA_MODE_READ); 81EXPORT_SYMBOL(DMA_MODE_READ);
84EXPORT_SYMBOL(DMA_MODE_WRITE); 82EXPORT_SYMBOL(DMA_MODE_WRITE);
85#if defined(CONFIG_PPC_PREP)
86EXPORT_SYMBOL(_prep_type);
87EXPORT_SYMBOL(ucSystemType);
88#endif
89 83
90#if !defined(__INLINE_BITOPS) 84#if !defined(__INLINE_BITOPS)
91EXPORT_SYMBOL(set_bit); 85EXPORT_SYMBOL(set_bit);
@@ -184,7 +178,7 @@ EXPORT_SYMBOL(kernel_thread);
184 178
185EXPORT_SYMBOL(flush_instruction_cache); 179EXPORT_SYMBOL(flush_instruction_cache);
186EXPORT_SYMBOL(giveup_fpu); 180EXPORT_SYMBOL(giveup_fpu);
187EXPORT_SYMBOL(flush_icache_range); 181EXPORT_SYMBOL(__flush_icache_range);
188EXPORT_SYMBOL(flush_dcache_range); 182EXPORT_SYMBOL(flush_dcache_range);
189EXPORT_SYMBOL(flush_icache_user_range); 183EXPORT_SYMBOL(flush_icache_user_range);
190EXPORT_SYMBOL(flush_dcache_page); 184EXPORT_SYMBOL(flush_dcache_page);
@@ -217,10 +211,6 @@ EXPORT_SYMBOL(adb_try_handler_change);
217EXPORT_SYMBOL(cuda_request); 211EXPORT_SYMBOL(cuda_request);
218EXPORT_SYMBOL(cuda_poll); 212EXPORT_SYMBOL(cuda_poll);
219#endif /* CONFIG_ADB_CUDA */ 213#endif /* CONFIG_ADB_CUDA */
220#ifdef CONFIG_PPC_PMAC
221EXPORT_SYMBOL(sys_ctrler);
222EXPORT_SYMBOL(pmac_newworld);
223#endif
224#ifdef CONFIG_PPC_OF 214#ifdef CONFIG_PPC_OF
225EXPORT_SYMBOL(find_devices); 215EXPORT_SYMBOL(find_devices);
226EXPORT_SYMBOL(find_type_devices); 216EXPORT_SYMBOL(find_type_devices);
@@ -245,9 +235,6 @@ EXPORT_SYMBOL(of_node_put);
245#if defined(CONFIG_BOOTX_TEXT) 235#if defined(CONFIG_BOOTX_TEXT)
246EXPORT_SYMBOL(btext_update_display); 236EXPORT_SYMBOL(btext_update_display);
247#endif 237#endif
248#if defined(CONFIG_SCSI) && defined(CONFIG_PPC_PMAC)
249EXPORT_SYMBOL(note_scsi_host);
250#endif
251#ifdef CONFIG_VT 238#ifdef CONFIG_VT
252EXPORT_SYMBOL(kd_mksound); 239EXPORT_SYMBOL(kd_mksound);
253#endif 240#endif
@@ -274,7 +261,6 @@ EXPORT_SYMBOL(__delay);
274EXPORT_SYMBOL(timer_interrupt); 261EXPORT_SYMBOL(timer_interrupt);
275EXPORT_SYMBOL(irq_desc); 262EXPORT_SYMBOL(irq_desc);
276EXPORT_SYMBOL(tb_ticks_per_jiffy); 263EXPORT_SYMBOL(tb_ticks_per_jiffy);
277EXPORT_SYMBOL(get_wchan);
278EXPORT_SYMBOL(console_drivers); 264EXPORT_SYMBOL(console_drivers);
279#ifdef CONFIG_XMON 265#ifdef CONFIG_XMON
280EXPORT_SYMBOL(xmon); 266EXPORT_SYMBOL(xmon);
@@ -311,7 +297,6 @@ EXPORT_SYMBOL(__res);
311 297
312EXPORT_SYMBOL(next_mmu_context); 298EXPORT_SYMBOL(next_mmu_context);
313EXPORT_SYMBOL(set_context); 299EXPORT_SYMBOL(set_context);
314EXPORT_SYMBOL_GPL(__handle_mm_fault); /* For MOL */
315EXPORT_SYMBOL(disarm_decr); 300EXPORT_SYMBOL(disarm_decr);
316#ifdef CONFIG_PPC_STD_MMU 301#ifdef CONFIG_PPC_STD_MMU
317extern long mol_trampoline; 302extern long mol_trampoline;
diff --git a/arch/ppc/kernel/process.c b/arch/ppc/kernel/process.c
deleted file mode 100644
index cb1c7b92f8..0000000000
--- a/arch/ppc/kernel/process.c
+++ /dev/null
@@ -1,845 +0,0 @@
1/*
2 * arch/ppc/kernel/process.c
3 *
4 * Derived from "arch/i386/kernel/process.c"
5 * Copyright (C) 1995 Linus Torvalds
6 *
7 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
8 * Paul Mackerras (paulus@cs.anu.edu.au)
9 *
10 * PowerPC version
11 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 */
19
20#include <linux/config.h>
21#include <linux/errno.h>
22#include <linux/sched.h>
23#include <linux/kernel.h>
24#include <linux/mm.h>
25#include <linux/smp.h>
26#include <linux/smp_lock.h>
27#include <linux/stddef.h>
28#include <linux/unistd.h>
29#include <linux/ptrace.h>
30#include <linux/slab.h>
31#include <linux/user.h>
32#include <linux/elf.h>
33#include <linux/init.h>
34#include <linux/prctl.h>
35#include <linux/init_task.h>
36#include <linux/module.h>
37#include <linux/kallsyms.h>
38#include <linux/mqueue.h>
39#include <linux/hardirq.h>
40
41#include <asm/pgtable.h>
42#include <asm/uaccess.h>
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/processor.h>
46#include <asm/mmu.h>
47#include <asm/prom.h>
48
49extern unsigned long _get_SP(void);
50
51struct task_struct *last_task_used_math = NULL;
52struct task_struct *last_task_used_altivec = NULL;
53struct task_struct *last_task_used_spe = NULL;
54
55static struct fs_struct init_fs = INIT_FS;
56static struct files_struct init_files = INIT_FILES;
57static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
58static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
59struct mm_struct init_mm = INIT_MM(init_mm);
60EXPORT_SYMBOL(init_mm);
61
62/* this is 8kB-aligned so we can get to the thread_info struct
63 at the base of it from the stack pointer with 1 integer instruction. */
64union thread_union init_thread_union
65 __attribute__((__section__(".data.init_task"))) =
66{ INIT_THREAD_INFO(init_task) };
67
68/* initial task structure */
69struct task_struct init_task = INIT_TASK(init_task);
70EXPORT_SYMBOL(init_task);
71
72/* only used to get secondary processor up */
73struct task_struct *current_set[NR_CPUS] = {&init_task, };
74
75#undef SHOW_TASK_SWITCHES
76#undef CHECK_STACK
77
78#if defined(CHECK_STACK)
79unsigned long
80kernel_stack_top(struct task_struct *tsk)
81{
82 return ((unsigned long)tsk) + sizeof(union task_union);
83}
84
85unsigned long
86task_top(struct task_struct *tsk)
87{
88 return ((unsigned long)tsk) + sizeof(struct thread_info);
89}
90
91/* check to make sure the kernel stack is healthy */
92int check_stack(struct task_struct *tsk)
93{
94 unsigned long stack_top = kernel_stack_top(tsk);
95 unsigned long tsk_top = task_top(tsk);
96 int ret = 0;
97
98#if 0
99 /* check thread magic */
100 if ( tsk->thread.magic != THREAD_MAGIC )
101 {
102 ret |= 1;
103 printk("thread.magic bad: %08x\n", tsk->thread.magic);
104 }
105#endif
106
107 if ( !tsk )
108 printk("check_stack(): tsk bad tsk %p\n",tsk);
109
110 /* check if stored ksp is bad */
111 if ( (tsk->thread.ksp > stack_top) || (tsk->thread.ksp < tsk_top) )
112 {
113 printk("stack out of bounds: %s/%d\n"
114 " tsk_top %08lx ksp %08lx stack_top %08lx\n",
115 tsk->comm,tsk->pid,
116 tsk_top, tsk->thread.ksp, stack_top);
117 ret |= 2;
118 }
119
120 /* check if stack ptr RIGHT NOW is bad */
121 if ( (tsk == current) && ((_get_SP() > stack_top ) || (_get_SP() < tsk_top)) )
122 {
123 printk("current stack ptr out of bounds: %s/%d\n"
124 " tsk_top %08lx sp %08lx stack_top %08lx\n",
125 current->comm,current->pid,
126 tsk_top, _get_SP(), stack_top);
127 ret |= 4;
128 }
129
130#if 0
131 /* check amount of free stack */
132 for ( i = (unsigned long *)task_top(tsk) ; i < kernel_stack_top(tsk) ; i++ )
133 {
134 if ( !i )
135 printk("check_stack(): i = %p\n", i);
136 if ( *i != 0 )
137 {
138 /* only notify if it's less than 900 bytes */
139 if ( (i - (unsigned long *)task_top(tsk)) < 900 )
140 printk("%d bytes free on stack\n",
141 i - task_top(tsk));
142 break;
143 }
144 }
145#endif
146
147 if (ret)
148 {
149 panic("bad kernel stack");
150 }
151 return(ret);
152}
153#endif /* defined(CHECK_STACK) */
154
155/*
156 * Make sure the floating-point register state in the
157 * the thread_struct is up to date for task tsk.
158 */
159void flush_fp_to_thread(struct task_struct *tsk)
160{
161 if (tsk->thread.regs) {
162 /*
163 * We need to disable preemption here because if we didn't,
164 * another process could get scheduled after the regs->msr
165 * test but before we have finished saving the FP registers
166 * to the thread_struct. That process could take over the
167 * FPU, and then when we get scheduled again we would store
168 * bogus values for the remaining FP registers.
169 */
170 preempt_disable();
171 if (tsk->thread.regs->msr & MSR_FP) {
172#ifdef CONFIG_SMP
173 /*
174 * This should only ever be called for current or
175 * for a stopped child process. Since we save away
176 * the FP register state on context switch on SMP,
177 * there is something wrong if a stopped child appears
178 * to still have its FP state in the CPU registers.
179 */
180 BUG_ON(tsk != current);
181#endif
182 giveup_fpu(current);
183 }
184 preempt_enable();
185 }
186}
187
188void enable_kernel_fp(void)
189{
190 WARN_ON(preemptible());
191
192#ifdef CONFIG_SMP
193 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
194 giveup_fpu(current);
195 else
196 giveup_fpu(NULL); /* just enables FP for kernel */
197#else
198 giveup_fpu(last_task_used_math);
199#endif /* CONFIG_SMP */
200}
201EXPORT_SYMBOL(enable_kernel_fp);
202
203int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs)
204{
205 preempt_disable();
206 if (tsk->thread.regs && (tsk->thread.regs->msr & MSR_FP))
207 giveup_fpu(tsk);
208 preempt_enable();
209 memcpy(fpregs, &tsk->thread.fpr[0], sizeof(*fpregs));
210 return 1;
211}
212
213#ifdef CONFIG_ALTIVEC
214void enable_kernel_altivec(void)
215{
216 WARN_ON(preemptible());
217
218#ifdef CONFIG_SMP
219 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
220 giveup_altivec(current);
221 else
222 giveup_altivec(NULL); /* just enable AltiVec for kernel - force */
223#else
224 giveup_altivec(last_task_used_altivec);
225#endif /* __SMP __ */
226}
227EXPORT_SYMBOL(enable_kernel_altivec);
228
229/*
230 * Make sure the VMX/Altivec register state in the
231 * the thread_struct is up to date for task tsk.
232 */
233void flush_altivec_to_thread(struct task_struct *tsk)
234{
235 if (tsk->thread.regs) {
236 preempt_disable();
237 if (tsk->thread.regs->msr & MSR_VEC) {
238#ifdef CONFIG_SMP
239 BUG_ON(tsk != current);
240#endif
241 giveup_altivec(current);
242 }
243 preempt_enable();
244 }
245}
246
247int dump_altivec(struct pt_regs *regs, elf_vrregset_t *vrregs)
248{
249 if (regs->msr & MSR_VEC)
250 giveup_altivec(current);
251 memcpy(vrregs, &current->thread.vr[0], sizeof(*vrregs));
252 return 1;
253}
254#endif /* CONFIG_ALTIVEC */
255
256#ifdef CONFIG_SPE
257void
258enable_kernel_spe(void)
259{
260 WARN_ON(preemptible());
261
262#ifdef CONFIG_SMP
263 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
264 giveup_spe(current);
265 else
266 giveup_spe(NULL); /* just enable SPE for kernel - force */
267#else
268 giveup_spe(last_task_used_spe);
269#endif /* __SMP __ */
270}
271EXPORT_SYMBOL(enable_kernel_spe);
272
273void flush_spe_to_thread(struct task_struct *tsk)
274{
275 if (tsk->thread.regs) {
276 preempt_disable();
277 if (tsk->thread.regs->msr & MSR_SPE) {
278#ifdef CONFIG_SMP
279 BUG_ON(tsk != current);
280#endif
281 giveup_spe(current);
282 }
283 preempt_enable();
284 }
285}
286
287int dump_spe(struct pt_regs *regs, elf_vrregset_t *evrregs)
288{
289 if (regs->msr & MSR_SPE)
290 giveup_spe(current);
291 /* We copy u32 evr[32] + u64 acc + u32 spefscr -> 35 */
292 memcpy(evrregs, &current->thread.evr[0], sizeof(u32) * 35);
293 return 1;
294}
295#endif /* CONFIG_SPE */
296
297struct task_struct *__switch_to(struct task_struct *prev,
298 struct task_struct *new)
299{
300 struct thread_struct *new_thread, *old_thread;
301 unsigned long s;
302 struct task_struct *last;
303
304 local_irq_save(s);
305#ifdef CHECK_STACK
306 check_stack(prev);
307 check_stack(new);
308#endif
309
310#ifdef CONFIG_SMP
311 /* avoid complexity of lazy save/restore of fpu
312 * by just saving it every time we switch out if
313 * this task used the fpu during the last quantum.
314 *
315 * If it tries to use the fpu again, it'll trap and
316 * reload its fp regs. So we don't have to do a restore
317 * every switch, just a save.
318 * -- Cort
319 */
320 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
321 giveup_fpu(prev);
322#ifdef CONFIG_ALTIVEC
323 /*
324 * If the previous thread used altivec in the last quantum
325 * (thus changing altivec regs) then save them.
326 * We used to check the VRSAVE register but not all apps
327 * set it, so we don't rely on it now (and in fact we need
328 * to save & restore VSCR even if VRSAVE == 0). -- paulus
329 *
330 * On SMP we always save/restore altivec regs just to avoid the
331 * complexity of changing processors.
332 * -- Cort
333 */
334 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)))
335 giveup_altivec(prev);
336#endif /* CONFIG_ALTIVEC */
337#ifdef CONFIG_SPE
338 /*
339 * If the previous thread used spe in the last quantum
340 * (thus changing spe regs) then save them.
341 *
342 * On SMP we always save/restore spe regs just to avoid the
343 * complexity of changing processors.
344 */
345 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
346 giveup_spe(prev);
347#endif /* CONFIG_SPE */
348#endif /* CONFIG_SMP */
349
350#ifdef CONFIG_ALTIVEC
351 /* Avoid the trap. On smp this this never happens since
352 * we don't set last_task_used_altivec -- Cort
353 */
354 if (new->thread.regs && last_task_used_altivec == new)
355 new->thread.regs->msr |= MSR_VEC;
356#endif
357#ifdef CONFIG_SPE
358 /* Avoid the trap. On smp this this never happens since
359 * we don't set last_task_used_spe
360 */
361 if (new->thread.regs && last_task_used_spe == new)
362 new->thread.regs->msr |= MSR_SPE;
363#endif /* CONFIG_SPE */
364 new_thread = &new->thread;
365 old_thread = &current->thread;
366 last = _switch(old_thread, new_thread);
367 local_irq_restore(s);
368 return last;
369}
370
371void show_regs(struct pt_regs * regs)
372{
373 int i, trap;
374
375 printk("NIP: %08lX LR: %08lX SP: %08lX REGS: %p TRAP: %04lx %s\n",
376 regs->nip, regs->link, regs->gpr[1], regs, regs->trap,
377 print_tainted());
378 printk("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
379 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
380 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
381 regs->msr&MSR_IR ? 1 : 0,
382 regs->msr&MSR_DR ? 1 : 0);
383 trap = TRAP(regs);
384 if (trap == 0x300 || trap == 0x600)
385 printk("DAR: %08lX, DSISR: %08lX\n", regs->dar, regs->dsisr);
386 printk("TASK = %p[%d] '%s' THREAD: %p\n",
387 current, current->pid, current->comm, current->thread_info);
388 printk("Last syscall: %ld ", current->thread.last_syscall);
389
390#ifdef CONFIG_SMP
391 printk(" CPU: %d", smp_processor_id());
392#endif /* CONFIG_SMP */
393
394 for (i = 0; i < 32; i++) {
395 long r;
396 if ((i % 8) == 0)
397 printk("\n" KERN_INFO "GPR%02d: ", i);
398 if (__get_user(r, &regs->gpr[i]))
399 break;
400 printk("%08lX ", r);
401 if (i == 12 && !FULL_REGS(regs))
402 break;
403 }
404 printk("\n");
405#ifdef CONFIG_KALLSYMS
406 /*
407 * Lookup NIP late so we have the best change of getting the
408 * above info out without failing
409 */
410 printk("NIP [%08lx] ", regs->nip);
411 print_symbol("%s\n", regs->nip);
412 printk("LR [%08lx] ", regs->link);
413 print_symbol("%s\n", regs->link);
414#endif
415 show_stack(current, (unsigned long *) regs->gpr[1]);
416}
417
418void exit_thread(void)
419{
420 if (last_task_used_math == current)
421 last_task_used_math = NULL;
422 if (last_task_used_altivec == current)
423 last_task_used_altivec = NULL;
424#ifdef CONFIG_SPE
425 if (last_task_used_spe == current)
426 last_task_used_spe = NULL;
427#endif
428}
429
430void flush_thread(void)
431{
432 if (last_task_used_math == current)
433 last_task_used_math = NULL;
434 if (last_task_used_altivec == current)
435 last_task_used_altivec = NULL;
436#ifdef CONFIG_SPE
437 if (last_task_used_spe == current)
438 last_task_used_spe = NULL;
439#endif
440}
441
442void
443release_thread(struct task_struct *t)
444{
445}
446
447/*
448 * This gets called before we allocate a new thread and copy
449 * the current task into it.
450 */
451void prepare_to_copy(struct task_struct *tsk)
452{
453 struct pt_regs *regs = tsk->thread.regs;
454
455 if (regs == NULL)
456 return;
457 preempt_disable();
458 if (regs->msr & MSR_FP)
459 giveup_fpu(current);
460#ifdef CONFIG_ALTIVEC
461 if (regs->msr & MSR_VEC)
462 giveup_altivec(current);
463#endif /* CONFIG_ALTIVEC */
464#ifdef CONFIG_SPE
465 if (regs->msr & MSR_SPE)
466 giveup_spe(current);
467#endif /* CONFIG_SPE */
468 preempt_enable();
469}
470
471/*
472 * Copy a thread..
473 */
474int
475copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
476 unsigned long unused,
477 struct task_struct *p, struct pt_regs *regs)
478{
479 struct pt_regs *childregs, *kregs;
480 extern void ret_from_fork(void);
481 unsigned long sp = (unsigned long)p->thread_info + THREAD_SIZE;
482 unsigned long childframe;
483
484 CHECK_FULL_REGS(regs);
485 /* Copy registers */
486 sp -= sizeof(struct pt_regs);
487 childregs = (struct pt_regs *) sp;
488 *childregs = *regs;
489 if ((childregs->msr & MSR_PR) == 0) {
490 /* for kernel thread, set `current' and stackptr in new task */
491 childregs->gpr[1] = sp + sizeof(struct pt_regs);
492 childregs->gpr[2] = (unsigned long) p;
493 p->thread.regs = NULL; /* no user register state */
494 } else {
495 childregs->gpr[1] = usp;
496 p->thread.regs = childregs;
497 if (clone_flags & CLONE_SETTLS)
498 childregs->gpr[2] = childregs->gpr[6];
499 }
500 childregs->gpr[3] = 0; /* Result from fork() */
501 sp -= STACK_FRAME_OVERHEAD;
502 childframe = sp;
503
504 /*
505 * The way this works is that at some point in the future
506 * some task will call _switch to switch to the new task.
507 * That will pop off the stack frame created below and start
508 * the new task running at ret_from_fork. The new task will
509 * do some house keeping and then return from the fork or clone
510 * system call, using the stack frame created above.
511 */
512 sp -= sizeof(struct pt_regs);
513 kregs = (struct pt_regs *) sp;
514 sp -= STACK_FRAME_OVERHEAD;
515 p->thread.ksp = sp;
516 kregs->nip = (unsigned long)ret_from_fork;
517
518 p->thread.last_syscall = -1;
519
520 return 0;
521}
522
523/*
524 * Set up a thread for executing a new program
525 */
526void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp)
527{
528 set_fs(USER_DS);
529 memset(regs->gpr, 0, sizeof(regs->gpr));
530 regs->ctr = 0;
531 regs->link = 0;
532 regs->xer = 0;
533 regs->ccr = 0;
534 regs->mq = 0;
535 regs->nip = nip;
536 regs->gpr[1] = sp;
537 regs->msr = MSR_USER;
538 if (last_task_used_math == current)
539 last_task_used_math = NULL;
540 if (last_task_used_altivec == current)
541 last_task_used_altivec = NULL;
542#ifdef CONFIG_SPE
543 if (last_task_used_spe == current)
544 last_task_used_spe = NULL;
545#endif
546 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
547 current->thread.fpscr.val = 0;
548#ifdef CONFIG_ALTIVEC
549 memset(current->thread.vr, 0, sizeof(current->thread.vr));
550 memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
551 current->thread.vrsave = 0;
552 current->thread.used_vr = 0;
553#endif /* CONFIG_ALTIVEC */
554#ifdef CONFIG_SPE
555 memset(current->thread.evr, 0, sizeof(current->thread.evr));
556 current->thread.acc = 0;
557 current->thread.spefscr = 0;
558 current->thread.used_spe = 0;
559#endif /* CONFIG_SPE */
560}
561
562#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
563 | PR_FP_EXC_RES | PR_FP_EXC_INV)
564
565int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
566{
567 struct pt_regs *regs = tsk->thread.regs;
568
569 /* This is a bit hairy. If we are an SPE enabled processor
570 * (have embedded fp) we store the IEEE exception enable flags in
571 * fpexc_mode. fpexc_mode is also used for setting FP exception
572 * mode (asyn, precise, disabled) for 'Classic' FP. */
573 if (val & PR_FP_EXC_SW_ENABLE) {
574#ifdef CONFIG_SPE
575 tsk->thread.fpexc_mode = val &
576 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
577#else
578 return -EINVAL;
579#endif
580 } else {
581 /* on a CONFIG_SPE this does not hurt us. The bits that
582 * __pack_fe01 use do not overlap with bits used for
583 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
584 * on CONFIG_SPE implementations are reserved so writing to
585 * them does not change anything */
586 if (val > PR_FP_EXC_PRECISE)
587 return -EINVAL;
588 tsk->thread.fpexc_mode = __pack_fe01(val);
589 if (regs != NULL && (regs->msr & MSR_FP) != 0)
590 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
591 | tsk->thread.fpexc_mode;
592 }
593 return 0;
594}
595
596int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
597{
598 unsigned int val;
599
600 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
601#ifdef CONFIG_SPE
602 val = tsk->thread.fpexc_mode;
603#else
604 return -EINVAL;
605#endif
606 else
607 val = __unpack_fe01(tsk->thread.fpexc_mode);
608 return put_user(val, (unsigned int __user *) adr);
609}
610
611int sys_clone(unsigned long clone_flags, unsigned long usp,
612 int __user *parent_tidp, void __user *child_threadptr,
613 int __user *child_tidp, int p6,
614 struct pt_regs *regs)
615{
616 CHECK_FULL_REGS(regs);
617 if (usp == 0)
618 usp = regs->gpr[1]; /* stack pointer for child */
619 return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp);
620}
621
622int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
623 unsigned long p4, unsigned long p5, unsigned long p6,
624 struct pt_regs *regs)
625{
626 CHECK_FULL_REGS(regs);
627 return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL);
628}
629
630int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
631 unsigned long p4, unsigned long p5, unsigned long p6,
632 struct pt_regs *regs)
633{
634 CHECK_FULL_REGS(regs);
635 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1],
636 regs, 0, NULL, NULL);
637}
638
639int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
640 unsigned long a3, unsigned long a4, unsigned long a5,
641 struct pt_regs *regs)
642{
643 int error;
644 char * filename;
645
646 filename = getname((char __user *) a0);
647 error = PTR_ERR(filename);
648 if (IS_ERR(filename))
649 goto out;
650 preempt_disable();
651 if (regs->msr & MSR_FP)
652 giveup_fpu(current);
653#ifdef CONFIG_ALTIVEC
654 if (regs->msr & MSR_VEC)
655 giveup_altivec(current);
656#endif /* CONFIG_ALTIVEC */
657#ifdef CONFIG_SPE
658 if (regs->msr & MSR_SPE)
659 giveup_spe(current);
660#endif /* CONFIG_SPE */
661 preempt_enable();
662 error = do_execve(filename, (char __user *__user *) a1,
663 (char __user *__user *) a2, regs);
664 if (error == 0) {
665 task_lock(current);
666 current->ptrace &= ~PT_DTRACE;
667 task_unlock(current);
668 }
669 putname(filename);
670out:
671 return error;
672}
673
674void dump_stack(void)
675{
676 show_stack(current, NULL);
677}
678
679EXPORT_SYMBOL(dump_stack);
680
681void show_stack(struct task_struct *tsk, unsigned long *stack)
682{
683 unsigned long sp, stack_top, prev_sp, ret;
684 int count = 0;
685 unsigned long next_exc = 0;
686 struct pt_regs *regs;
687 extern char ret_from_except, ret_from_except_full, ret_from_syscall;
688
689 sp = (unsigned long) stack;
690 if (tsk == NULL)
691 tsk = current;
692 if (sp == 0) {
693 if (tsk == current)
694 asm("mr %0,1" : "=r" (sp));
695 else
696 sp = tsk->thread.ksp;
697 }
698
699 prev_sp = (unsigned long) (tsk->thread_info + 1);
700 stack_top = (unsigned long) tsk->thread_info + THREAD_SIZE;
701 while (count < 16 && sp > prev_sp && sp < stack_top && (sp & 3) == 0) {
702 if (count == 0) {
703 printk("Call trace:");
704#ifdef CONFIG_KALLSYMS
705 printk("\n");
706#endif
707 } else {
708 if (next_exc) {
709 ret = next_exc;
710 next_exc = 0;
711 } else
712 ret = *(unsigned long *)(sp + 4);
713 printk(" [%08lx] ", ret);
714#ifdef CONFIG_KALLSYMS
715 print_symbol("%s", ret);
716 printk("\n");
717#endif
718 if (ret == (unsigned long) &ret_from_except
719 || ret == (unsigned long) &ret_from_except_full
720 || ret == (unsigned long) &ret_from_syscall) {
721 /* sp + 16 points to an exception frame */
722 regs = (struct pt_regs *) (sp + 16);
723 if (sp + 16 + sizeof(*regs) <= stack_top)
724 next_exc = regs->nip;
725 }
726 }
727 ++count;
728 sp = *(unsigned long *)sp;
729 }
730#ifndef CONFIG_KALLSYMS
731 if (count > 0)
732 printk("\n");
733#endif
734}
735
736#if 0
737/*
738 * Low level print for debugging - Cort
739 */
740int __init ll_printk(const char *fmt, ...)
741{
742 va_list args;
743 char buf[256];
744 int i;
745
746 va_start(args, fmt);
747 i=vsprintf(buf,fmt,args);
748 ll_puts(buf);
749 va_end(args);
750 return i;
751}
752
753int lines = 24, cols = 80;
754int orig_x = 0, orig_y = 0;
755
756void puthex(unsigned long val)
757{
758 unsigned char buf[10];
759 int i;
760 for (i = 7; i >= 0; i--)
761 {
762 buf[i] = "0123456789ABCDEF"[val & 0x0F];
763 val >>= 4;
764 }
765 buf[8] = '\0';
766 prom_print(buf);
767}
768
769void __init ll_puts(const char *s)
770{
771 int x,y;
772 char *vidmem = (char *)/*(_ISA_MEM_BASE + 0xB8000) */0xD00B8000;
773 char c;
774 extern int mem_init_done;
775
776 if ( mem_init_done ) /* assume this means we can printk */
777 {
778 printk(s);
779 return;
780 }
781
782#if 0
783 if ( have_of )
784 {
785 prom_print(s);
786 return;
787 }
788#endif
789
790 /*
791 * can't ll_puts on chrp without openfirmware yet.
792 * vidmem just needs to be setup for it.
793 * -- Cort
794 */
795 if ( _machine != _MACH_prep )
796 return;
797 x = orig_x;
798 y = orig_y;
799
800 while ( ( c = *s++ ) != '\0' ) {
801 if ( c == '\n' ) {
802 x = 0;
803 if ( ++y >= lines ) {
804 /*scroll();*/
805 /*y--;*/
806 y = 0;
807 }
808 } else {
809 vidmem [ ( x + cols * y ) * 2 ] = c;
810 if ( ++x >= cols ) {
811 x = 0;
812 if ( ++y >= lines ) {
813 /*scroll();*/
814 /*y--;*/
815 y = 0;
816 }
817 }
818 }
819 }
820
821 orig_x = x;
822 orig_y = y;
823}
824#endif
825
826unsigned long get_wchan(struct task_struct *p)
827{
828 unsigned long ip, sp;
829 unsigned long stack_page = (unsigned long) p->thread_info;
830 int count = 0;
831 if (!p || p == current || p->state == TASK_RUNNING)
832 return 0;
833 sp = p->thread.ksp;
834 do {
835 sp = *(unsigned long *)sp;
836 if (sp < stack_page || sp >= stack_page + 8188)
837 return 0;
838 if (count > 0) {
839 ip = *(unsigned long *)(sp + 4);
840 if (!in_sched_functions(ip))
841 return ip;
842 }
843 } while (count++ < 16);
844 return 0;
845}
diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c
index dc55e1abc4..c08ab432e9 100644
--- a/arch/ppc/kernel/setup.c
+++ b/arch/ppc/kernel/setup.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Common prep/pmac/chrp boot and setup code. 2 * Common prep/chrp boot and setup code.
3 */ 3 */
4 4
5#include <linux/config.h> 5#include <linux/config.h>
@@ -35,7 +35,6 @@
35#include <asm/machdep.h> 35#include <asm/machdep.h>
36#include <asm/uaccess.h> 36#include <asm/uaccess.h>
37#include <asm/system.h> 37#include <asm/system.h>
38#include <asm/pmac_feature.h>
39#include <asm/sections.h> 38#include <asm/sections.h>
40#include <asm/nvram.h> 39#include <asm/nvram.h>
41#include <asm/xmon.h> 40#include <asm/xmon.h>
@@ -55,7 +54,6 @@
55 54
56extern void platform_init(unsigned long r3, unsigned long r4, 55extern void platform_init(unsigned long r3, unsigned long r4,
57 unsigned long r5, unsigned long r6, unsigned long r7); 56 unsigned long r5, unsigned long r6, unsigned long r7);
58extern void bootx_init(unsigned long r4, unsigned long phys);
59extern void identify_cpu(unsigned long offset, unsigned long cpu); 57extern void identify_cpu(unsigned long offset, unsigned long cpu);
60extern void do_cpu_ftr_fixups(unsigned long offset); 58extern void do_cpu_ftr_fixups(unsigned long offset);
61extern void reloc_got2(unsigned long offset); 59extern void reloc_got2(unsigned long offset);
@@ -80,8 +78,6 @@ EXPORT_SYMBOL(_machine);
80 78
81extern void prep_init(unsigned long r3, unsigned long r4, 79extern void prep_init(unsigned long r3, unsigned long r4,
82 unsigned long r5, unsigned long r6, unsigned long r7); 80 unsigned long r5, unsigned long r6, unsigned long r7);
83extern void pmac_init(unsigned long r3, unsigned long r4,
84 unsigned long r5, unsigned long r6, unsigned long r7);
85extern void chrp_init(unsigned long r3, unsigned long r4, 81extern void chrp_init(unsigned long r3, unsigned long r4,
86 unsigned long r5, unsigned long r6, unsigned long r7); 82 unsigned long r5, unsigned long r6, unsigned long r7);
87 83
@@ -324,20 +320,15 @@ early_init(int r3, int r4, int r5)
324 identify_cpu(offset, 0); 320 identify_cpu(offset, 0);
325 do_cpu_ftr_fixups(offset); 321 do_cpu_ftr_fixups(offset);
326 322
327#if defined(CONFIG_PPC_MULTIPLATFORM) 323#if defined(CONFIG_PPC_OF)
328 reloc_got2(offset); 324 reloc_got2(offset);
329 325
330 /* If we came here from BootX, clear the screen,
331 * set up some pointers and return. */
332 if ((r3 == 0x426f6f58) && (r5 == 0))
333 bootx_init(r4, phys);
334
335 /* 326 /*
336 * don't do anything on prep 327 * don't do anything on prep
337 * for now, don't use bootinfo because it breaks yaboot 0.5 328 * for now, don't use bootinfo because it breaks yaboot 0.5
338 * and assume that if we didn't find a magic number, we have OF 329 * and assume that if we didn't find a magic number, we have OF
339 */ 330 */
340 else if (*(unsigned long *)(0) != 0xdeadc0de) 331 if (*(unsigned long *)(0) != 0xdeadc0de)
341 phys = prom_init(r3, r4, (prom_entry)r5); 332 phys = prom_init(r3, r4, (prom_entry)r5);
342 333
343 reloc_got2(-offset); 334 reloc_got2(-offset);
@@ -424,6 +415,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
424 } 415 }
425#endif 416#endif
426 417
418#ifdef CONFIG_PPC_OF
427 have_of = 1; 419 have_of = 1;
428 420
429 /* prom_init has already been called from __start */ 421 /* prom_init has already been called from __start */
@@ -495,19 +487,17 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
495#endif /* CONFIG_ADB */ 487#endif /* CONFIG_ADB */
496 488
497 switch (_machine) { 489 switch (_machine) {
498#ifdef CONFIG_PPC_PMAC
499 case _MACH_Pmac:
500 pmac_init(r3, r4, r5, r6, r7);
501 break;
502#endif
503#ifdef CONFIG_PPC_CHRP 490#ifdef CONFIG_PPC_CHRP
504 case _MACH_chrp: 491 case _MACH_chrp:
505 chrp_init(r3, r4, r5, r6, r7); 492 chrp_init(r3, r4, r5, r6, r7);
506 break; 493 break;
507#endif 494#endif
508 } 495 }
496#endif /* CONFIG_PPC_OF */
509} 497}
498#endif /* CONFIG_PPC_MULTIPLATFORM */
510 499
500#ifdef CONFIG_PPC_OF
511#ifdef CONFIG_SERIAL_CORE_CONSOLE 501#ifdef CONFIG_SERIAL_CORE_CONSOLE
512extern char *of_stdout_device; 502extern char *of_stdout_device;
513 503
@@ -564,7 +554,7 @@ static int __init set_preferred_console(void)
564} 554}
565console_initcall(set_preferred_console); 555console_initcall(set_preferred_console);
566#endif /* CONFIG_SERIAL_CORE_CONSOLE */ 556#endif /* CONFIG_SERIAL_CORE_CONSOLE */
567#endif /* CONFIG_PPC_MULTIPLATFORM */ 557#endif /* CONFIG_PPC_OF */
568 558
569struct bi_record *find_bootinfo(void) 559struct bi_record *find_bootinfo(void)
570{ 560{
@@ -602,7 +592,19 @@ void parse_bootinfo(struct bi_record *rec)
602#endif /* CONFIG_BLK_DEV_INITRD */ 592#endif /* CONFIG_BLK_DEV_INITRD */
603#ifdef CONFIG_PPC_MULTIPLATFORM 593#ifdef CONFIG_PPC_MULTIPLATFORM
604 case BI_MACHTYPE: 594 case BI_MACHTYPE:
605 _machine = data[0]; 595 /* Machine types changed with the merge. Since the
596 * bootinfo are now deprecated, we can just hard code
597 * the appropriate conversion here for when we are
598 * called with yaboot which passes us a machine type
599 * this way.
600 */
601 switch(data[0]) {
602 case 1: _machine = _MACH_prep; break;
603 case 2: _machine = _MACH_Pmac; break;
604 case 4: _machine = _MACH_chrp; break;
605 default:
606 _machine = data[0];
607 }
606 break; 608 break;
607#endif 609#endif
608 case BI_MEMSIZE: 610 case BI_MEMSIZE:
@@ -732,13 +734,8 @@ void __init setup_arch(char **cmdline_p)
732 /* so udelay does something sensible, assume <= 1000 bogomips */ 734 /* so udelay does something sensible, assume <= 1000 bogomips */
733 loops_per_jiffy = 500000000 / HZ; 735 loops_per_jiffy = 500000000 / HZ;
734 736
735#ifdef CONFIG_PPC_MULTIPLATFORM 737 if (ppc_md.init_early)
736 /* This could be called "early setup arch", it must be done 738 ppc_md.init_early();
737 * now because xmon need it
738 */
739 if (_machine == _MACH_Pmac)
740 pmac_feature_init(); /* New cool way */
741#endif
742 739
743#ifdef CONFIG_XMON 740#ifdef CONFIG_XMON
744 xmon_init(1); 741 xmon_init(1);
diff --git a/arch/ppc/kernel/smp.c b/arch/ppc/kernel/smp.c
index 43b8fc2ca5..e55cdda614 100644
--- a/arch/ppc/kernel/smp.c
+++ b/arch/ppc/kernel/smp.c
@@ -301,6 +301,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
301 301
302 /* Probe platform for CPUs: always linear. */ 302 /* Probe platform for CPUs: always linear. */
303 num_cpus = smp_ops->probe(); 303 num_cpus = smp_ops->probe();
304
305 if (num_cpus < 2)
306 smp_tb_synchronized = 1;
307
304 for (i = 0; i < num_cpus; ++i) 308 for (i = 0; i < num_cpus; ++i)
305 cpu_set(i, cpu_possible_map); 309 cpu_set(i, cpu_possible_map);
306 310
@@ -314,7 +318,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
314 p = fork_idle(cpu); 318 p = fork_idle(cpu);
315 if (IS_ERR(p)) 319 if (IS_ERR(p))
316 panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); 320 panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p));
317 p->thread_info->cpu = cpu; 321 task_thread_info(p)->cpu = cpu;
318 idle_tasks[cpu] = p; 322 idle_tasks[cpu] = p;
319 } 323 }
320} 324}
@@ -365,7 +369,7 @@ int __cpu_up(unsigned int cpu)
365 char buf[32]; 369 char buf[32];
366 int c; 370 int c;
367 371
368 secondary_ti = idle_tasks[cpu]->thread_info; 372 secondary_ti = task_thread_info(idle_tasks[cpu]);
369 mb(); 373 mb();
370 374
371 /* 375 /*
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
index 9dbc4d28fa..6d0a1838d9 100644
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -38,9 +38,6 @@
38#include <asm/io.h> 38#include <asm/io.h>
39#include <asm/reg.h> 39#include <asm/reg.h>
40#include <asm/xmon.h> 40#include <asm/xmon.h>
41#ifdef CONFIG_PMAC_BACKLIGHT
42#include <asm/backlight.h>
43#endif
44#include <asm/pmc.h> 41#include <asm/pmc.h>
45 42
46#ifdef CONFIG_XMON 43#ifdef CONFIG_XMON
@@ -85,12 +82,6 @@ int die(const char * str, struct pt_regs * fp, long err)
85 int nl = 0; 82 int nl = 0;
86 console_verbose(); 83 console_verbose();
87 spin_lock_irq(&die_lock); 84 spin_lock_irq(&die_lock);
88#ifdef CONFIG_PMAC_BACKLIGHT
89 if (_machine == _MACH_Pmac) {
90 set_backlight_enable(1);
91 set_backlight_level(BACKLIGHT_MAX);
92 }
93#endif
94 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 85 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
95#ifdef CONFIG_PREEMPT 86#ifdef CONFIG_PREEMPT
96 printk("PREEMPT "); 87 printk("PREEMPT ");
@@ -159,7 +150,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
159 */ 150 */
160static inline int check_io_access(struct pt_regs *regs) 151static inline int check_io_access(struct pt_regs *regs)
161{ 152{
162#if defined CONFIG_PPC_PMAC || defined CONFIG_8xx 153#if defined CONFIG_8xx
163 unsigned long msr = regs->msr; 154 unsigned long msr = regs->msr;
164 const struct exception_table_entry *entry; 155 const struct exception_table_entry *entry;
165 unsigned int *nip = (unsigned int *)regs->nip; 156 unsigned int *nip = (unsigned int *)regs->nip;
@@ -196,7 +187,7 @@ static inline int check_io_access(struct pt_regs *regs)
196 return 1; 187 return 1;
197 } 188 }
198 } 189 }
199#endif /* CONFIG_PPC_PMAC */ 190#endif /* CONFIG_8xx */
200 return 0; 191 return 0;
201} 192}
202 193
diff --git a/arch/ppc/mm/fsl_booke_mmu.c b/arch/ppc/mm/fsl_booke_mmu.c
index af9ca0eb6d..5d581bb3aa 100644
--- a/arch/ppc/mm/fsl_booke_mmu.c
+++ b/arch/ppc/mm/fsl_booke_mmu.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Modifications by Kumar Gala (kumar.gala@freescale.com) to support 2 * Modifications by Kumar Gala (galak@kernel.crashing.org) to support
3 * E500 Book E processors. 3 * E500 Book E processors.
4 * 4 *
5 * Copyright 2004 Freescale Semiconductor, Inc 5 * Copyright 2004 Freescale Semiconductor, Inc
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index 99b48abd32..134db5c042 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -67,10 +67,6 @@ unsigned long ppc_memoffset = PAGE_OFFSET;
67int mem_init_done; 67int mem_init_done;
68int init_bootmem_done; 68int init_bootmem_done;
69int boot_mapsize; 69int boot_mapsize;
70#ifdef CONFIG_PPC_PMAC
71unsigned long agp_special_page;
72EXPORT_SYMBOL(agp_special_page);
73#endif
74 70
75extern char _end[]; 71extern char _end[];
76extern char etext[], _stext[]; 72extern char etext[], _stext[];
@@ -424,10 +420,6 @@ void __init mem_init(void)
424 addr += PAGE_SIZE) 420 addr += PAGE_SIZE)
425 SetPageReserved(virt_to_page(addr)); 421 SetPageReserved(virt_to_page(addr));
426#endif 422#endif
427#ifdef CONFIG_PPC_PMAC
428 if (agp_special_page)
429 SetPageReserved(virt_to_page(agp_special_page));
430#endif
431 for (addr = PAGE_OFFSET; addr < (unsigned long)high_memory; 423 for (addr = PAGE_OFFSET; addr < (unsigned long)high_memory;
432 addr += PAGE_SIZE) { 424 addr += PAGE_SIZE) {
433 if (!PageReserved(virt_to_page(addr))) 425 if (!PageReserved(virt_to_page(addr)))
@@ -463,11 +455,6 @@ void __init mem_init(void)
463 initpages<< (PAGE_SHIFT-10), 455 initpages<< (PAGE_SHIFT-10),
464 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); 456 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
465 457
466#ifdef CONFIG_PPC_PMAC
467 if (agp_special_page)
468 printk(KERN_INFO "AGP special page: 0x%08lx\n", agp_special_page);
469#endif
470
471 mem_init_done = 1; 458 mem_init_done = 1;
472} 459}
473 460
@@ -512,22 +499,6 @@ set_phys_avail(unsigned long total_memory)
512 if (rtas_data) 499 if (rtas_data)
513 mem_pieces_remove(&phys_avail, rtas_data, rtas_size, 1); 500 mem_pieces_remove(&phys_avail, rtas_data, rtas_size, 1);
514#endif 501#endif
515#ifdef CONFIG_PPC_PMAC
516 /* Because of some uninorth weirdness, we need a page of
517 * memory as high as possible (it must be outside of the
518 * bus address seen as the AGP aperture). It will be used
519 * by the r128 DRM driver
520 *
521 * FIXME: We need to make sure that page doesn't overlap any of the\
522 * above. This could be done by improving mem_pieces_find to be able
523 * to do a backward search from the end of the list.
524 */
525 if (_machine == _MACH_Pmac && find_devices("uni-north-agp")) {
526 agp_special_page = (total_memory - PAGE_SIZE);
527 mem_pieces_remove(&phys_avail, agp_special_page, PAGE_SIZE, 0);
528 agp_special_page = (unsigned long)__va(agp_special_page);
529 }
530#endif /* CONFIG_PPC_PMAC */
531} 502}
532 503
533/* Mark some memory as reserved by removing it from phys_avail. */ 504/* Mark some memory as reserved by removing it from phys_avail. */
@@ -597,21 +568,20 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
597 568
598 if (pfn_valid(pfn)) { 569 if (pfn_valid(pfn)) {
599 struct page *page = pfn_to_page(pfn); 570 struct page *page = pfn_to_page(pfn);
600 if (!PageReserved(page)
601 && !test_bit(PG_arch_1, &page->flags)) {
602 if (vma->vm_mm == current->active_mm) {
603#ifdef CONFIG_8xx 571#ifdef CONFIG_8xx
604 /* On 8xx, cache control instructions (particularly 572 /* On 8xx, the TLB handlers work in 2 stages:
605 * "dcbst" from flush_dcache_icache) fault as write 573 * First, a zeroed entry is loaded by TLBMiss handler,
606 * operation if there is an unpopulated TLB entry 574 * which causes the TLBError handler to be triggered.
607 * for the address in question. To workaround that, 575 * That means the zeroed TLB has to be invalidated
608 * we invalidate the TLB here, thus avoiding dcbst 576 * whenever a page miss occurs.
609 * misbehaviour. 577 */
610 */ 578 _tlbie(address);
611 _tlbie(address);
612#endif 579#endif
580 if (!PageReserved(page)
581 && !test_bit(PG_arch_1, &page->flags)) {
582 if (vma->vm_mm == current->active_mm)
613 __flush_dcache_icache((void *) address); 583 __flush_dcache_icache((void *) address);
614 } else 584 else
615 flush_dcache_icache_page(page); 585 flush_dcache_icache_page(page);
616 set_bit(PG_arch_1, &page->flags); 586 set_bit(PG_arch_1, &page->flags);
617 } 587 }
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
index 956f45e4ef..d24c09ee7b 100644
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ b/arch/ppc/platforms/4xx/ibm440gx.c
@@ -58,7 +58,6 @@ static struct ocp_func_emac_data ibm440gx_emac2_def = {
58 .wol_irq = 65, /* WOL interrupt number */ 58 .wol_irq = 65, /* WOL interrupt number */
59 .mdio_idx = -1, /* No shared MDIO */ 59 .mdio_idx = -1, /* No shared MDIO */
60 .tah_idx = 0, /* TAH device index */ 60 .tah_idx = 0, /* TAH device index */
61 .jumbo = 1, /* Jumbo frames supported */
62}; 61};
63 62
64static struct ocp_func_emac_data ibm440gx_emac3_def = { 63static struct ocp_func_emac_data ibm440gx_emac3_def = {
@@ -72,7 +71,6 @@ static struct ocp_func_emac_data ibm440gx_emac3_def = {
72 .wol_irq = 67, /* WOL interrupt number */ 71 .wol_irq = 67, /* WOL interrupt number */
73 .mdio_idx = -1, /* No shared MDIO */ 72 .mdio_idx = -1, /* No shared MDIO */
74 .tah_idx = 1, /* TAH device index */ 73 .tah_idx = 1, /* TAH device index */
75 .jumbo = 1, /* Jumbo frames supported */
76}; 74};
77OCP_SYSFS_EMAC_DATA() 75OCP_SYSFS_EMAC_DATA()
78 76
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index feb17e41ef..71a0117d35 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -31,7 +31,6 @@ static struct ocp_func_emac_data ibm440sp_emac0_def = {
31 .wol_irq = 61, /* WOL interrupt number */ 31 .wol_irq = 61, /* WOL interrupt number */
32 .mdio_idx = -1, /* No shared MDIO */ 32 .mdio_idx = -1, /* No shared MDIO */
33 .tah_idx = -1, /* No TAH */ 33 .tah_idx = -1, /* No TAH */
34 .jumbo = 1, /* Jumbo frames supported */
35}; 34};
36OCP_SYSFS_EMAC_DATA() 35OCP_SYSFS_EMAC_DATA()
37 36
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index 98edc75f41..012e1e652c 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC834x SYS board specific routines 4 * MPC834x SYS board specific routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
@@ -51,9 +51,6 @@
51 51
52#include <syslib/ppc83xx_setup.h> 52#include <syslib/ppc83xx_setup.h>
53 53
54static const char *GFAR_PHY_0 = "phy0:0";
55static const char *GFAR_PHY_1 = "phy0:1";
56
57#ifndef CONFIG_PCI 54#ifndef CONFIG_PCI
58unsigned long isa_io_base = 0; 55unsigned long isa_io_base = 0;
59unsigned long isa_mem_base = 0; 56unsigned long isa_mem_base = 0;
@@ -73,12 +70,19 @@ mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
73 * A B C D 70 * A B C D
74 */ 71 */
75 { 72 {
76 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */ 73 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
77 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */ 74 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
78 {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */ 75 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
76 {0, 0, 0, 0},
77 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
78 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
79 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
80 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
81 {0, 0, 0, 0}, /* idsel 0x19 */
82 {0, 0, 0, 0}, /* idsel 0x20 */
79 }; 83 };
80 84
81 const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4; 85 const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
82 return PCI_IRQ_TABLE_LOOKUP; 86 return PCI_IRQ_TABLE_LOOKUP;
83} 87}
84 88
@@ -122,20 +126,21 @@ mpc834x_sys_setup_arch(void)
122 mdata->irq[1] = MPC83xx_IRQ_EXT2; 126 mdata->irq[1] = MPC83xx_IRQ_EXT2;
123 mdata->irq[2] = -1; 127 mdata->irq[2] = -1;
124 mdata->irq[31] = -1; 128 mdata->irq[31] = -1;
125 mdata->paddr += binfo->bi_immr_base;
126 129
127 /* setup the board related information for the enet controllers */ 130 /* setup the board related information for the enet controllers */
128 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1); 131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
129 if (pdata) { 132 if (pdata) {
130 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 133 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
131 pdata->bus_id = GFAR_PHY_0; 134 pdata->bus_id = 0;
135 pdata->phy_id = 0;
132 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 136 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
133 } 137 }
134 138
135 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2); 139 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
136 if (pdata) { 140 if (pdata) {
137 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 141 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
138 pdata->bus_id = GFAR_PHY_1; 142 pdata->bus_id = 0;
143 pdata->phy_id = 1;
139 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 144 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
140 } 145 }
141 146
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index 58e44c0425..2e514d316f 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC834X SYS common board definitions 4 * MPC834X SYS common board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor, Inc. 8 * Copyright 2005 Freescale Semiconductor, Inc.
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/Kconfig b/arch/ppc/platforms/85xx/Kconfig
index c5bc2821d9..7ddd331a71 100644
--- a/arch/ppc/platforms/85xx/Kconfig
+++ b/arch/ppc/platforms/85xx/Kconfig
@@ -39,7 +39,7 @@ config MPC8560_ADS
39config SBC8560 39config SBC8560
40 bool "WindRiver PowerQUICC III SBC8560" 40 bool "WindRiver PowerQUICC III SBC8560"
41 help 41 help
42 This option enables support for the WindRiver PowerQUICC III 42 This option enables support for the WindRiver PowerQUICC III
43 SBC8560 board. 43 SBC8560 board.
44 44
45config STX_GP3 45config STX_GP3
@@ -48,6 +48,26 @@ config STX_GP3
48 This option enables support for the Silicon Turnkey Express GP3 48 This option enables support for the Silicon Turnkey Express GP3
49 board. 49 board.
50 50
51config TQM8540
52 bool "TQ Components TQM8540"
53 help
54 This option enablese support for the TQ Components TQM8540 board.
55
56config TQM8541
57 bool "TQ Components TQM8541"
58 help
59 This option enablese support for the TQ Components TQM8541 board.
60
61config TQM8555
62 bool "TQ Components TQM8555"
63 help
64 This option enablese support for the TQ Components TQM8555 board.
65
66config TQM8560
67 bool "TQ Components TQM8560"
68 help
69 This option enablese support for the TQ Components TQM8560 board.
70
51endchoice 71endchoice
52 72
53# It's often necessary to know the specific 85xx processor type. 73# It's often necessary to know the specific 85xx processor type.
@@ -55,7 +75,7 @@ endchoice
55# don't need to ask more redundant questions. 75# don't need to ask more redundant questions.
56config MPC8540 76config MPC8540
57 bool 77 bool
58 depends on MPC8540_ADS 78 depends on MPC8540_ADS || TQM8540
59 default y 79 default y
60 80
61config MPC8548 81config MPC8548
@@ -65,12 +85,12 @@ config MPC8548
65 85
66config MPC8555 86config MPC8555
67 bool 87 bool
68 depends on MPC8555_CDS 88 depends on MPC8555_CDS || TQM8541 || TQM8555
69 default y 89 default y
70 90
71config MPC8560 91config MPC8560
72 bool 92 bool
73 depends on SBC8560 || MPC8560_ADS || STX_GP3 93 depends on SBC8560 || MPC8560_ADS || STX_GP3 || TQM8560
74 default y 94 default y
75 95
76config 85xx_PCI2 96config 85xx_PCI2
diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile
index efdf813108..6c4753c144 100644
--- a/arch/ppc/platforms/85xx/Makefile
+++ b/arch/ppc/platforms/85xx/Makefile
@@ -7,3 +7,7 @@ obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o
7obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o 7obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o
8obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o 8obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o
9obj-$(CONFIG_STX_GP3) += stx_gp3.o 9obj-$(CONFIG_STX_GP3) += stx_gp3.o
10obj-$(CONFIG_TQM8540) += tqm85xx.o
11obj-$(CONFIG_TQM8541) += tqm85xx.o
12obj-$(CONFIG_TQM8555) += tqm85xx.o
13obj-$(CONFIG_TQM8560) += tqm85xx.o
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index 7e952c1228..2eceb1e6f4 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8540ADS board specific routines 4 * MPC8540ADS board specific routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
@@ -52,10 +52,6 @@
52 52
53#include <syslib/ppc85xx_setup.h> 53#include <syslib/ppc85xx_setup.h>
54 54
55static const char *GFAR_PHY_0 = "phy0:0";
56static const char *GFAR_PHY_1 = "phy0:1";
57static const char *GFAR_PHY_3 = "phy0:3";
58
59/* ************************************************************************ 55/* ************************************************************************
60 * 56 *
61 * Setup the architecture 57 * Setup the architecture
@@ -102,27 +98,29 @@ mpc8540ads_setup_arch(void)
102 mdata->irq[2] = -1; 98 mdata->irq[2] = -1;
103 mdata->irq[3] = MPC85xx_IRQ_EXT5; 99 mdata->irq[3] = MPC85xx_IRQ_EXT5;
104 mdata->irq[31] = -1; 100 mdata->irq[31] = -1;
105 mdata->paddr += binfo->bi_immr_base;
106 101
107 /* setup the board related information for the enet controllers */ 102 /* setup the board related information for the enet controllers */
108 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 103 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
109 if (pdata) { 104 if (pdata) {
110 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 105 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
111 pdata->bus_id = GFAR_PHY_0; 106 pdata->bus_id = 0;
107 pdata->phy_id = 0;
112 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 108 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
113 } 109 }
114 110
115 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 111 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
116 if (pdata) { 112 if (pdata) {
117 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 113 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
118 pdata->bus_id = GFAR_PHY_1; 114 pdata->bus_id = 0;
115 pdata->phy_id = 1;
119 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 116 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
120 } 117 }
121 118
122 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 119 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
123 if (pdata) { 120 if (pdata) {
124 pdata->board_flags = 0; 121 pdata->board_flags = 0;
125 pdata->bus_id = GFAR_PHY_3; 122 pdata->bus_id = 0;
123 pdata->phy_id = 3;
126 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 124 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
127 } 125 }
128 126
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.h b/arch/ppc/platforms/85xx/mpc8540_ads.h
index 3d05d7c4a9..e48ca3a973 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.h
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8540ADS board definitions 4 * MPC8540ADS board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/mpc8555_cds.h b/arch/ppc/platforms/85xx/mpc8555_cds.h
index e0e75568bc..1a8e6c6735 100644
--- a/arch/ppc/platforms/85xx/mpc8555_cds.h
+++ b/arch/ppc/platforms/85xx/mpc8555_cds.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8555CDS board definitions 4 * MPC8555CDS board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index 208433f1e9..442c7ff195 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8560ADS board specific routines 4 * MPC8560ADS board specific routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
@@ -56,10 +56,6 @@
56#include <syslib/ppc85xx_setup.h> 56#include <syslib/ppc85xx_setup.h>
57 57
58 58
59static const char *GFAR_PHY_0 = "phy0:0";
60static const char *GFAR_PHY_1 = "phy0:1";
61static const char *GFAR_PHY_3 = "phy0:3";
62
63/* ************************************************************************ 59/* ************************************************************************
64 * 60 *
65 * Setup the architecture 61 * Setup the architecture
@@ -99,20 +95,21 @@ mpc8560ads_setup_arch(void)
99 mdata->irq[2] = -1; 95 mdata->irq[2] = -1;
100 mdata->irq[3] = MPC85xx_IRQ_EXT5; 96 mdata->irq[3] = MPC85xx_IRQ_EXT5;
101 mdata->irq[31] = -1; 97 mdata->irq[31] = -1;
102 mdata->paddr += binfo->bi_immr_base;
103 98
104 /* setup the board related information for the enet controllers */ 99 /* setup the board related information for the enet controllers */
105 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 100 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
106 if (pdata) { 101 if (pdata) {
107 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 102 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
108 pdata->bus_id = GFAR_PHY_0; 103 pdata->bus_id = 0;
104 pdata->phy_id = 0;
109 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 105 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
110 } 106 }
111 107
112 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 108 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
113 if (pdata) { 109 if (pdata) {
114 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 110 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
115 pdata->bus_id = GFAR_PHY_1; 111 pdata->bus_id = 0;
112 pdata->phy_id = 1;
116 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 113 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
117 } 114 }
118 115
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.h b/arch/ppc/platforms/85xx/mpc8560_ads.h
index 7df885d73e..143ae7eefa 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.h
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8540ADS board definitions 4 * MPC8540ADS board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
index 16ad092d8a..17ce48fe35 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx ADS board common routines 4 * MPC85xx ADS board common routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
index 84acf6e8d4..198a6a02cd 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85XX ADS common board definitions 4 * MPC85XX ADS common board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
@@ -25,6 +25,8 @@
25#define BCSR_ADDR ((uint)0xf8000000) 25#define BCSR_ADDR ((uint)0xf8000000)
26#define BCSR_SIZE ((uint)(32 * 1024)) 26#define BCSR_SIZE ((uint)(32 * 1024))
27 27
28struct seq_file;
29
28extern int mpc85xx_ads_show_cpuinfo(struct seq_file *m); 30extern int mpc85xx_ads_show_cpuinfo(struct seq_file *m);
29extern void mpc85xx_ads_init_IRQ(void) __init; 31extern void mpc85xx_ads_init_IRQ(void) __init;
30extern void mpc85xx_ads_map_io(void) __init; 32extern void mpc85xx_ads_map_io(void) __init;
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index a21156967a..b332ebae6b 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx CDS board specific routines 4 * MPC85xx CDS board specific routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor, Inc 8 * Copyright 2004 Freescale Semiconductor, Inc
9 * 9 *
@@ -130,10 +130,11 @@ mpc85xx_cds_show_cpuinfo(struct seq_file *m)
130} 130}
131 131
132#ifdef CONFIG_CPM2 132#ifdef CONFIG_CPM2
133static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) 133static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
134{ 134{
135 while((irq = cpm2_get_irq(regs)) >= 0) 135 while((irq = cpm2_get_irq(regs)) >= 0)
136 __do_IRQ(irq, regs); 136 __do_IRQ(irq, regs);
137 return IRQ_HANDLED;
137} 138}
138 139
139static struct irqaction cpm2_irqaction = { 140static struct irqaction cpm2_irqaction = {
@@ -350,10 +351,10 @@ mpc85xx_cds_fixup_via(struct pci_controller *hose)
350void __init 351void __init
351mpc85xx_cds_pcibios_fixup(void) 352mpc85xx_cds_pcibios_fixup(void)
352{ 353{
353 struct pci_dev *dev = NULL; 354 struct pci_dev *dev;
354 u_char c; 355 u_char c;
355 356
356 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, 357 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
357 PCI_DEVICE_ID_VIA_82C586_1, NULL))) { 358 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
358 /* 359 /*
359 * U-Boot does not set the enable bits 360 * U-Boot does not set the enable bits
@@ -370,30 +371,30 @@ mpc85xx_cds_pcibios_fixup(void)
370 */ 371 */
371 dev->irq = 14; 372 dev->irq = 14;
372 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 373 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
374 pci_dev_put(dev);
373 } 375 }
374 376
375 /* 377 /*
376 * Force legacy USB interrupt routing 378 * Force legacy USB interrupt routing
377 */ 379 */
378 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, 380 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
379 PCI_DEVICE_ID_VIA_82C586_2, NULL))) { 381 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
380 dev->irq = 10; 382 dev->irq = 10;
381 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10); 383 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
384 pci_dev_put(dev);
382 } 385 }
383 386
384 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, 387 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
385 PCI_DEVICE_ID_VIA_82C586_2, dev))) { 388 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
386 dev->irq = 11; 389 dev->irq = 11;
387 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 390 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
391 pci_dev_put(dev);
388 } 392 }
389} 393}
390#endif /* CONFIG_PCI */ 394#endif /* CONFIG_PCI */
391 395
392TODC_ALLOC(); 396TODC_ALLOC();
393 397
394static const char *GFAR_PHY_0 = "phy0:0";
395static const char *GFAR_PHY_1 = "phy0:1";
396
397/* ************************************************************************ 398/* ************************************************************************
398 * 399 *
399 * Setup the architecture 400 * Setup the architecture
@@ -457,34 +458,37 @@ mpc85xx_cds_setup_arch(void)
457 mdata->irq[2] = -1; 458 mdata->irq[2] = -1;
458 mdata->irq[3] = -1; 459 mdata->irq[3] = -1;
459 mdata->irq[31] = -1; 460 mdata->irq[31] = -1;
460 mdata->paddr += binfo->bi_immr_base;
461 461
462 /* setup the board related information for the enet controllers */ 462 /* setup the board related information for the enet controllers */
463 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 463 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
464 if (pdata) { 464 if (pdata) {
465 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 465 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
466 pdata->bus_id = GFAR_PHY_0; 466 pdata->bus_id = 0;
467 pdata->phy_id = 0;
467 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 468 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
468 } 469 }
469 470
470 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 471 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
471 if (pdata) { 472 if (pdata) {
472 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 473 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
473 pdata->bus_id = GFAR_PHY_1; 474 pdata->bus_id = 0;
475 pdata->phy_id = 1;
474 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 476 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
475 } 477 }
476 478
477 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); 479 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
478 if (pdata) { 480 if (pdata) {
479 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 481 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
480 pdata->bus_id = GFAR_PHY_0; 482 pdata->bus_id = 0;
483 pdata->phy_id = 0;
481 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 484 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
482 } 485 }
483 486
484 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); 487 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
485 if (pdata) { 488 if (pdata) {
486 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 489 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
487 pdata->bus_id = GFAR_PHY_1; 490 pdata->bus_id = 0;
491 pdata->phy_id = 1;
488 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 492 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
489 } 493 }
490 494
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
index 12b292c6ae..5b588cfd0e 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx CDS board definitions 4 * MPC85xx CDS board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor, Inc 8 * Copyright 2004 Freescale Semiconductor, Inc
9 * 9 *
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index b4ee1707a8..e777ba824a 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Wind River SBC8560 board specific routines 4 * Wind River SBC8560 board specific routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
@@ -91,9 +91,6 @@ sbc8560_early_serial_map(void)
91} 91}
92#endif 92#endif
93 93
94static const char *GFAR_PHY_25 = "phy0:25";
95static const char *GFAR_PHY_26 = "phy0:26";
96
97/* ************************************************************************ 94/* ************************************************************************
98 * 95 *
99 * Setup the architecture 96 * Setup the architecture
@@ -136,20 +133,21 @@ sbc8560_setup_arch(void)
136 mdata->irq[25] = MPC85xx_IRQ_EXT6; 133 mdata->irq[25] = MPC85xx_IRQ_EXT6;
137 mdata->irq[26] = MPC85xx_IRQ_EXT7; 134 mdata->irq[26] = MPC85xx_IRQ_EXT7;
138 mdata->irq[31] = -1; 135 mdata->irq[31] = -1;
139 mdata->paddr += binfo->bi_immr_base;
140 136
141 /* setup the board related information for the enet controllers */ 137 /* setup the board related information for the enet controllers */
142 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 138 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
143 if (pdata) { 139 if (pdata) {
144 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 140 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
145 pdata->bus_id = GFAR_PHY_25; 141 pdata->bus_id = 0;
142 pdata->phy_id = 25;
146 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 143 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
147 } 144 }
148 145
149 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 146 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
150 if (pdata) { 147 if (pdata) {
151 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 148 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
152 pdata->bus_id = GFAR_PHY_26; 149 pdata->bus_id = 0;
150 pdata->phy_id = 26;
153 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 151 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
154 } 152 }
155 153
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index 15ce9d0706..061bb7cf2d 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -93,9 +93,6 @@ static u8 gp3_openpic_initsenses[] __initdata = {
93 0x0, /* External 11: */ 93 0x0, /* External 11: */
94}; 94};
95 95
96static const char *GFAR_PHY_2 = "phy0:2";
97static const char *GFAR_PHY_4 = "phy0:4";
98
99/* 96/*
100 * Setup the architecture 97 * Setup the architecture
101 */ 98 */
@@ -130,20 +127,21 @@ gp3_setup_arch(void)
130 mdata->irq[2] = MPC85xx_IRQ_EXT5; 127 mdata->irq[2] = MPC85xx_IRQ_EXT5;
131 mdata->irq[4] = MPC85xx_IRQ_EXT5; 128 mdata->irq[4] = MPC85xx_IRQ_EXT5;
132 mdata->irq[31] = -1; 129 mdata->irq[31] = -1;
133 mdata->paddr += binfo->bi_immr_base;
134 130
135 /* setup the board related information for the enet controllers */ 131 /* setup the board related information for the enet controllers */
136 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 132 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
137 if (pdata) { 133 if (pdata) {
138 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 134 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
139 pdata->bus_id = GFAR_PHY_2; 135 pdata->bus_id = 0;
136 pdata->phy_id = 2;
140 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 137 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
141 } 138 }
142 139
143 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 140 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
144 if (pdata) { 141 if (pdata) {
145 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 142 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
146 pdata->bus_id = GFAR_PHY_4; 143 pdata->bus_id = 0;
144 pdata->phy_id = 4;
147 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 145 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
148 } 146 }
149 147
diff --git a/arch/ppc/platforms/85xx/stx_gp3.h b/arch/ppc/platforms/85xx/stx_gp3.h
index 7bcc6c35a4..2f25b51951 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.h
+++ b/arch/ppc/platforms/85xx/stx_gp3.h
@@ -21,7 +21,6 @@
21 21
22#include <linux/config.h> 22#include <linux/config.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/seq_file.h>
25#include <asm/ppcboot.h> 24#include <asm/ppcboot.h>
26 25
27#define BOARD_CCSRBAR ((uint)0xe0000000) 26#define BOARD_CCSRBAR ((uint)0xe0000000)
@@ -43,7 +42,6 @@ extern void mpc85xx_setup_hose(void) __init;
43extern void mpc85xx_restart(char *cmd); 42extern void mpc85xx_restart(char *cmd);
44extern void mpc85xx_power_off(void); 43extern void mpc85xx_power_off(void);
45extern void mpc85xx_halt(void); 44extern void mpc85xx_halt(void);
46extern int mpc85xx_show_cpuinfo(struct seq_file *m);
47extern void mpc85xx_init_IRQ(void) __init; 45extern void mpc85xx_init_IRQ(void) __init;
48extern unsigned long mpc85xx_find_end_of_memory(void) __init; 46extern unsigned long mpc85xx_find_end_of_memory(void) __init;
49extern void mpc85xx_calibrate_decr(void) __init; 47extern void mpc85xx_calibrate_decr(void) __init;
diff --git a/arch/ppc/platforms/85xx/tqm85xx.c b/arch/ppc/platforms/85xx/tqm85xx.c
new file mode 100644
index 0000000000..b436f4d0a3
--- /dev/null
+++ b/arch/ppc/platforms/85xx/tqm85xx.c
@@ -0,0 +1,415 @@
1/*
2 * arch/ppc/platforms/85xx/tqm85xx.c
3 *
4 * TQM85xx (40/41/55/60) board specific routines
5 *
6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * Based on original work by
10 * Kumar Gala <galak@kernel.crashing.org>
11 * Copyright 2004 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/config.h>
20#include <linux/stddef.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/reboot.h>
25#include <linux/pci.h>
26#include <linux/kdev_t.h>
27#include <linux/major.h>
28#include <linux/console.h>
29#include <linux/delay.h>
30#include <linux/seq_file.h>
31#include <linux/root_dev.h>
32#include <linux/serial.h>
33#include <linux/tty.h> /* for linux/serial_core.h */
34#include <linux/serial_core.h>
35#include <linux/initrd.h>
36#include <linux/module.h>
37#include <linux/fsl_devices.h>
38
39#include <asm/system.h>
40#include <asm/pgtable.h>
41#include <asm/page.h>
42#include <asm/atomic.h>
43#include <asm/time.h>
44#include <asm/io.h>
45#include <asm/machdep.h>
46#include <asm/open_pic.h>
47#include <asm/bootinfo.h>
48#include <asm/pci-bridge.h>
49#include <asm/mpc85xx.h>
50#include <asm/irq.h>
51#include <asm/immap_85xx.h>
52#include <asm/kgdb.h>
53#include <asm/ppc_sys.h>
54#include <asm/cpm2.h>
55#include <mm/mmu_decl.h>
56
57#include <syslib/ppc85xx_setup.h>
58#include <syslib/cpm2_pic.h>
59#include <syslib/ppc85xx_common.h>
60#include <syslib/ppc85xx_rio.h>
61
62#ifndef CONFIG_PCI
63unsigned long isa_io_base = 0;
64unsigned long isa_mem_base = 0;
65#endif
66
67
68extern unsigned long total_memory; /* in mm/init */
69
70unsigned char __res[sizeof (bd_t)];
71
72/* Internal interrupts are all Level Sensitive, and Positive Polarity */
73static u_char tqm85xx_openpic_initsenses[] __initdata = {
74 MPC85XX_INTERNAL_IRQ_SENSES,
75 0x0, /* External 0: */
76 0x0, /* External 1: */
77#if defined(CONFIG_PCI)
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI INTA */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI INTB */
80#else
81 0x0, /* External 2: */
82 0x0, /* External 3: */
83#endif
84 0x0, /* External 4: */
85 0x0, /* External 5: */
86 0x0, /* External 6: */
87 0x0, /* External 7: */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: PHY */
89 0x0, /* External 9: */
90 0x0, /* External 10: */
91 0x0, /* External 11: */
92};
93
94/* ************************************************************************
95 *
96 * Setup the architecture
97 *
98 */
99static void __init
100tqm85xx_setup_arch(void)
101{
102 bd_t *binfo = (bd_t *) __res;
103 unsigned int freq;
104 struct gianfar_platform_data *pdata;
105 struct gianfar_mdio_data *mdata;
106
107#ifdef CONFIG_MPC8560
108 cpm2_reset();
109#endif
110
111 /* get the core frequency */
112 freq = binfo->bi_intfreq;
113
114 if (ppc_md.progress)
115 ppc_md.progress("tqm85xx_setup_arch()", 0);
116
117 /* Set loops_per_jiffy to a half-way reasonable value,
118 for use until calibrate_delay gets called. */
119 loops_per_jiffy = freq / HZ;
120
121#ifdef CONFIG_PCI
122 /* setup PCI host bridges */
123 mpc85xx_setup_hose();
124#endif
125
126#ifndef CONFIG_MPC8560
127#if defined(CONFIG_SERIAL_8250)
128 mpc85xx_early_serial_map();
129#endif
130
131#ifdef CONFIG_SERIAL_TEXT_DEBUG
132 /* Invalidate the entry we stole earlier the serial ports
133 * should be properly mapped */
134 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
135#endif
136#endif /* CONFIG_MPC8560 */
137
138 /* setup the board related info for the MDIO bus */
139 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
140
141 mdata->irq[0] = MPC85xx_IRQ_EXT8;
142 mdata->irq[1] = MPC85xx_IRQ_EXT8;
143 mdata->irq[2] = -1;
144 mdata->irq[3] = MPC85xx_IRQ_EXT8;
145 mdata->irq[31] = -1;
146
147 /* setup the board related information for the enet controllers */
148 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
149 if (pdata) {
150 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
151 pdata->bus_id = 0;
152 pdata->phy_id = 2;
153 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
154 }
155
156 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
157 if (pdata) {
158 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
159 pdata->bus_id = 0;
160 pdata->phy_id = 1;
161 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
162 }
163
164#ifdef CONFIG_MPC8540
165 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
166 if (pdata) {
167 pdata->board_flags = 0;
168 pdata->bus_id = 0;
169 pdata->phy_id = 3;
170 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
171 }
172#endif
173
174#ifdef CONFIG_BLK_DEV_INITRD
175 if (initrd_start)
176 ROOT_DEV = Root_RAM0;
177 else
178#endif
179#ifdef CONFIG_ROOT_NFS
180 ROOT_DEV = Root_NFS;
181#else
182 ROOT_DEV = Root_HDA1;
183#endif
184}
185
186#ifdef CONFIG_MPC8560
187static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
188{
189 while ((irq = cpm2_get_irq(regs)) >= 0)
190 __do_IRQ(irq, regs);
191 return IRQ_HANDLED;
192}
193
194static struct irqaction cpm2_irqaction = {
195 .handler = cpm2_cascade,
196 .flags = SA_INTERRUPT,
197 .mask = CPU_MASK_NONE,
198 .name = "cpm2_cascade",
199};
200#endif /* CONFIG_MPC8560 */
201
202void __init
203tqm85xx_init_IRQ(void)
204{
205 bd_t *binfo = (bd_t *) __res;
206
207 /* Determine the Physical Address of the OpenPIC regs */
208 phys_addr_t OpenPIC_PAddr =
209 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
210 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
211 OpenPIC_InitSenses = tqm85xx_openpic_initsenses;
212 OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses);
213
214 /* Skip reserved space and internal sources */
215 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
216
217 /* Map PIC IRQs 0-11 */
218 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
219
220 /* we let openpic interrupts starting from an offset, to
221 * leave space for cascading interrupts underneath.
222 */
223 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
224
225#ifdef CONFIG_MPC8560
226 /* Setup CPM2 PIC */
227 cpm2_init_IRQ();
228
229 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
230#endif /* CONFIG_MPC8560 */
231
232 return;
233}
234
235int tqm85xx_show_cpuinfo(struct seq_file *m)
236{
237 uint pvid, svid, phid1;
238 uint memsize = total_memory;
239 bd_t *binfo = (bd_t *) __res;
240 unsigned int freq;
241
242 /* get the core frequency */
243 freq = binfo->bi_intfreq;
244
245 pvid = mfspr(SPRN_PVR);
246 svid = mfspr(SPRN_SVR);
247
248 seq_printf(m, "Vendor\t\t: TQ Components\n");
249 seq_printf(m, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec->ppc_sys_name);
250 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
251 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
252 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
253
254 /* Display cpu Pll setting */
255 phid1 = mfspr(SPRN_HID1);
256 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
257
258 /* Display the amount of memory */
259 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
260
261 return 0;
262}
263
264#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_DS1337)
265extern ulong ds1337_get_rtc_time(void);
266extern int ds1337_set_rtc_time(unsigned long nowtime);
267
268static int __init
269tqm85xx_rtc_hookup(void)
270{
271 struct timespec tv;
272
273 ppc_md.set_rtc_time = ds1337_set_rtc_time;
274 ppc_md.get_rtc_time = ds1337_get_rtc_time;
275
276 tv.tv_nsec = 0;
277 tv.tv_sec = (ppc_md.get_rtc_time)();
278 do_settimeofday(&tv);
279
280 return 0;
281}
282late_initcall(tqm85xx_rtc_hookup);
283#endif
284
285#ifdef CONFIG_PCI
286/*
287 * interrupt routing
288 */
289int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
290{
291 static char pci_irq_table[][4] =
292 /*
293 * PCI IDSEL/INTPIN->INTLINE
294 * A B C D
295 */
296 {
297 {PIRQA, PIRQB, 0, 0},
298 };
299
300 const long min_idsel = 0x1c, max_idsel = 0x1c, irqs_per_slot = 4;
301 return PCI_IRQ_TABLE_LOOKUP;
302}
303
304int mpc85xx_exclude_device(u_char bus, u_char devfn)
305{
306 if (bus == 0 && PCI_SLOT(devfn) == 0)
307 return PCIBIOS_DEVICE_NOT_FOUND;
308 else
309 return PCIBIOS_SUCCESSFUL;
310}
311
312#endif /* CONFIG_PCI */
313
314#ifdef CONFIG_RAPIDIO
315void platform_rio_init(void)
316{
317 /* 512MB RIO LAW at 0xc0000000 */
318 mpc85xx_rio_setup(0xc0000000, 0x20000000);
319}
320#endif /* CONFIG_RAPIDIO */
321
322/* ************************************************************************ */
323void __init
324platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
325 unsigned long r6, unsigned long r7)
326{
327 /* parse_bootinfo must always be called first */
328 parse_bootinfo(find_bootinfo());
329
330 /*
331 * If we were passed in a board information, copy it into the
332 * residual data area.
333 */
334 if (r3) {
335 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
336 sizeof (bd_t));
337 }
338
339#if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560)
340 {
341 bd_t *binfo = (bd_t *) __res;
342 struct uart_port p;
343
344 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
345 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
346 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
347
348 memset(&p, 0, sizeof (p));
349 p.iotype = SERIAL_IO_MEM;
350 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
351 p.uartclk = binfo->bi_busfreq;
352
353 gen550_init(0, &p);
354
355 memset(&p, 0, sizeof (p));
356 p.iotype = SERIAL_IO_MEM;
357 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
358 p.uartclk = binfo->bi_busfreq;
359
360 gen550_init(1, &p);
361 }
362#endif
363
364#if defined(CONFIG_BLK_DEV_INITRD)
365 /*
366 * If the init RAM disk has been configured in, and there's a valid
367 * starting address for it, set it up.
368 */
369 if (r4) {
370 initrd_start = r4 + KERNELBASE;
371 initrd_end = r5 + KERNELBASE;
372 }
373#endif /* CONFIG_BLK_DEV_INITRD */
374
375 /* Copy the kernel command line arguments to a safe place. */
376
377 if (r6) {
378 *(char *) (r7 + KERNELBASE) = 0;
379 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
380 }
381
382 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
383
384 /* setup the PowerPC module struct */
385 ppc_md.setup_arch = tqm85xx_setup_arch;
386 ppc_md.show_cpuinfo = tqm85xx_show_cpuinfo;
387
388 ppc_md.init_IRQ = tqm85xx_init_IRQ;
389 ppc_md.get_irq = openpic_get_irq;
390
391 ppc_md.restart = mpc85xx_restart;
392 ppc_md.power_off = mpc85xx_power_off;
393 ppc_md.halt = mpc85xx_halt;
394
395 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
396
397 ppc_md.time_init = NULL;
398 ppc_md.set_rtc_time = NULL;
399 ppc_md.get_rtc_time = NULL;
400 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
401
402#ifndef CONFIG_MPC8560
403#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
404 ppc_md.progress = gen550_progress;
405#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
406#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
407 ppc_md.early_serial_map = mpc85xx_early_serial_map;
408#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
409#endif /* CONFIG_MPC8560 */
410
411 if (ppc_md.progress)
412 ppc_md.progress("tqm85xx_init(): exit", 0);
413
414 return;
415}
diff --git a/arch/ppc/platforms/85xx/tqm85xx.h b/arch/ppc/platforms/85xx/tqm85xx.h
new file mode 100644
index 0000000000..3775eb363f
--- /dev/null
+++ b/arch/ppc/platforms/85xx/tqm85xx.h
@@ -0,0 +1,56 @@
1/*
2 * arch/ppc/platforms/85xx/tqm85xx.h
3 *
4 * TQM85xx (40/41/55/60) board definitions
5 *
6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __MACH_TQM85XX_H
17#define __MACH_TQM85XX_H
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <asm/ppcboot.h>
22
23#define BOARD_CCSRBAR ((uint)0xe0000000)
24#define CCSRBAR_SIZE ((uint)1024*1024)
25
26#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
27
28#define PCI_CFG_ADDR_OFFSET (0x8000)
29#define PCI_CFG_DATA_OFFSET (0x8004)
30
31/* PCI interrupt controller */
32#define PIRQA MPC85xx_IRQ_EXT2
33#define PIRQB MPC85xx_IRQ_EXT3
34
35#define MPC85XX_PCI1_LOWER_IO 0x00000000
36#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
37
38#define MPC85XX_PCI1_LOWER_MEM 0x80000000
39#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
40
41#define MPC85XX_PCI1_IO_BASE 0xe2000000
42#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
43
44#define MPC85XX_PCI1_IO_SIZE 0x01000000
45
46#define BASE_BAUD 115200
47
48extern void mpc85xx_setup_hose(void) __init;
49extern void mpc85xx_restart(char *cmd);
50extern void mpc85xx_power_off(void);
51extern void mpc85xx_halt(void);
52extern void mpc85xx_init_IRQ(void) __init;
53extern unsigned long mpc85xx_find_end_of_memory(void) __init;
54extern void mpc85xx_calibrate_decr(void) __init;
55
56#endif /* __MACH_TQM85XX_H */
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 7c5cdabf6f..51430e294b 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -3,26 +3,18 @@
3# 3#
4 4
5# Extra CFLAGS so we don't have to do relative includes 5# Extra CFLAGS so we don't have to do relative includes
6CFLAGS_pmac_setup.o += -Iarch/$(ARCH)/mm 6CFLAGS_chrp_setup.o += -Iarch/$(ARCH)/mm
7 7
8obj-$(CONFIG_APUS) += apus_setup.o 8obj-$(CONFIG_APUS) += apus_setup.o
9ifeq ($(CONFIG_APUS),y) 9ifeq ($(CONFIG_APUS),y)
10obj-$(CONFIG_PCI) += apus_pci.o 10obj-$(CONFIG_PCI) += apus_pci.o
11endif 11endif
12obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \
13 pmac_feature.o pmac_pci.o pmac_sleep.o \
14 pmac_low_i2c.o pmac_cache.o
15obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \ 12obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \
16 chrp_pegasos_eth.o 13 chrp_pegasos_eth.o
17ifeq ($(CONFIG_PPC_CHRP),y) 14ifeq ($(CONFIG_PPC_CHRP),y)
18obj-$(CONFIG_NVRAM) += chrp_nvram.o 15obj-$(CONFIG_NVRAM) += chrp_nvram.o
19endif 16endif
20obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o 17obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
21ifeq ($(CONFIG_PPC_PMAC),y)
22obj-$(CONFIG_NVRAM) += pmac_nvram.o
23obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
24endif
25obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
26obj-$(CONFIG_PREP_RESIDUAL) += residual.o 18obj-$(CONFIG_PREP_RESIDUAL) += residual.o
27obj-$(CONFIG_PQ2ADS) += pq2ads.o 19obj-$(CONFIG_PQ2ADS) += pq2ads.o
28obj-$(CONFIG_TQM8260) += tqm8260_setup.o 20obj-$(CONFIG_TQM8260) += tqm8260_setup.o
@@ -47,6 +39,5 @@ obj-$(CONFIG_LITE5200) += lite5200.o
47obj-$(CONFIG_EV64360) += ev64360.o 39obj-$(CONFIG_EV64360) += ev64360.o
48 40
49ifeq ($(CONFIG_SMP),y) 41ifeq ($(CONFIG_SMP),y)
50obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
51obj-$(CONFIG_PPC_CHRP) += chrp_smp.o 42obj-$(CONFIG_PPC_CHRP) += chrp_smp.o
52endif 43endif
diff --git a/arch/ppc/platforms/apus_setup.c b/arch/ppc/platforms/apus_setup.c
index 2f74fde98e..c42c50073d 100644
--- a/arch/ppc/platforms/apus_setup.c
+++ b/arch/ppc/platforms/apus_setup.c
@@ -55,9 +55,6 @@ int (*mach_hwclk) (int, struct hwclk_time*) = NULL;
55int (*mach_set_clock_mmss) (unsigned long) = NULL; 55int (*mach_set_clock_mmss) (unsigned long) = NULL;
56void (*mach_reset)( void ); 56void (*mach_reset)( void );
57long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */ 57long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */
58#if defined(CONFIG_AMIGA_FLOPPY)
59void (*mach_floppy_setup) (char *, int *) __initdata = NULL;
60#endif
61#ifdef CONFIG_HEARTBEAT 58#ifdef CONFIG_HEARTBEAT
62void (*mach_heartbeat) (int) = NULL; 59void (*mach_heartbeat) (int) = NULL;
63extern void apus_heartbeat (void); 60extern void apus_heartbeat (void);
@@ -76,7 +73,6 @@ struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */
76 73
77struct mem_info ramdisk; 74struct mem_info ramdisk;
78 75
79extern void amiga_floppy_setup(char *, int *);
80extern void config_amiga(void); 76extern void config_amiga(void);
81 77
82static int __60nsram = 0; 78static int __60nsram = 0;
@@ -305,16 +301,6 @@ void kbd_reset_setup(char *str, int *ints)
305{ 301{
306} 302}
307 303
308/*********************************************************** FLOPPY */
309#if defined(CONFIG_AMIGA_FLOPPY)
310__init
311void floppy_setup(char *str, int *ints)
312{
313 if (mach_floppy_setup)
314 mach_floppy_setup (str, ints);
315}
316#endif
317
318/*********************************************************** MEMORY */ 304/*********************************************************** MEMORY */
319#define KMAP_MAX 32 305#define KMAP_MAX 32
320unsigned long kmap_chunks[KMAP_MAX*3]; 306unsigned long kmap_chunks[KMAP_MAX*3];
@@ -574,9 +560,9 @@ static __inline__ void ser_RTSon(void)
574 560
575int __debug_ser_out( unsigned char c ) 561int __debug_ser_out( unsigned char c )
576{ 562{
577 custom.serdat = c | 0x100; 563 amiga_custom.serdat = c | 0x100;
578 mb(); 564 mb();
579 while (!(custom.serdatr & 0x2000)) 565 while (!(amiga_custom.serdatr & 0x2000))
580 barrier(); 566 barrier();
581 return 1; 567 return 1;
582} 568}
@@ -586,11 +572,11 @@ unsigned char __debug_ser_in( void )
586 unsigned char c; 572 unsigned char c;
587 573
588 /* XXX: is that ok?? derived from amiga_ser.c... */ 574 /* XXX: is that ok?? derived from amiga_ser.c... */
589 while( !(custom.intreqr & IF_RBF) ) 575 while( !(amiga_custom.intreqr & IF_RBF) )
590 barrier(); 576 barrier();
591 c = custom.serdatr; 577 c = amiga_custom.serdatr;
592 /* clear the interrupt, so that another character can be read */ 578 /* clear the interrupt, so that another character can be read */
593 custom.intreq = IF_RBF; 579 amiga_custom.intreq = IF_RBF;
594 return c; 580 return c;
595} 581}
596 582
@@ -601,10 +587,10 @@ int __debug_serinit( void )
601 local_irq_save(flags); 587 local_irq_save(flags);
602 588
603 /* turn off Rx and Tx interrupts */ 589 /* turn off Rx and Tx interrupts */
604 custom.intena = IF_RBF | IF_TBE; 590 amiga_custom.intena = IF_RBF | IF_TBE;
605 591
606 /* clear any pending interrupt */ 592 /* clear any pending interrupt */
607 custom.intreq = IF_RBF | IF_TBE; 593 amiga_custom.intreq = IF_RBF | IF_TBE;
608 594
609 local_irq_restore(flags); 595 local_irq_restore(flags);
610 596
@@ -617,7 +603,7 @@ int __debug_serinit( void )
617 603
618#ifdef CONFIG_KGDB 604#ifdef CONFIG_KGDB
619 /* turn Rx interrupts on for GDB */ 605 /* turn Rx interrupts on for GDB */
620 custom.intena = IF_SETCLR | IF_RBF; 606 amiga_custom.intena = IF_SETCLR | IF_RBF;
621 ser_RTSon(); 607 ser_RTSon();
622#endif 608#endif
623 609
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
index bd047aac01..c7fe6182bb 100644
--- a/arch/ppc/platforms/chrp_pci.c
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -275,7 +275,7 @@ chrp_find_bridges(void)
275 setup_python(hose, dev); 275 setup_python(hose, dev);
276 } else if (is_mot 276 } else if (is_mot
277 || strncmp(model, "Motorola, Grackle", 17) == 0) { 277 || strncmp(model, "Motorola, Grackle", 17) == 0) {
278 setup_grackle(hose); 278 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
279 } else if (is_longtrail) { 279 } else if (is_longtrail) {
280 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); 280 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
281 hose->ops = &gg2_pci_ops; 281 hose->ops = &gg2_pci_ops;
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
index f1b70ab3c6..48996b7873 100644
--- a/arch/ppc/platforms/chrp_setup.c
+++ b/arch/ppc/platforms/chrp_setup.c
@@ -53,6 +53,7 @@
53#include <asm/i8259.h> 53#include <asm/i8259.h>
54#include <asm/open_pic.h> 54#include <asm/open_pic.h>
55#include <asm/xmon.h> 55#include <asm/xmon.h>
56#include "mem_pieces.h"
56 57
57unsigned long chrp_get_rtc_time(void); 58unsigned long chrp_get_rtc_time(void);
58int chrp_set_rtc_time(unsigned long nowtime); 59int chrp_set_rtc_time(unsigned long nowtime);
@@ -65,7 +66,6 @@ void rtas_display_progress(char *, unsigned short);
65void rtas_indicator_progress(char *, unsigned short); 66void rtas_indicator_progress(char *, unsigned short);
66void btext_progress(char *, unsigned short); 67void btext_progress(char *, unsigned short);
67 68
68extern unsigned long pmac_find_end_of_memory(void);
69extern int of_show_percpuinfo(struct seq_file *, int); 69extern int of_show_percpuinfo(struct seq_file *, int);
70 70
71int _chrp_type; 71int _chrp_type;
@@ -404,7 +404,6 @@ static struct irqaction xmon_irqaction = {
404void __init chrp_init_IRQ(void) 404void __init chrp_init_IRQ(void)
405{ 405{
406 struct device_node *np; 406 struct device_node *np;
407 int i;
408 unsigned long chrp_int_ack = 0; 407 unsigned long chrp_int_ack = 0;
409 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS]; 408 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
410#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 409#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
@@ -468,6 +467,75 @@ chrp_init2(void)
468 ppc_md.progress(" Have fun! ", 0x7777); 467 ppc_md.progress(" Have fun! ", 0x7777);
469} 468}
470 469
470static struct device_node *memory_node;
471
472static int __init get_mem_prop(char *name, struct mem_pieces *mp)
473{
474 struct reg_property *rp;
475 int i, s;
476 unsigned int *ip;
477 int nac = prom_n_addr_cells(memory_node);
478 int nsc = prom_n_size_cells(memory_node);
479
480 ip = (unsigned int *) get_property(memory_node, name, &s);
481 if (ip == NULL) {
482 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
483 name);
484 return 0;
485 }
486 s /= (nsc + nac) * 4;
487 rp = mp->regions;
488 for (i = 0; i < s; ++i, ip += nac+nsc) {
489 if (nac >= 2 && ip[nac-2] != 0)
490 continue;
491 rp->address = ip[nac-1];
492 if (nsc >= 2 && ip[nac+nsc-2] != 0)
493 rp->size = ~0U;
494 else
495 rp->size = ip[nac+nsc-1];
496 ++rp;
497 }
498 mp->n_regions = rp - mp->regions;
499
500 /* Make sure the pieces are sorted. */
501 mem_pieces_sort(mp);
502 mem_pieces_coalesce(mp);
503 return 1;
504}
505
506static unsigned long __init chrp_find_end_of_memory(void)
507{
508 unsigned long a, total;
509 struct mem_pieces phys_mem;
510
511 /*
512 * Find out where physical memory is, and check that it
513 * starts at 0 and is contiguous. It seems that RAM is
514 * always physically contiguous on Power Macintoshes.
515 *
516 * Supporting discontiguous physical memory isn't hard,
517 * it just makes the virtual <-> physical mapping functions
518 * more complicated (or else you end up wasting space
519 * in mem_map).
520 */
521 memory_node = find_devices("memory");
522 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
523 || phys_mem.n_regions == 0)
524 panic("No RAM??");
525 a = phys_mem.regions[0].address;
526 if (a != 0)
527 panic("RAM doesn't start at physical address 0");
528 total = phys_mem.regions[0].size;
529
530 if (phys_mem.n_regions > 1) {
531 printk("RAM starting at 0x%x is not contiguous\n",
532 phys_mem.regions[1].address);
533 printk("Using RAM from 0 to 0x%lx\n", total-1);
534 }
535
536 return total;
537}
538
471void __init 539void __init
472chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, 540chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
473 unsigned long r6, unsigned long r7) 541 unsigned long r6, unsigned long r7)
@@ -526,7 +594,7 @@ chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
526 ppc_md.get_rtc_time = chrp_get_rtc_time; 594 ppc_md.get_rtc_time = chrp_get_rtc_time;
527 ppc_md.calibrate_decr = chrp_calibrate_decr; 595 ppc_md.calibrate_decr = chrp_calibrate_decr;
528 596
529 ppc_md.find_end_of_memory = pmac_find_end_of_memory; 597 ppc_md.find_end_of_memory = chrp_find_end_of_memory;
530 598
531 if (rtas_data) { 599 if (rtas_data) {
532 struct device_node *rtas; 600 struct device_node *rtas;
diff --git a/arch/ppc/platforms/chrp_time.c b/arch/ppc/platforms/chrp_time.c
index 29d074c305..57753a55b5 100644
--- a/arch/ppc/platforms/chrp_time.c
+++ b/arch/ppc/platforms/chrp_time.c
@@ -163,13 +163,75 @@ unsigned long chrp_get_rtc_time(void)
163 return mktime(year, mon, day, hour, min, sec); 163 return mktime(year, mon, day, hour, min, sec);
164} 164}
165 165
166/*
167 * Calibrate the decrementer frequency with the VIA timer 1.
168 */
169#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
170
171/* VIA registers */
172#define RS 0x200 /* skip between registers */
173#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
174#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
175#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
176#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
177#define ACR (11*RS) /* Auxiliary control register */
178#define IFR (13*RS) /* Interrupt flag register */
179
180/* Bits in ACR */
181#define T1MODE 0xc0 /* Timer 1 mode */
182#define T1MODE_CONT 0x40 /* continuous interrupts */
183
184/* Bits in IFR and IER */
185#define T1_INT 0x40 /* Timer 1 interrupt */
186
187static int __init chrp_via_calibrate_decr(void)
188{
189 struct device_node *vias;
190 volatile unsigned char __iomem *via;
191 int count = VIA_TIMER_FREQ_6 / 100;
192 unsigned int dstart, dend;
193
194 vias = find_devices("via-cuda");
195 if (vias == 0)
196 vias = find_devices("via");
197 if (vias == 0 || vias->n_addrs == 0)
198 return 0;
199 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
200
201 /* set timer 1 for continuous interrupts */
202 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
203 /* set the counter to a small value */
204 out_8(&via[T1CH], 2);
205 /* set the latch to `count' */
206 out_8(&via[T1LL], count);
207 out_8(&via[T1LH], count >> 8);
208 /* wait until it hits 0 */
209 while ((in_8(&via[IFR]) & T1_INT) == 0)
210 ;
211 dstart = get_dec();
212 /* clear the interrupt & wait until it hits 0 again */
213 in_8(&via[T1CL]);
214 while ((in_8(&via[IFR]) & T1_INT) == 0)
215 ;
216 dend = get_dec();
217
218 tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
219 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
220
221 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
222 tb_ticks_per_jiffy, dstart - dend);
223
224 iounmap(via);
225
226 return 1;
227}
166 228
167void __init chrp_calibrate_decr(void) 229void __init chrp_calibrate_decr(void)
168{ 230{
169 struct device_node *cpu; 231 struct device_node *cpu;
170 unsigned int freq, *fp; 232 unsigned int freq, *fp;
171 233
172 if (via_calibrate_decr()) 234 if (chrp_via_calibrate_decr())
173 return; 235 return;
174 236
175 /* 237 /*
diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
index d44cc99117..7ed52dc340 100644
--- a/arch/ppc/platforms/lite5200.c
+++ b/arch/ppc/platforms/lite5200.c
@@ -196,8 +196,10 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
196 mpc52xx_set_bat(); 196 mpc52xx_set_bat();
197 197
198 /* No ISA bus by default */ 198 /* No ISA bus by default */
199#ifdef CONFIG_PCI
199 isa_io_base = 0; 200 isa_io_base = 0;
200 isa_mem_base = 0; 201 isa_mem_base = 0;
202#endif
201 203
202 /* Powersave */ 204 /* Powersave */
203 /* This is provided as an example on how to do it. But you 205 /* This is provided as an example on how to do it. But you
diff --git a/arch/ppc/platforms/mpc5200.c b/arch/ppc/platforms/mpc5200.c
deleted file mode 100644
index a58db438c1..0000000000
--- a/arch/ppc/platforms/mpc5200.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * arch/ppc/platforms/mpc5200.c
3 *
4 * OCP Definitions for the boards based on MPC5200 processor. Contains
5 * definitions for every common peripherals. (Mostly all but PSCs)
6 *
7 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
8 *
9 * Copyright 2004 Sylvain Munaut <tnt@246tNt.com>
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#include <asm/ocp.h>
17#include <asm/mpc52xx.h>
18
19
20static struct ocp_fs_i2c_data mpc5200_i2c_def = {
21 .flags = FS_I2C_CLOCK_5200,
22};
23
24
25/* Here is the core_ocp struct.
26 * With all the devices common to all board. Even if port multiplexing is
27 * not setup for them (if the user don't want them, just don't select the
28 * config option). The potentially conflicting devices (like PSCs) goes in
29 * board specific file.
30 */
31struct ocp_def core_ocp[] = {
32 {
33 .vendor = OCP_VENDOR_FREESCALE,
34 .function = OCP_FUNC_IIC,
35 .index = 0,
36 .paddr = MPC52xx_I2C1,
37 .irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C1 - Buggy */
38 .pm = OCP_CPM_NA,
39 .additions = &mpc5200_i2c_def,
40 },
41 {
42 .vendor = OCP_VENDOR_FREESCALE,
43 .function = OCP_FUNC_IIC,
44 .index = 1,
45 .paddr = MPC52xx_I2C2,
46 .irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C2 - Buggy */
47 .pm = OCP_CPM_NA,
48 .additions = &mpc5200_i2c_def,
49 },
50 { /* Terminating entry */
51 .vendor = OCP_VENDOR_INVALID
52 }
53};
diff --git a/arch/ppc/platforms/pmac_backlight.c b/arch/ppc/platforms/pmac_backlight.c
deleted file mode 100644
index 8be2f7d071..0000000000
--- a/arch/ppc/platforms/pmac_backlight.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/*
2 * Miscellaneous procedures for dealing with the PowerMac hardware.
3 * Contains support for the backlight.
4 *
5 * Copyright (C) 2000 Benjamin Herrenschmidt
6 *
7 */
8
9#include <linux/config.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/stddef.h>
13#include <linux/reboot.h>
14#include <linux/nvram.h>
15#include <linux/console.h>
16#include <asm/sections.h>
17#include <asm/ptrace.h>
18#include <asm/io.h>
19#include <asm/pgtable.h>
20#include <asm/system.h>
21#include <asm/prom.h>
22#include <asm/machdep.h>
23#include <asm/nvram.h>
24#include <asm/backlight.h>
25
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29static struct backlight_controller *backlighter;
30static void* backlighter_data;
31static int backlight_autosave;
32static int backlight_level = BACKLIGHT_MAX;
33static int backlight_enabled = 1;
34static int backlight_req_level = -1;
35static int backlight_req_enable = -1;
36
37static void backlight_callback(void *);
38static DECLARE_WORK(backlight_work, backlight_callback, NULL);
39
40void register_backlight_controller(struct backlight_controller *ctrler,
41 void *data, char *type)
42{
43 struct device_node* bk_node;
44 char *prop;
45 int valid = 0;
46
47 /* There's already a matching controller, bail out */
48 if (backlighter != NULL)
49 return;
50
51 bk_node = find_devices("backlight");
52
53#ifdef CONFIG_ADB_PMU
54 /* Special case for the old PowerBook since I can't test on it */
55 backlight_autosave = machine_is_compatible("AAPL,3400/2400")
56 || machine_is_compatible("AAPL,3500");
57 if ((backlight_autosave
58 || machine_is_compatible("AAPL,PowerBook1998")
59 || machine_is_compatible("PowerBook1,1"))
60 && !strcmp(type, "pmu"))
61 valid = 1;
62#endif
63 if (bk_node) {
64 prop = get_property(bk_node, "backlight-control", NULL);
65 if (prop && !strncmp(prop, type, strlen(type)))
66 valid = 1;
67 }
68 if (!valid)
69 return;
70 backlighter = ctrler;
71 backlighter_data = data;
72
73 if (bk_node && !backlight_autosave)
74 prop = get_property(bk_node, "bklt", NULL);
75 else
76 prop = NULL;
77 if (prop) {
78 backlight_level = ((*prop)+1) >> 1;
79 if (backlight_level > BACKLIGHT_MAX)
80 backlight_level = BACKLIGHT_MAX;
81 }
82
83#ifdef CONFIG_ADB_PMU
84 if (backlight_autosave) {
85 struct adb_request req;
86 pmu_request(&req, NULL, 2, 0xd9, 0);
87 while (!req.complete)
88 pmu_poll();
89 backlight_level = req.reply[0] >> 4;
90 }
91#endif
92 acquire_console_sem();
93 if (!backlighter->set_enable(1, backlight_level, data))
94 backlight_enabled = 1;
95 release_console_sem();
96
97 printk(KERN_INFO "Registered \"%s\" backlight controller,"
98 "level: %d/15\n", type, backlight_level);
99}
100EXPORT_SYMBOL(register_backlight_controller);
101
102void unregister_backlight_controller(struct backlight_controller
103 *ctrler, void *data)
104{
105 /* We keep the current backlight level (for now) */
106 if (ctrler == backlighter && data == backlighter_data)
107 backlighter = NULL;
108}
109EXPORT_SYMBOL(unregister_backlight_controller);
110
111static int __set_backlight_enable(int enable)
112{
113 int rc;
114
115 if (!backlighter)
116 return -ENODEV;
117 acquire_console_sem();
118 rc = backlighter->set_enable(enable, backlight_level,
119 backlighter_data);
120 if (!rc)
121 backlight_enabled = enable;
122 release_console_sem();
123 return rc;
124}
125int set_backlight_enable(int enable)
126{
127 if (!backlighter)
128 return -ENODEV;
129 backlight_req_enable = enable;
130 schedule_work(&backlight_work);
131 return 0;
132}
133
134EXPORT_SYMBOL(set_backlight_enable);
135
136int get_backlight_enable(void)
137{
138 if (!backlighter)
139 return -ENODEV;
140 return backlight_enabled;
141}
142EXPORT_SYMBOL(get_backlight_enable);
143
144static int __set_backlight_level(int level)
145{
146 int rc = 0;
147
148 if (!backlighter)
149 return -ENODEV;
150 if (level < BACKLIGHT_MIN)
151 level = BACKLIGHT_OFF;
152 if (level > BACKLIGHT_MAX)
153 level = BACKLIGHT_MAX;
154 acquire_console_sem();
155 if (backlight_enabled)
156 rc = backlighter->set_level(level, backlighter_data);
157 if (!rc)
158 backlight_level = level;
159 release_console_sem();
160 if (!rc && !backlight_autosave) {
161 level <<=1;
162 if (level & 0x10)
163 level |= 0x01;
164 // -- todo: save to property "bklt"
165 }
166 return rc;
167}
168int set_backlight_level(int level)
169{
170 if (!backlighter)
171 return -ENODEV;
172 backlight_req_level = level;
173 schedule_work(&backlight_work);
174 return 0;
175}
176
177EXPORT_SYMBOL(set_backlight_level);
178
179int get_backlight_level(void)
180{
181 if (!backlighter)
182 return -ENODEV;
183 return backlight_level;
184}
185EXPORT_SYMBOL(get_backlight_level);
186
187static void backlight_callback(void *dummy)
188{
189 int level, enable;
190
191 do {
192 level = backlight_req_level;
193 enable = backlight_req_enable;
194 mb();
195
196 if (level >= 0)
197 __set_backlight_level(level);
198 if (enable >= 0)
199 __set_backlight_enable(enable);
200 } while(cmpxchg(&backlight_req_level, level, -1) != level ||
201 cmpxchg(&backlight_req_enable, enable, -1) != enable);
202}
diff --git a/arch/ppc/platforms/pmac_cache.S b/arch/ppc/platforms/pmac_cache.S
deleted file mode 100644
index fb977de6b7..0000000000
--- a/arch/ppc/platforms/pmac_cache.S
+++ /dev/null
@@ -1,359 +0,0 @@
1/*
2 * This file contains low-level cache management functions
3 * used for sleep and CPU speed changes on Apple machines.
4 * (In fact the only thing that is Apple-specific is that we assume
5 * that we can read from ROM at physical address 0xfff00000.)
6 *
7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
8 * Benjamin Herrenschmidt (benh@kernel.crashing.org)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
16
17#include <linux/config.h>
18#include <asm/processor.h>
19#include <asm/ppc_asm.h>
20#include <asm/cputable.h>
21
22/*
23 * Flush and disable all data caches (dL1, L2, L3). This is used
24 * when going to sleep, when doing a PMU based cpufreq transition,
25 * or when "offlining" a CPU on SMP machines. This code is over
26 * paranoid, but I've had enough issues with various CPU revs and
27 * bugs that I decided it was worth beeing over cautious
28 */
29
30_GLOBAL(flush_disable_caches)
31#ifndef CONFIG_6xx
32 blr
33#else
34BEGIN_FTR_SECTION
35 b flush_disable_745x
36END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
37BEGIN_FTR_SECTION
38 b flush_disable_75x
39END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
40 b __flush_disable_L1
41
42/* This is the code for G3 and 74[01]0 */
43flush_disable_75x:
44 mflr r10
45
46 /* Turn off EE and DR in MSR */
47 mfmsr r11
48 rlwinm r0,r11,0,~MSR_EE
49 rlwinm r0,r0,0,~MSR_DR
50 sync
51 mtmsr r0
52 isync
53
54 /* Stop DST streams */
55BEGIN_FTR_SECTION
56 DSSALL
57 sync
58END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
59
60 /* Stop DPM */
61 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
62 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
63 sync
64 mtspr SPRN_HID0,r4 /* Disable DPM */
65 sync
66
67 /* Disp-flush L1. We have a weird problem here that I never
68 * totally figured out. On 750FX, using the ROM for the flush
69 * results in a non-working flush. We use that workaround for
70 * now until I finally understand what's going on. --BenH
71 */
72
73 /* ROM base by default */
74 lis r4,0xfff0
75 mfpvr r3
76 srwi r3,r3,16
77 cmplwi cr0,r3,0x7000
78 bne+ 1f
79 /* RAM base on 750FX */
80 li r4,0
811: li r4,0x4000
82 mtctr r4
831: lwz r0,0(r4)
84 addi r4,r4,32
85 bdnz 1b
86 sync
87 isync
88
89 /* Disable / invalidate / enable L1 data */
90 mfspr r3,SPRN_HID0
91 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
92 mtspr SPRN_HID0,r3
93 sync
94 isync
95 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
96 sync
97 isync
98 mtspr SPRN_HID0,r3
99 xori r3,r3,(HID0_DCI|HID0_ICFI)
100 mtspr SPRN_HID0,r3
101 sync
102
103 /* Get the current enable bit of the L2CR into r4 */
104 mfspr r5,SPRN_L2CR
105 /* Set to data-only (pre-745x bit) */
106 oris r3,r5,L2CR_L2DO@h
107 b 2f
108 /* When disabling L2, code must be in L1 */
109 .balign 32
1101: mtspr SPRN_L2CR,r3
1113: sync
112 isync
113 b 1f
1142: b 3f
1153: sync
116 isync
117 b 1b
1181: /* disp-flush L2. The interesting thing here is that the L2 can be
119 * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
120 * but that is probbaly fine. We disp-flush over 4Mb to be safe
121 */
122 lis r4,2
123 mtctr r4
124 lis r4,0xfff0
1251: lwz r0,0(r4)
126 addi r4,r4,32
127 bdnz 1b
128 sync
129 isync
130 lis r4,2
131 mtctr r4
132 lis r4,0xfff0
1331: dcbf 0,r4
134 addi r4,r4,32
135 bdnz 1b
136 sync
137 isync
138
139 /* now disable L2 */
140 rlwinm r5,r5,0,~L2CR_L2E
141 b 2f
142 /* When disabling L2, code must be in L1 */
143 .balign 32
1441: mtspr SPRN_L2CR,r5
1453: sync
146 isync
147 b 1f
1482: b 3f
1493: sync
150 isync
151 b 1b
1521: sync
153 isync
154 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
155 oris r4,r5,L2CR_L2I@h
156 mtspr SPRN_L2CR,r4
157 sync
158 isync
159
160 /* Wait for the invalidation to complete */
1611: mfspr r3,SPRN_L2CR
162 rlwinm. r0,r3,0,31,31
163 bne 1b
164
165 /* Clear L2I */
166 xoris r4,r4,L2CR_L2I@h
167 sync
168 mtspr SPRN_L2CR,r4
169 sync
170
171 /* now disable the L1 data cache */
172 mfspr r0,SPRN_HID0
173 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
174 mtspr SPRN_HID0,r0
175 sync
176 isync
177
178 /* Restore HID0[DPM] to whatever it was before */
179 sync
180 mfspr r0,SPRN_HID0
181 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
182 mtspr SPRN_HID0,r0
183 sync
184
185 /* restore DR and EE */
186 sync
187 mtmsr r11
188 isync
189
190 mtlr r10
191 blr
192
193/* This code is for 745x processors */
194flush_disable_745x:
195 /* Turn off EE and DR in MSR */
196 mfmsr r11
197 rlwinm r0,r11,0,~MSR_EE
198 rlwinm r0,r0,0,~MSR_DR
199 sync
200 mtmsr r0
201 isync
202
203 /* Stop prefetch streams */
204 DSSALL
205 sync
206
207 /* Disable L2 prefetching */
208 mfspr r0,SPRN_MSSCR0
209 rlwinm r0,r0,0,0,29
210 mtspr SPRN_MSSCR0,r0
211 sync
212 isync
213 lis r4,0
214 dcbf 0,r4
215 dcbf 0,r4
216 dcbf 0,r4
217 dcbf 0,r4
218 dcbf 0,r4
219 dcbf 0,r4
220 dcbf 0,r4
221 dcbf 0,r4
222
223 /* Due to a bug with the HW flush on some CPU revs, we occasionally
224 * experience data corruption. I'm adding a displacement flush along
225 * with a dcbf loop over a few Mb to "help". The problem isn't totally
226 * fixed by this in theory, but at least, in practice, I couldn't reproduce
227 * it even with a big hammer...
228 */
229
230 lis r4,0x0002
231 mtctr r4
232 li r4,0
2331:
234 lwz r0,0(r4)
235 addi r4,r4,32 /* Go to start of next cache line */
236 bdnz 1b
237 isync
238
239 /* Now, flush the first 4MB of memory */
240 lis r4,0x0002
241 mtctr r4
242 li r4,0
243 sync
2441:
245 dcbf 0,r4
246 addi r4,r4,32 /* Go to start of next cache line */
247 bdnz 1b
248
249 /* Flush and disable the L1 data cache */
250 mfspr r6,SPRN_LDSTCR
251 lis r3,0xfff0 /* read from ROM for displacement flush */
252 li r4,0xfe /* start with only way 0 unlocked */
253 li r5,128 /* 128 lines in each way */
2541: mtctr r5
255 rlwimi r6,r4,0,24,31
256 mtspr SPRN_LDSTCR,r6
257 sync
258 isync
2592: lwz r0,0(r3) /* touch each cache line */
260 addi r3,r3,32
261 bdnz 2b
262 rlwinm r4,r4,1,24,30 /* move on to the next way */
263 ori r4,r4,1
264 cmpwi r4,0xff /* all done? */
265 bne 1b
266 /* now unlock the L1 data cache */
267 li r4,0
268 rlwimi r6,r4,0,24,31
269 sync
270 mtspr SPRN_LDSTCR,r6
271 sync
272 isync
273
274 /* Flush the L2 cache using the hardware assist */
275 mfspr r3,SPRN_L2CR
276 cmpwi r3,0 /* check if it is enabled first */
277 bge 4f
278 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
279 b 2f
280 /* When disabling/locking L2, code must be in L1 */
281 .balign 32
2821: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
2833: sync
284 isync
285 b 1f
2862: b 3f
2873: sync
288 isync
289 b 1b
2901: sync
291 isync
292 ori r0,r3,L2CR_L2HWF_745x
293 sync
294 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
2953: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
296 andi. r0,r0,L2CR_L2HWF_745x
297 bne 3b
298 sync
299 rlwinm r3,r3,0,~L2CR_L2E
300 b 2f
301 /* When disabling L2, code must be in L1 */
302 .balign 32
3031: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
3043: sync
305 isync
306 b 1f
3072: b 3f
3083: sync
309 isync
310 b 1b
3111: sync
312 isync
313 oris r4,r3,L2CR_L2I@h
314 mtspr SPRN_L2CR,r4
315 sync
316 isync
3171: mfspr r4,SPRN_L2CR
318 andis. r0,r4,L2CR_L2I@h
319 bne 1b
320 sync
321
322BEGIN_FTR_SECTION
323 /* Flush the L3 cache using the hardware assist */
3244: mfspr r3,SPRN_L3CR
325 cmpwi r3,0 /* check if it is enabled */
326 bge 6f
327 oris r0,r3,L3CR_L3IO@h
328 ori r0,r0,L3CR_L3DO
329 sync
330 mtspr SPRN_L3CR,r0 /* lock the L3 cache */
331 sync
332 isync
333 ori r0,r0,L3CR_L3HWF
334 sync
335 mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
3365: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
337 andi. r0,r0,L3CR_L3HWF
338 bne 5b
339 rlwinm r3,r3,0,~L3CR_L3E
340 sync
341 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
342 sync
343 ori r4,r3,L3CR_L3I
344 mtspr SPRN_L3CR,r4
3451: mfspr r4,SPRN_L3CR
346 andi. r0,r4,L3CR_L3I
347 bne 1b
348 sync
349END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
350
3516: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
352 rlwinm r0,r0,0,~HID0_DCE
353 mtspr SPRN_HID0,r0
354 sync
355 isync
356 mtmsr r11 /* restore DR and EE */
357 isync
358 blr
359#endif /* CONFIG_6xx */
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
deleted file mode 100644
index fba7e4d7c0..0000000000
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ /dev/null
@@ -1,735 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_cpufreq.c
3 *
4 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright (C) 2004 John Steele Scott <toojays@toojays.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * TODO: Need a big cleanup here. Basically, we need to have different
12 * cpufreq_driver structures for the different type of HW instead of the
13 * current mess. We also need to better deal with the detection of the
14 * type of machine.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/sched.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <linux/slab.h>
28#include <linux/cpufreq.h>
29#include <linux/init.h>
30#include <linux/sysdev.h>
31#include <linux/i2c.h>
32#include <linux/hardirq.h>
33#include <asm/prom.h>
34#include <asm/machdep.h>
35#include <asm/irq.h>
36#include <asm/pmac_feature.h>
37#include <asm/mmu_context.h>
38#include <asm/sections.h>
39#include <asm/cputable.h>
40#include <asm/time.h>
41#include <asm/system.h>
42#include <asm/open_pic.h>
43#include <asm/keylargo.h>
44
45/* WARNING !!! This will cause calibrate_delay() to be called,
46 * but this is an __init function ! So you MUST go edit
47 * init/main.c to make it non-init before enabling DEBUG_FREQ
48 */
49#undef DEBUG_FREQ
50
51/*
52 * There is a problem with the core cpufreq code on SMP kernels,
53 * it won't recalculate the Bogomips properly
54 */
55#ifdef CONFIG_SMP
56#warning "WARNING, CPUFREQ not recommended on SMP kernels"
57#endif
58
59extern void low_choose_7447a_dfs(int dfs);
60extern void low_choose_750fx_pll(int pll);
61extern void low_sleep_handler(void);
62
63/*
64 * Currently, PowerMac cpufreq supports only high & low frequencies
65 * that are set by the firmware
66 */
67static unsigned int low_freq;
68static unsigned int hi_freq;
69static unsigned int cur_freq;
70static unsigned int sleep_freq;
71
72/*
73 * Different models uses different mecanisms to switch the frequency
74 */
75static int (*set_speed_proc)(int low_speed);
76static unsigned int (*get_speed_proc)(void);
77
78/*
79 * Some definitions used by the various speedprocs
80 */
81static u32 voltage_gpio;
82static u32 frequency_gpio;
83static u32 slew_done_gpio;
84static int no_schedule;
85static int has_cpu_l2lve;
86static int is_pmu_based;
87
88/* There are only two frequency states for each processor. Values
89 * are in kHz for the time being.
90 */
91#define CPUFREQ_HIGH 0
92#define CPUFREQ_LOW 1
93
94static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
95 {CPUFREQ_HIGH, 0},
96 {CPUFREQ_LOW, 0},
97 {0, CPUFREQ_TABLE_END},
98};
99
100static struct freq_attr* pmac_cpu_freqs_attr[] = {
101 &cpufreq_freq_attr_scaling_available_freqs,
102 NULL,
103};
104
105static inline void local_delay(unsigned long ms)
106{
107 if (no_schedule)
108 mdelay(ms);
109 else
110 msleep(ms);
111}
112
113static inline void wakeup_decrementer(void)
114{
115 set_dec(tb_ticks_per_jiffy);
116 /* No currently-supported powerbook has a 601,
117 * so use get_tbl, not native
118 */
119 last_jiffy_stamp(0) = tb_last_stamp = get_tbl();
120}
121
122#ifdef DEBUG_FREQ
123static inline void debug_calc_bogomips(void)
124{
125 /* This will cause a recalc of bogomips and display the
126 * result. We backup/restore the value to avoid affecting the
127 * core cpufreq framework's own calculation.
128 */
129 extern void calibrate_delay(void);
130
131 unsigned long save_lpj = loops_per_jiffy;
132 calibrate_delay();
133 loops_per_jiffy = save_lpj;
134}
135#endif /* DEBUG_FREQ */
136
137/* Switch CPU speed under 750FX CPU control
138 */
139static int cpu_750fx_cpu_speed(int low_speed)
140{
141 u32 hid2;
142
143 if (low_speed == 0) {
144 /* ramping up, set voltage first */
145 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
146 /* Make sure we sleep for at least 1ms */
147 local_delay(10);
148
149 /* tweak L2 for high voltage */
150 if (has_cpu_l2lve) {
151 hid2 = mfspr(SPRN_HID2);
152 hid2 &= ~0x2000;
153 mtspr(SPRN_HID2, hid2);
154 }
155 }
156#ifdef CONFIG_6xx
157 low_choose_750fx_pll(low_speed);
158#endif
159 if (low_speed == 1) {
160 /* tweak L2 for low voltage */
161 if (has_cpu_l2lve) {
162 hid2 = mfspr(SPRN_HID2);
163 hid2 |= 0x2000;
164 mtspr(SPRN_HID2, hid2);
165 }
166
167 /* ramping down, set voltage last */
168 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
169 local_delay(10);
170 }
171
172 return 0;
173}
174
175static unsigned int cpu_750fx_get_cpu_speed(void)
176{
177 if (mfspr(SPRN_HID1) & HID1_PS)
178 return low_freq;
179 else
180 return hi_freq;
181}
182
183/* Switch CPU speed using DFS */
184static int dfs_set_cpu_speed(int low_speed)
185{
186 if (low_speed == 0) {
187 /* ramping up, set voltage first */
188 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
189 /* Make sure we sleep for at least 1ms */
190 local_delay(1);
191 }
192
193 /* set frequency */
194#ifdef CONFIG_6xx
195 low_choose_7447a_dfs(low_speed);
196#endif
197 udelay(100);
198
199 if (low_speed == 1) {
200 /* ramping down, set voltage last */
201 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
202 local_delay(1);
203 }
204
205 return 0;
206}
207
208static unsigned int dfs_get_cpu_speed(void)
209{
210 if (mfspr(SPRN_HID1) & HID1_DFS)
211 return low_freq;
212 else
213 return hi_freq;
214}
215
216
217/* Switch CPU speed using slewing GPIOs
218 */
219static int gpios_set_cpu_speed(int low_speed)
220{
221 int gpio, timeout = 0;
222
223 /* If ramping up, set voltage first */
224 if (low_speed == 0) {
225 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
226 /* Delay is way too big but it's ok, we schedule */
227 local_delay(10);
228 }
229
230 /* Set frequency */
231 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
232 if (low_speed == ((gpio & 0x01) == 0))
233 goto skip;
234
235 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
236 low_speed ? 0x04 : 0x05);
237 udelay(200);
238 do {
239 if (++timeout > 100)
240 break;
241 local_delay(1);
242 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
243 } while((gpio & 0x02) == 0);
244 skip:
245 /* If ramping down, set voltage last */
246 if (low_speed == 1) {
247 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
248 /* Delay is way too big but it's ok, we schedule */
249 local_delay(10);
250 }
251
252#ifdef DEBUG_FREQ
253 debug_calc_bogomips();
254#endif
255
256 return 0;
257}
258
259/* Switch CPU speed under PMU control
260 */
261static int pmu_set_cpu_speed(int low_speed)
262{
263 struct adb_request req;
264 unsigned long save_l2cr;
265 unsigned long save_l3cr;
266 unsigned int pic_prio;
267 unsigned long flags;
268
269 preempt_disable();
270
271#ifdef DEBUG_FREQ
272 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
273#endif
274 pmu_suspend();
275
276 /* Disable all interrupt sources on openpic */
277 pic_prio = openpic_get_priority();
278 openpic_set_priority(0xf);
279
280 /* Make sure the decrementer won't interrupt us */
281 asm volatile("mtdec %0" : : "r" (0x7fffffff));
282 /* Make sure any pending DEC interrupt occuring while we did
283 * the above didn't re-enable the DEC */
284 mb();
285 asm volatile("mtdec %0" : : "r" (0x7fffffff));
286
287 /* We can now disable MSR_EE */
288 local_irq_save(flags);
289
290 /* Giveup the FPU & vec */
291 enable_kernel_fp();
292
293#ifdef CONFIG_ALTIVEC
294 if (cpu_has_feature(CPU_FTR_ALTIVEC))
295 enable_kernel_altivec();
296#endif /* CONFIG_ALTIVEC */
297
298 /* Save & disable L2 and L3 caches */
299 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
300 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
301
302 /* Send the new speed command. My assumption is that this command
303 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
304 */
305 pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
306 while (!req.complete)
307 pmu_poll();
308
309 /* Prepare the northbridge for the speed transition */
310 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
311
312 /* Call low level code to backup CPU state and recover from
313 * hardware reset
314 */
315 low_sleep_handler();
316
317 /* Restore the northbridge */
318 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
319
320 /* Restore L2 cache */
321 if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
322 _set_L2CR(save_l2cr);
323 /* Restore L3 cache */
324 if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
325 _set_L3CR(save_l3cr);
326
327 /* Restore userland MMU context */
328 set_context(current->active_mm->context, current->active_mm->pgd);
329
330#ifdef DEBUG_FREQ
331 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
332#endif
333
334 /* Restore low level PMU operations */
335 pmu_unlock();
336
337 /* Restore decrementer */
338 wakeup_decrementer();
339
340 /* Restore interrupts */
341 openpic_set_priority(pic_prio);
342
343 /* Let interrupts flow again ... */
344 local_irq_restore(flags);
345
346#ifdef DEBUG_FREQ
347 debug_calc_bogomips();
348#endif
349
350 pmu_resume();
351
352 preempt_enable();
353
354 return 0;
355}
356
357static int do_set_cpu_speed(int speed_mode, int notify)
358{
359 struct cpufreq_freqs freqs;
360 unsigned long l3cr;
361 static unsigned long prev_l3cr;
362
363 freqs.old = cur_freq;
364 freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
365 freqs.cpu = smp_processor_id();
366
367 if (freqs.old == freqs.new)
368 return 0;
369
370 if (notify)
371 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
372 if (speed_mode == CPUFREQ_LOW &&
373 cpu_has_feature(CPU_FTR_L3CR)) {
374 l3cr = _get_L3CR();
375 if (l3cr & L3CR_L3E) {
376 prev_l3cr = l3cr;
377 _set_L3CR(0);
378 }
379 }
380 set_speed_proc(speed_mode == CPUFREQ_LOW);
381 if (speed_mode == CPUFREQ_HIGH &&
382 cpu_has_feature(CPU_FTR_L3CR)) {
383 l3cr = _get_L3CR();
384 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
385 _set_L3CR(prev_l3cr);
386 }
387 if (notify)
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
390
391 return 0;
392}
393
394static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
395{
396 return cur_freq;
397}
398
399static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
400{
401 return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
402}
403
404static int pmac_cpufreq_target( struct cpufreq_policy *policy,
405 unsigned int target_freq,
406 unsigned int relation)
407{
408 unsigned int newstate = 0;
409
410 if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
411 target_freq, relation, &newstate))
412 return -EINVAL;
413
414 return do_set_cpu_speed(newstate, 1);
415}
416
417unsigned int pmac_get_one_cpufreq(int i)
418{
419 /* Supports only one CPU for now */
420 return (i == 0) ? cur_freq : 0;
421}
422
423static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
424{
425 if (policy->cpu != 0)
426 return -ENODEV;
427
428 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
429 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
430 policy->cur = cur_freq;
431
432 cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
433 return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
434}
435
436static u32 read_gpio(struct device_node *np)
437{
438 u32 *reg = (u32 *)get_property(np, "reg", NULL);
439 u32 offset;
440
441 if (reg == NULL)
442 return 0;
443 /* That works for all keylargos but shall be fixed properly
444 * some day... The problem is that it seems we can't rely
445 * on the "reg" property of the GPIO nodes, they are either
446 * relative to the base of KeyLargo or to the base of the
447 * GPIO space, and the device-tree doesn't help.
448 */
449 offset = *reg;
450 if (offset < KEYLARGO_GPIO_LEVELS0)
451 offset += KEYLARGO_GPIO_LEVELS0;
452 return offset;
453}
454
455static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
456{
457 /* Ok, this could be made a bit smarter, but let's be robust for now. We
458 * always force a speed change to high speed before sleep, to make sure
459 * we have appropriate voltage and/or bus speed for the wakeup process,
460 * and to make sure our loops_per_jiffies are "good enough", that is will
461 * not cause too short delays if we sleep in low speed and wake in high
462 * speed..
463 */
464 no_schedule = 1;
465 sleep_freq = cur_freq;
466 if (cur_freq == low_freq && !is_pmu_based)
467 do_set_cpu_speed(CPUFREQ_HIGH, 0);
468 return 0;
469}
470
471static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
472{
473 /* If we resume, first check if we have a get() function */
474 if (get_speed_proc)
475 cur_freq = get_speed_proc();
476 else
477 cur_freq = 0;
478
479 /* We don't, hrm... we don't really know our speed here, best
480 * is that we force a switch to whatever it was, which is
481 * probably high speed due to our suspend() routine
482 */
483 do_set_cpu_speed(sleep_freq == low_freq ?
484 CPUFREQ_LOW : CPUFREQ_HIGH, 0);
485
486 no_schedule = 0;
487 return 0;
488}
489
490static struct cpufreq_driver pmac_cpufreq_driver = {
491 .verify = pmac_cpufreq_verify,
492 .target = pmac_cpufreq_target,
493 .get = pmac_cpufreq_get_speed,
494 .init = pmac_cpufreq_cpu_init,
495 .suspend = pmac_cpufreq_suspend,
496 .resume = pmac_cpufreq_resume,
497 .flags = CPUFREQ_PM_NO_WARN,
498 .attr = pmac_cpu_freqs_attr,
499 .name = "powermac",
500 .owner = THIS_MODULE,
501};
502
503
504static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
505{
506 struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
507 "voltage-gpio");
508 struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
509 "frequency-gpio");
510 struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
511 "slewing-done");
512 u32 *value;
513
514 /*
515 * Check to see if it's GPIO driven or PMU only
516 *
517 * The way we extract the GPIO address is slightly hackish, but it
518 * works well enough for now. We need to abstract the whole GPIO
519 * stuff sooner or later anyway
520 */
521
522 if (volt_gpio_np)
523 voltage_gpio = read_gpio(volt_gpio_np);
524 if (freq_gpio_np)
525 frequency_gpio = read_gpio(freq_gpio_np);
526 if (slew_done_gpio_np)
527 slew_done_gpio = read_gpio(slew_done_gpio_np);
528
529 /* If we use the frequency GPIOs, calculate the min/max speeds based
530 * on the bus frequencies
531 */
532 if (frequency_gpio && slew_done_gpio) {
533 int lenp, rc;
534 u32 *freqs, *ratio;
535
536 freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp);
537 lenp /= sizeof(u32);
538 if (freqs == NULL || lenp != 2) {
539 printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
540 return 1;
541 }
542 ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL);
543 if (ratio == NULL) {
544 printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
545 return 1;
546 }
547
548 /* Get the min/max bus frequencies */
549 low_freq = min(freqs[0], freqs[1]);
550 hi_freq = max(freqs[0], freqs[1]);
551
552 /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
553 * frequency, it claims it to be around 84Mhz on some models while
554 * it appears to be approx. 101Mhz on all. Let's hack around here...
555 * fortunately, we don't need to be too precise
556 */
557 if (low_freq < 98000000)
558 low_freq = 101000000;
559
560 /* Convert those to CPU core clocks */
561 low_freq = (low_freq * (*ratio)) / 2000;
562 hi_freq = (hi_freq * (*ratio)) / 2000;
563
564 /* Now we get the frequencies, we read the GPIO to see what is out current
565 * speed
566 */
567 rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
568 cur_freq = (rc & 0x01) ? hi_freq : low_freq;
569
570 set_speed_proc = gpios_set_cpu_speed;
571 return 1;
572 }
573
574 /* If we use the PMU, look for the min & max frequencies in the
575 * device-tree
576 */
577 value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
578 if (!value)
579 return 1;
580 low_freq = (*value) / 1000;
581 /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
582 * here */
583 if (low_freq < 100000)
584 low_freq *= 10;
585
586 value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
587 if (!value)
588 return 1;
589 hi_freq = (*value) / 1000;
590 set_speed_proc = pmu_set_cpu_speed;
591 is_pmu_based = 1;
592
593 return 0;
594}
595
596static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
597{
598 struct device_node *volt_gpio_np;
599
600 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
601 return 1;
602
603 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
604 if (volt_gpio_np)
605 voltage_gpio = read_gpio(volt_gpio_np);
606 if (!voltage_gpio){
607 printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
608 return 1;
609 }
610
611 /* OF only reports the high frequency */
612 hi_freq = cur_freq;
613 low_freq = cur_freq/2;
614
615 /* Read actual frequency from CPU */
616 cur_freq = dfs_get_cpu_speed();
617 set_speed_proc = dfs_set_cpu_speed;
618 get_speed_proc = dfs_get_cpu_speed;
619
620 return 0;
621}
622
623static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
624{
625 struct device_node *volt_gpio_np;
626 u32 pvr, *value;
627
628 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
629 return 1;
630
631 hi_freq = cur_freq;
632 value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
633 if (!value)
634 return 1;
635 low_freq = (*value) / 1000;
636
637 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
638 if (volt_gpio_np)
639 voltage_gpio = read_gpio(volt_gpio_np);
640
641 pvr = mfspr(SPRN_PVR);
642 has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
643
644 set_speed_proc = cpu_750fx_cpu_speed;
645 get_speed_proc = cpu_750fx_get_cpu_speed;
646 cur_freq = cpu_750fx_get_cpu_speed();
647
648 return 0;
649}
650
651/* Currently, we support the following machines:
652 *
653 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
654 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
655 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
656 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
657 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
658 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
659 * - Recent MacRISC3 laptops
660 * - All new machines with 7447A CPUs
661 */
662static int __init pmac_cpufreq_setup(void)
663{
664 struct device_node *cpunode;
665 u32 *value;
666
667 if (strstr(cmd_line, "nocpufreq"))
668 return 0;
669
670 /* Assume only one CPU */
671 cpunode = find_type_devices("cpu");
672 if (!cpunode)
673 goto out;
674
675 /* Get current cpu clock freq */
676 value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
677 if (!value)
678 goto out;
679 cur_freq = (*value) / 1000;
680
681 /* Check for 7447A based MacRISC3 */
682 if (machine_is_compatible("MacRISC3") &&
683 get_property(cpunode, "dynamic-power-step", NULL) &&
684 PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
685 pmac_cpufreq_init_7447A(cpunode);
686 /* Check for other MacRISC3 machines */
687 } else if (machine_is_compatible("PowerBook3,4") ||
688 machine_is_compatible("PowerBook3,5") ||
689 machine_is_compatible("MacRISC3")) {
690 pmac_cpufreq_init_MacRISC3(cpunode);
691 /* Else check for iBook2 500/600 */
692 } else if (machine_is_compatible("PowerBook4,1")) {
693 hi_freq = cur_freq;
694 low_freq = 400000;
695 set_speed_proc = pmu_set_cpu_speed;
696 is_pmu_based = 1;
697 }
698 /* Else check for TiPb 550 */
699 else if (machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
700 hi_freq = cur_freq;
701 low_freq = 500000;
702 set_speed_proc = pmu_set_cpu_speed;
703 is_pmu_based = 1;
704 }
705 /* Else check for TiPb 400 & 500 */
706 else if (machine_is_compatible("PowerBook3,2")) {
707 /* We only know about the 400 MHz and the 500Mhz model
708 * they both have 300 MHz as low frequency
709 */
710 if (cur_freq < 350000 || cur_freq > 550000)
711 goto out;
712 hi_freq = cur_freq;
713 low_freq = 300000;
714 set_speed_proc = pmu_set_cpu_speed;
715 is_pmu_based = 1;
716 }
717 /* Else check for 750FX */
718 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
719 pmac_cpufreq_init_750FX(cpunode);
720out:
721 if (set_speed_proc == NULL)
722 return -ENODEV;
723
724 pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
725 pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
726
727 printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
728 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
729 low_freq/1000, hi_freq/1000, cur_freq/1000);
730
731 return cpufreq_register_driver(&pmac_cpufreq_driver);
732}
733
734module_init(pmac_cpufreq_setup);
735
diff --git a/arch/ppc/platforms/pmac_feature.c b/arch/ppc/platforms/pmac_feature.c
deleted file mode 100644
index 58884a63eb..0000000000
--- a/arch/ppc/platforms/pmac_feature.c
+++ /dev/null
@@ -1,3005 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_feature.c
3 *
4 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
5 * Ben. Herrenschmidt (benh@kernel.crashing.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * TODO:
13 *
14 * - Replace mdelay with some schedule loop if possible
15 * - Shorten some obfuscated delays on some routines (like modem
16 * power)
17 * - Refcount some clocks (see darwin)
18 * - Split split split...
19 *
20 */
21#include <linux/config.h>
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/adb.h>
29#include <linux/pmu.h>
30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <asm/sections.h>
33#include <asm/errno.h>
34#include <asm/ohare.h>
35#include <asm/heathrow.h>
36#include <asm/keylargo.h>
37#include <asm/uninorth.h>
38#include <asm/io.h>
39#include <asm/prom.h>
40#include <asm/machdep.h>
41#include <asm/pmac_feature.h>
42#include <asm/dbdma.h>
43#include <asm/pci-bridge.h>
44#include <asm/pmac_low_i2c.h>
45
46#undef DEBUG_FEATURE
47
48#ifdef DEBUG_FEATURE
49#define DBG(fmt,...) printk(KERN_DEBUG fmt)
50#else
51#define DBG(fmt,...)
52#endif
53
54#ifdef CONFIG_6xx
55extern int powersave_lowspeed;
56#endif
57
58extern int powersave_nap;
59extern struct device_node *k2_skiplist[2];
60
61
62/*
63 * We use a single global lock to protect accesses. Each driver has
64 * to take care of its own locking
65 */
66static DEFINE_SPINLOCK(feature_lock);
67
68#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
69#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
70
71
72/*
73 * Instance of some macio stuffs
74 */
75struct macio_chip macio_chips[MAX_MACIO_CHIPS];
76
77struct macio_chip* macio_find(struct device_node* child, int type)
78{
79 while(child) {
80 int i;
81
82 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
83 if (child == macio_chips[i].of_node &&
84 (!type || macio_chips[i].type == type))
85 return &macio_chips[i];
86 child = child->parent;
87 }
88 return NULL;
89}
90EXPORT_SYMBOL_GPL(macio_find);
91
92static const char* macio_names[] =
93{
94 "Unknown",
95 "Grand Central",
96 "OHare",
97 "OHareII",
98 "Heathrow",
99 "Gatwick",
100 "Paddington",
101 "Keylargo",
102 "Pangea",
103 "Intrepid",
104 "K2"
105};
106
107
108
109/*
110 * Uninorth reg. access. Note that Uni-N regs are big endian
111 */
112
113#define UN_REG(r) (uninorth_base + ((r) >> 2))
114#define UN_IN(r) (in_be32(UN_REG(r)))
115#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
116#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
117#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
118
119static struct device_node* uninorth_node;
120static u32 __iomem * uninorth_base;
121static u32 uninorth_rev;
122static int uninorth_u3;
123static void __iomem *u3_ht;
124
125/*
126 * For each motherboard family, we have a table of functions pointers
127 * that handle the various features.
128 */
129
130typedef long (*feature_call)(struct device_node* node, long param, long value);
131
132struct feature_table_entry {
133 unsigned int selector;
134 feature_call function;
135};
136
137struct pmac_mb_def
138{
139 const char* model_string;
140 const char* model_name;
141 int model_id;
142 struct feature_table_entry* features;
143 unsigned long board_flags;
144};
145static struct pmac_mb_def pmac_mb;
146
147/*
148 * Here are the chip specific feature functions
149 */
150
151static inline int
152simple_feature_tweak(struct device_node* node, int type, int reg, u32 mask, int value)
153{
154 struct macio_chip* macio;
155 unsigned long flags;
156
157 macio = macio_find(node, type);
158 if (!macio)
159 return -ENODEV;
160 LOCK(flags);
161 if (value)
162 MACIO_BIS(reg, mask);
163 else
164 MACIO_BIC(reg, mask);
165 (void)MACIO_IN32(reg);
166 UNLOCK(flags);
167
168 return 0;
169}
170
171#ifndef CONFIG_POWER4
172
173static long
174ohare_htw_scc_enable(struct device_node* node, long param, long value)
175{
176 struct macio_chip* macio;
177 unsigned long chan_mask;
178 unsigned long fcr;
179 unsigned long flags;
180 int htw, trans;
181 unsigned long rmask;
182
183 macio = macio_find(node, 0);
184 if (!macio)
185 return -ENODEV;
186 if (!strcmp(node->name, "ch-a"))
187 chan_mask = MACIO_FLAG_SCCA_ON;
188 else if (!strcmp(node->name, "ch-b"))
189 chan_mask = MACIO_FLAG_SCCB_ON;
190 else
191 return -ENODEV;
192
193 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
194 || macio->type == macio_gatwick);
195 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
196 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
197 pmac_mb.model_id != PMAC_TYPE_YIKES);
198 if (value) {
199#ifdef CONFIG_ADB_PMU
200 if ((param & 0xfff) == PMAC_SCC_IRDA)
201 pmu_enable_irled(1);
202#endif /* CONFIG_ADB_PMU */
203 LOCK(flags);
204 fcr = MACIO_IN32(OHARE_FCR);
205 /* Check if scc cell need enabling */
206 if (!(fcr & OH_SCC_ENABLE)) {
207 fcr |= OH_SCC_ENABLE;
208 if (htw) {
209 /* Side effect: this will also power up the
210 * modem, but it's too messy to figure out on which
211 * ports this controls the tranceiver and on which
212 * it controls the modem
213 */
214 if (trans)
215 fcr &= ~HRW_SCC_TRANS_EN_N;
216 MACIO_OUT32(OHARE_FCR, fcr);
217 fcr |= (rmask = HRW_RESET_SCC);
218 MACIO_OUT32(OHARE_FCR, fcr);
219 } else {
220 fcr |= (rmask = OH_SCC_RESET);
221 MACIO_OUT32(OHARE_FCR, fcr);
222 }
223 UNLOCK(flags);
224 (void)MACIO_IN32(OHARE_FCR);
225 mdelay(15);
226 LOCK(flags);
227 fcr &= ~rmask;
228 MACIO_OUT32(OHARE_FCR, fcr);
229 }
230 if (chan_mask & MACIO_FLAG_SCCA_ON)
231 fcr |= OH_SCCA_IO;
232 if (chan_mask & MACIO_FLAG_SCCB_ON)
233 fcr |= OH_SCCB_IO;
234 MACIO_OUT32(OHARE_FCR, fcr);
235 macio->flags |= chan_mask;
236 UNLOCK(flags);
237 if (param & PMAC_SCC_FLAG_XMON)
238 macio->flags |= MACIO_FLAG_SCC_LOCKED;
239 } else {
240 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
241 return -EPERM;
242 LOCK(flags);
243 fcr = MACIO_IN32(OHARE_FCR);
244 if (chan_mask & MACIO_FLAG_SCCA_ON)
245 fcr &= ~OH_SCCA_IO;
246 if (chan_mask & MACIO_FLAG_SCCB_ON)
247 fcr &= ~OH_SCCB_IO;
248 MACIO_OUT32(OHARE_FCR, fcr);
249 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
250 fcr &= ~OH_SCC_ENABLE;
251 if (htw && trans)
252 fcr |= HRW_SCC_TRANS_EN_N;
253 MACIO_OUT32(OHARE_FCR, fcr);
254 }
255 macio->flags &= ~(chan_mask);
256 UNLOCK(flags);
257 mdelay(10);
258#ifdef CONFIG_ADB_PMU
259 if ((param & 0xfff) == PMAC_SCC_IRDA)
260 pmu_enable_irled(0);
261#endif /* CONFIG_ADB_PMU */
262 }
263 return 0;
264}
265
266static long
267ohare_floppy_enable(struct device_node* node, long param, long value)
268{
269 return simple_feature_tweak(node, macio_ohare,
270 OHARE_FCR, OH_FLOPPY_ENABLE, value);
271}
272
273static long
274ohare_mesh_enable(struct device_node* node, long param, long value)
275{
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_MESH_ENABLE, value);
278}
279
280static long
281ohare_ide_enable(struct device_node* node, long param, long value)
282{
283 switch(param) {
284 case 0:
285 /* For some reason, setting the bit in set_initial_features()
286 * doesn't stick. I'm still investigating... --BenH.
287 */
288 if (value)
289 simple_feature_tweak(node, macio_ohare,
290 OHARE_FCR, OH_IOBUS_ENABLE, 1);
291 return simple_feature_tweak(node, macio_ohare,
292 OHARE_FCR, OH_IDE0_ENABLE, value);
293 case 1:
294 return simple_feature_tweak(node, macio_ohare,
295 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
296 default:
297 return -ENODEV;
298 }
299}
300
301static long
302ohare_ide_reset(struct device_node* node, long param, long value)
303{
304 switch(param) {
305 case 0:
306 return simple_feature_tweak(node, macio_ohare,
307 OHARE_FCR, OH_IDE0_RESET_N, !value);
308 case 1:
309 return simple_feature_tweak(node, macio_ohare,
310 OHARE_FCR, OH_IDE1_RESET_N, !value);
311 default:
312 return -ENODEV;
313 }
314}
315
316static long
317ohare_sleep_state(struct device_node* node, long param, long value)
318{
319 struct macio_chip* macio = &macio_chips[0];
320
321 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
322 return -EPERM;
323 if (value == 1) {
324 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
325 } else if (value == 0) {
326 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
327 }
328
329 return 0;
330}
331
332static long
333heathrow_modem_enable(struct device_node* node, long param, long value)
334{
335 struct macio_chip* macio;
336 u8 gpio;
337 unsigned long flags;
338
339 macio = macio_find(node, macio_unknown);
340 if (!macio)
341 return -ENODEV;
342 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
343 if (!value) {
344 LOCK(flags);
345 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
346 UNLOCK(flags);
347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
348 mdelay(250);
349 }
350 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
351 pmac_mb.model_id != PMAC_TYPE_YIKES) {
352 LOCK(flags);
353 if (value)
354 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
355 else
356 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
357 UNLOCK(flags);
358 (void)MACIO_IN32(HEATHROW_FCR);
359 mdelay(250);
360 }
361 if (value) {
362 LOCK(flags);
363 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
364 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
365 UNLOCK(flags); mdelay(250); LOCK(flags);
366 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
367 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
368 UNLOCK(flags); mdelay(250); LOCK(flags);
369 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
370 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
371 UNLOCK(flags); mdelay(250);
372 }
373 return 0;
374}
375
376static long
377heathrow_floppy_enable(struct device_node* node, long param, long value)
378{
379 return simple_feature_tweak(node, macio_unknown,
380 HEATHROW_FCR,
381 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
382 value);
383}
384
385static long
386heathrow_mesh_enable(struct device_node* node, long param, long value)
387{
388 struct macio_chip* macio;
389 unsigned long flags;
390
391 macio = macio_find(node, macio_unknown);
392 if (!macio)
393 return -ENODEV;
394 LOCK(flags);
395 /* Set clear mesh cell enable */
396 if (value)
397 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
398 else
399 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
400 (void)MACIO_IN32(HEATHROW_FCR);
401 udelay(10);
402 /* Set/Clear termination power */
403 if (value)
404 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
405 else
406 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
407 (void)MACIO_IN32(HEATHROW_MBCR);
408 udelay(10);
409 UNLOCK(flags);
410
411 return 0;
412}
413
414static long
415heathrow_ide_enable(struct device_node* node, long param, long value)
416{
417 switch(param) {
418 case 0:
419 return simple_feature_tweak(node, macio_unknown,
420 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
421 case 1:
422 return simple_feature_tweak(node, macio_unknown,
423 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
424 default:
425 return -ENODEV;
426 }
427}
428
429static long
430heathrow_ide_reset(struct device_node* node, long param, long value)
431{
432 switch(param) {
433 case 0:
434 return simple_feature_tweak(node, macio_unknown,
435 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
436 case 1:
437 return simple_feature_tweak(node, macio_unknown,
438 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
439 default:
440 return -ENODEV;
441 }
442}
443
444static long
445heathrow_bmac_enable(struct device_node* node, long param, long value)
446{
447 struct macio_chip* macio;
448 unsigned long flags;
449
450 macio = macio_find(node, 0);
451 if (!macio)
452 return -ENODEV;
453 if (value) {
454 LOCK(flags);
455 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
456 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
457 UNLOCK(flags);
458 (void)MACIO_IN32(HEATHROW_FCR);
459 mdelay(10);
460 LOCK(flags);
461 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
462 UNLOCK(flags);
463 (void)MACIO_IN32(HEATHROW_FCR);
464 mdelay(10);
465 } else {
466 LOCK(flags);
467 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
468 UNLOCK(flags);
469 }
470 return 0;
471}
472
473static long
474heathrow_sound_enable(struct device_node* node, long param, long value)
475{
476 struct macio_chip* macio;
477 unsigned long flags;
478
479 /* B&W G3 and Yikes don't support that properly (the
480 * sound appear to never come back after beeing shut down).
481 */
482 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
483 pmac_mb.model_id == PMAC_TYPE_YIKES)
484 return 0;
485
486 macio = macio_find(node, 0);
487 if (!macio)
488 return -ENODEV;
489 if (value) {
490 LOCK(flags);
491 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
492 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
493 UNLOCK(flags);
494 (void)MACIO_IN32(HEATHROW_FCR);
495 } else {
496 LOCK(flags);
497 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
498 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
499 UNLOCK(flags);
500 }
501 return 0;
502}
503
504static u32 save_fcr[6];
505static u32 save_mbcr;
506static u32 save_gpio_levels[2];
507static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
508static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
509static u32 save_unin_clock_ctl;
510static struct dbdma_regs save_dbdma[13];
511static struct dbdma_regs save_alt_dbdma[13];
512
513static void
514dbdma_save(struct macio_chip* macio, struct dbdma_regs* save)
515{
516 int i;
517
518 /* Save state & config of DBDMA channels */
519 for (i=0; i<13; i++) {
520 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
521 (macio->base + ((0x8000+i*0x100)>>2));
522 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
523 save[i].cmdptr = in_le32(&chan->cmdptr);
524 save[i].intr_sel = in_le32(&chan->intr_sel);
525 save[i].br_sel = in_le32(&chan->br_sel);
526 save[i].wait_sel = in_le32(&chan->wait_sel);
527 }
528}
529
530static void
531dbdma_restore(struct macio_chip* macio, struct dbdma_regs* save)
532{
533 int i;
534
535 /* Save state & config of DBDMA channels */
536 for (i=0; i<13; i++) {
537 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
538 (macio->base + ((0x8000+i*0x100)>>2));
539 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
540 while (in_le32(&chan->status) & ACTIVE)
541 mb();
542 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
543 out_le32(&chan->cmdptr, save[i].cmdptr);
544 out_le32(&chan->intr_sel, save[i].intr_sel);
545 out_le32(&chan->br_sel, save[i].br_sel);
546 out_le32(&chan->wait_sel, save[i].wait_sel);
547 }
548}
549
550static void
551heathrow_sleep(struct macio_chip* macio, int secondary)
552{
553 if (secondary) {
554 dbdma_save(macio, save_alt_dbdma);
555 save_fcr[2] = MACIO_IN32(0x38);
556 save_fcr[3] = MACIO_IN32(0x3c);
557 } else {
558 dbdma_save(macio, save_dbdma);
559 save_fcr[0] = MACIO_IN32(0x38);
560 save_fcr[1] = MACIO_IN32(0x3c);
561 save_mbcr = MACIO_IN32(0x34);
562 /* Make sure sound is shut down */
563 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
564 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
565 /* This seems to be necessary as well or the fan
566 * keeps coming up and battery drains fast */
567 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
568 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
569 /* Make sure eth is down even if module or sleep
570 * won't work properly */
571 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
572 }
573 /* Make sure modem is shut down */
574 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
575 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
576 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
577 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
578
579 /* Let things settle */
580 (void)MACIO_IN32(HEATHROW_FCR);
581}
582
583static void
584heathrow_wakeup(struct macio_chip* macio, int secondary)
585{
586 if (secondary) {
587 MACIO_OUT32(0x38, save_fcr[2]);
588 (void)MACIO_IN32(0x38);
589 mdelay(1);
590 MACIO_OUT32(0x3c, save_fcr[3]);
591 (void)MACIO_IN32(0x38);
592 mdelay(10);
593 dbdma_restore(macio, save_alt_dbdma);
594 } else {
595 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
596 (void)MACIO_IN32(0x38);
597 mdelay(1);
598 MACIO_OUT32(0x3c, save_fcr[1]);
599 (void)MACIO_IN32(0x38);
600 mdelay(1);
601 MACIO_OUT32(0x34, save_mbcr);
602 (void)MACIO_IN32(0x38);
603 mdelay(10);
604 dbdma_restore(macio, save_dbdma);
605 }
606}
607
608static long
609heathrow_sleep_state(struct device_node* node, long param, long value)
610{
611 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
612 return -EPERM;
613 if (value == 1) {
614 if (macio_chips[1].type == macio_gatwick)
615 heathrow_sleep(&macio_chips[0], 1);
616 heathrow_sleep(&macio_chips[0], 0);
617 } else if (value == 0) {
618 heathrow_wakeup(&macio_chips[0], 0);
619 if (macio_chips[1].type == macio_gatwick)
620 heathrow_wakeup(&macio_chips[0], 1);
621 }
622 return 0;
623}
624
625static long
626core99_scc_enable(struct device_node* node, long param, long value)
627{
628 struct macio_chip* macio;
629 unsigned long flags;
630 unsigned long chan_mask;
631 u32 fcr;
632
633 macio = macio_find(node, 0);
634 if (!macio)
635 return -ENODEV;
636 if (!strcmp(node->name, "ch-a"))
637 chan_mask = MACIO_FLAG_SCCA_ON;
638 else if (!strcmp(node->name, "ch-b"))
639 chan_mask = MACIO_FLAG_SCCB_ON;
640 else
641 return -ENODEV;
642
643 if (value) {
644 int need_reset_scc = 0;
645 int need_reset_irda = 0;
646
647 LOCK(flags);
648 fcr = MACIO_IN32(KEYLARGO_FCR0);
649 /* Check if scc cell need enabling */
650 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
651 fcr |= KL0_SCC_CELL_ENABLE;
652 need_reset_scc = 1;
653 }
654 if (chan_mask & MACIO_FLAG_SCCA_ON) {
655 fcr |= KL0_SCCA_ENABLE;
656 /* Don't enable line drivers for I2S modem */
657 if ((param & 0xfff) == PMAC_SCC_I2S1)
658 fcr &= ~KL0_SCC_A_INTF_ENABLE;
659 else
660 fcr |= KL0_SCC_A_INTF_ENABLE;
661 }
662 if (chan_mask & MACIO_FLAG_SCCB_ON) {
663 fcr |= KL0_SCCB_ENABLE;
664 /* Perform irda specific inits */
665 if ((param & 0xfff) == PMAC_SCC_IRDA) {
666 fcr &= ~KL0_SCC_B_INTF_ENABLE;
667 fcr |= KL0_IRDA_ENABLE;
668 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
669 fcr |= KL0_IRDA_SOURCE1_SEL;
670 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
671 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
672 need_reset_irda = 1;
673 } else
674 fcr |= KL0_SCC_B_INTF_ENABLE;
675 }
676 MACIO_OUT32(KEYLARGO_FCR0, fcr);
677 macio->flags |= chan_mask;
678 if (need_reset_scc) {
679 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
680 (void)MACIO_IN32(KEYLARGO_FCR0);
681 UNLOCK(flags);
682 mdelay(15);
683 LOCK(flags);
684 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
685 }
686 if (need_reset_irda) {
687 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
688 (void)MACIO_IN32(KEYLARGO_FCR0);
689 UNLOCK(flags);
690 mdelay(15);
691 LOCK(flags);
692 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
693 }
694 UNLOCK(flags);
695 if (param & PMAC_SCC_FLAG_XMON)
696 macio->flags |= MACIO_FLAG_SCC_LOCKED;
697 } else {
698 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
699 return -EPERM;
700 LOCK(flags);
701 fcr = MACIO_IN32(KEYLARGO_FCR0);
702 if (chan_mask & MACIO_FLAG_SCCA_ON)
703 fcr &= ~KL0_SCCA_ENABLE;
704 if (chan_mask & MACIO_FLAG_SCCB_ON) {
705 fcr &= ~KL0_SCCB_ENABLE;
706 /* Perform irda specific clears */
707 if ((param & 0xfff) == PMAC_SCC_IRDA) {
708 fcr &= ~KL0_IRDA_ENABLE;
709 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
710 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
711 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
712 }
713 }
714 MACIO_OUT32(KEYLARGO_FCR0, fcr);
715 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
716 fcr &= ~KL0_SCC_CELL_ENABLE;
717 MACIO_OUT32(KEYLARGO_FCR0, fcr);
718 }
719 macio->flags &= ~(chan_mask);
720 UNLOCK(flags);
721 mdelay(10);
722 }
723 return 0;
724}
725
726static long
727core99_modem_enable(struct device_node* node, long param, long value)
728{
729 struct macio_chip* macio;
730 u8 gpio;
731 unsigned long flags;
732
733 /* Hack for internal USB modem */
734 if (node == NULL) {
735 if (macio_chips[0].type != macio_keylargo)
736 return -ENODEV;
737 node = macio_chips[0].of_node;
738 }
739 macio = macio_find(node, 0);
740 if (!macio)
741 return -ENODEV;
742 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
743 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
744 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
745
746 if (!value) {
747 LOCK(flags);
748 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
749 UNLOCK(flags);
750 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
751 mdelay(250);
752 }
753 LOCK(flags);
754 if (value) {
755 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
756 UNLOCK(flags);
757 (void)MACIO_IN32(KEYLARGO_FCR2);
758 mdelay(250);
759 } else {
760 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
761 UNLOCK(flags);
762 }
763 if (value) {
764 LOCK(flags);
765 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
766 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
767 UNLOCK(flags); mdelay(250); LOCK(flags);
768 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
769 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
770 UNLOCK(flags); mdelay(250); LOCK(flags);
771 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
772 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
773 UNLOCK(flags); mdelay(250);
774 }
775 return 0;
776}
777
778static long
779pangea_modem_enable(struct device_node* node, long param, long value)
780{
781 struct macio_chip* macio;
782 u8 gpio;
783 unsigned long flags;
784
785 /* Hack for internal USB modem */
786 if (node == NULL) {
787 if (macio_chips[0].type != macio_pangea &&
788 macio_chips[0].type != macio_intrepid)
789 return -ENODEV;
790 node = macio_chips[0].of_node;
791 }
792 macio = macio_find(node, 0);
793 if (!macio)
794 return -ENODEV;
795 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
796 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
797 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
798
799 if (!value) {
800 LOCK(flags);
801 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
802 UNLOCK(flags);
803 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
804 mdelay(250);
805 }
806 LOCK(flags);
807 if (value) {
808 MACIO_OUT8(KL_GPIO_MODEM_POWER,
809 KEYLARGO_GPIO_OUTPUT_ENABLE);
810 UNLOCK(flags);
811 (void)MACIO_IN32(KEYLARGO_FCR2);
812 mdelay(250);
813 } else {
814 MACIO_OUT8(KL_GPIO_MODEM_POWER,
815 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
816 UNLOCK(flags);
817 }
818 if (value) {
819 LOCK(flags);
820 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
821 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
822 UNLOCK(flags); mdelay(250); LOCK(flags);
823 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
824 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
825 UNLOCK(flags); mdelay(250); LOCK(flags);
826 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
827 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
828 UNLOCK(flags); mdelay(250);
829 }
830 return 0;
831}
832
833static long
834core99_ata100_enable(struct device_node* node, long value)
835{
836 unsigned long flags;
837 struct pci_dev *pdev = NULL;
838 u8 pbus, pid;
839
840 if (uninorth_rev < 0x24)
841 return -ENODEV;
842
843 LOCK(flags);
844 if (value)
845 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
846 else
847 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
848 (void)UN_IN(UNI_N_CLOCK_CNTL);
849 UNLOCK(flags);
850 udelay(20);
851
852 if (value) {
853 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
854 pdev = pci_find_slot(pbus, pid);
855 if (pdev == NULL)
856 return 0;
857 pci_enable_device(pdev);
858 pci_set_master(pdev);
859 }
860 return 0;
861}
862
863static long
864core99_ide_enable(struct device_node* node, long param, long value)
865{
866 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
867 * based ata-100
868 */
869 switch(param) {
870 case 0:
871 return simple_feature_tweak(node, macio_unknown,
872 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
873 case 1:
874 return simple_feature_tweak(node, macio_unknown,
875 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
876 case 2:
877 return simple_feature_tweak(node, macio_unknown,
878 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
879 case 3:
880 return core99_ata100_enable(node, value);
881 default:
882 return -ENODEV;
883 }
884}
885
886static long
887core99_ide_reset(struct device_node* node, long param, long value)
888{
889 switch(param) {
890 case 0:
891 return simple_feature_tweak(node, macio_unknown,
892 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
893 case 1:
894 return simple_feature_tweak(node, macio_unknown,
895 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
896 case 2:
897 return simple_feature_tweak(node, macio_unknown,
898 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
899 default:
900 return -ENODEV;
901 }
902}
903
904static long
905core99_gmac_enable(struct device_node* node, long param, long value)
906{
907 unsigned long flags;
908
909 LOCK(flags);
910 if (value)
911 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
912 else
913 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
914 (void)UN_IN(UNI_N_CLOCK_CNTL);
915 UNLOCK(flags);
916 udelay(20);
917
918 return 0;
919}
920
921static long
922core99_gmac_phy_reset(struct device_node* node, long param, long value)
923{
924 unsigned long flags;
925 struct macio_chip* macio;
926
927 macio = &macio_chips[0];
928 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
929 macio->type != macio_intrepid)
930 return -ENODEV;
931
932 LOCK(flags);
933 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
934 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
935 UNLOCK(flags);
936 mdelay(10);
937 LOCK(flags);
938 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
939 KEYLARGO_GPIO_OUTOUT_DATA);
940 UNLOCK(flags);
941 mdelay(10);
942
943 return 0;
944}
945
946static long
947core99_sound_chip_enable(struct device_node* node, long param, long value)
948{
949 struct macio_chip* macio;
950 unsigned long flags;
951
952 macio = macio_find(node, 0);
953 if (!macio)
954 return -ENODEV;
955
956 /* Do a better probe code, screamer G4 desktops &
957 * iMacs can do that too, add a recalibrate in
958 * the driver as well
959 */
960 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
961 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
962 LOCK(flags);
963 if (value)
964 MACIO_OUT8(KL_GPIO_SOUND_POWER,
965 KEYLARGO_GPIO_OUTPUT_ENABLE |
966 KEYLARGO_GPIO_OUTOUT_DATA);
967 else
968 MACIO_OUT8(KL_GPIO_SOUND_POWER,
969 KEYLARGO_GPIO_OUTPUT_ENABLE);
970 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
971 UNLOCK(flags);
972 }
973 return 0;
974}
975
976static long
977core99_airport_enable(struct device_node* node, long param, long value)
978{
979 struct macio_chip* macio;
980 unsigned long flags;
981 int state;
982
983 macio = macio_find(node, 0);
984 if (!macio)
985 return -ENODEV;
986
987 /* Hint: we allow passing of macio itself for the sake of the
988 * sleep code
989 */
990 if (node != macio->of_node &&
991 (!node->parent || node->parent != macio->of_node))
992 return -ENODEV;
993 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
994 if (value == state)
995 return 0;
996 if (value) {
997 /* This code is a reproduction of OF enable-cardslot
998 * and init-wireless methods, slightly hacked until
999 * I got it working.
1000 */
1001 LOCK(flags);
1002 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
1003 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1004 UNLOCK(flags);
1005 mdelay(10);
1006 LOCK(flags);
1007 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
1008 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1009 UNLOCK(flags);
1010
1011 mdelay(10);
1012
1013 LOCK(flags);
1014 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1015 (void)MACIO_IN32(KEYLARGO_FCR2);
1016 udelay(10);
1017 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
1018 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
1019 udelay(10);
1020 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1021 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1022 udelay(10);
1023 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1024 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1025 udelay(10);
1026 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1027 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1028 udelay(10);
1029 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1030 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1031 UNLOCK(flags);
1032 udelay(10);
1033 MACIO_OUT32(0x1c000, 0);
1034 mdelay(1);
1035 MACIO_OUT8(0x1a3e0, 0x41);
1036 (void)MACIO_IN8(0x1a3e0);
1037 udelay(10);
1038 LOCK(flags);
1039 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1040 (void)MACIO_IN32(KEYLARGO_FCR2);
1041 UNLOCK(flags);
1042 mdelay(100);
1043
1044 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1045 } else {
1046 LOCK(flags);
1047 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1048 (void)MACIO_IN32(KEYLARGO_FCR2);
1049 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1050 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1051 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1052 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1053 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1054 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1055 UNLOCK(flags);
1056
1057 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1058 }
1059 return 0;
1060}
1061
1062#ifdef CONFIG_SMP
1063static long
1064core99_reset_cpu(struct device_node* node, long param, long value)
1065{
1066 unsigned int reset_io = 0;
1067 unsigned long flags;
1068 struct macio_chip* macio;
1069 struct device_node* np;
1070 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1071 KL_GPIO_RESET_CPU1,
1072 KL_GPIO_RESET_CPU2,
1073 KL_GPIO_RESET_CPU3 };
1074
1075 macio = &macio_chips[0];
1076 if (macio->type != macio_keylargo)
1077 return -ENODEV;
1078
1079 np = find_path_device("/cpus");
1080 if (np == NULL)
1081 return -ENODEV;
1082 for (np = np->child; np != NULL; np = np->sibling) {
1083 u32* num = (u32 *)get_property(np, "reg", NULL);
1084 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1085 if (num == NULL || rst == NULL)
1086 continue;
1087 if (param == *num) {
1088 reset_io = *rst;
1089 break;
1090 }
1091 }
1092 if (np == NULL || reset_io == 0)
1093 reset_io = dflt_reset_lines[param];
1094
1095 LOCK(flags);
1096 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1097 (void)MACIO_IN8(reset_io);
1098 udelay(1);
1099 MACIO_OUT8(reset_io, 0);
1100 (void)MACIO_IN8(reset_io);
1101 UNLOCK(flags);
1102
1103 return 0;
1104}
1105#endif /* CONFIG_SMP */
1106
1107static long
1108core99_usb_enable(struct device_node* node, long param, long value)
1109{
1110 struct macio_chip* macio;
1111 unsigned long flags;
1112 char* prop;
1113 int number;
1114 u32 reg;
1115
1116 macio = &macio_chips[0];
1117 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1118 macio->type != macio_intrepid)
1119 return -ENODEV;
1120
1121 prop = (char *)get_property(node, "AAPL,clock-id", NULL);
1122 if (!prop)
1123 return -ENODEV;
1124 if (strncmp(prop, "usb0u048", 8) == 0)
1125 number = 0;
1126 else if (strncmp(prop, "usb1u148", 8) == 0)
1127 number = 2;
1128 else if (strncmp(prop, "usb2u248", 8) == 0)
1129 number = 4;
1130 else
1131 return -ENODEV;
1132
1133 /* Sorry for the brute-force locking, but this is only used during
1134 * sleep and the timing seem to be critical
1135 */
1136 LOCK(flags);
1137 if (value) {
1138 /* Turn ON */
1139 if (number == 0) {
1140 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1141 (void)MACIO_IN32(KEYLARGO_FCR0);
1142 UNLOCK(flags);
1143 mdelay(1);
1144 LOCK(flags);
1145 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1146 } else if (number == 2) {
1147 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1148 UNLOCK(flags);
1149 (void)MACIO_IN32(KEYLARGO_FCR0);
1150 mdelay(1);
1151 LOCK(flags);
1152 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1153 } else if (number == 4) {
1154 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1155 UNLOCK(flags);
1156 (void)MACIO_IN32(KEYLARGO_FCR1);
1157 mdelay(1);
1158 LOCK(flags);
1159 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1160 }
1161 if (number < 4) {
1162 reg = MACIO_IN32(KEYLARGO_FCR4);
1163 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1164 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1165 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1166 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1167 MACIO_OUT32(KEYLARGO_FCR4, reg);
1168 (void)MACIO_IN32(KEYLARGO_FCR4);
1169 udelay(10);
1170 } else {
1171 reg = MACIO_IN32(KEYLARGO_FCR3);
1172 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1173 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1174 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1175 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1176 MACIO_OUT32(KEYLARGO_FCR3, reg);
1177 (void)MACIO_IN32(KEYLARGO_FCR3);
1178 udelay(10);
1179 }
1180 if (macio->type == macio_intrepid) {
1181 /* wait for clock stopped bits to clear */
1182 u32 test0 = 0, test1 = 0;
1183 u32 status0, status1;
1184 int timeout = 1000;
1185
1186 UNLOCK(flags);
1187 switch (number) {
1188 case 0:
1189 test0 = UNI_N_CLOCK_STOPPED_USB0;
1190 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1191 break;
1192 case 2:
1193 test0 = UNI_N_CLOCK_STOPPED_USB1;
1194 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1195 break;
1196 case 4:
1197 test0 = UNI_N_CLOCK_STOPPED_USB2;
1198 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1199 break;
1200 }
1201 do {
1202 if (--timeout <= 0) {
1203 printk(KERN_ERR "core99_usb_enable: "
1204 "Timeout waiting for clocks\n");
1205 break;
1206 }
1207 mdelay(1);
1208 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1209 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1210 } while ((status0 & test0) | (status1 & test1));
1211 LOCK(flags);
1212 }
1213 } else {
1214 /* Turn OFF */
1215 if (number < 4) {
1216 reg = MACIO_IN32(KEYLARGO_FCR4);
1217 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1218 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1219 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1220 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1221 MACIO_OUT32(KEYLARGO_FCR4, reg);
1222 (void)MACIO_IN32(KEYLARGO_FCR4);
1223 udelay(1);
1224 } else {
1225 reg = MACIO_IN32(KEYLARGO_FCR3);
1226 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1227 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1228 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1229 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1230 MACIO_OUT32(KEYLARGO_FCR3, reg);
1231 (void)MACIO_IN32(KEYLARGO_FCR3);
1232 udelay(1);
1233 }
1234 if (number == 0) {
1235 if (macio->type != macio_intrepid)
1236 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1237 (void)MACIO_IN32(KEYLARGO_FCR0);
1238 udelay(1);
1239 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1240 (void)MACIO_IN32(KEYLARGO_FCR0);
1241 } else if (number == 2) {
1242 if (macio->type != macio_intrepid)
1243 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1244 (void)MACIO_IN32(KEYLARGO_FCR0);
1245 udelay(1);
1246 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1247 (void)MACIO_IN32(KEYLARGO_FCR0);
1248 } else if (number == 4) {
1249 udelay(1);
1250 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1251 (void)MACIO_IN32(KEYLARGO_FCR1);
1252 }
1253 udelay(1);
1254 }
1255 UNLOCK(flags);
1256
1257 return 0;
1258}
1259
1260static long
1261core99_firewire_enable(struct device_node* node, long param, long value)
1262{
1263 unsigned long flags;
1264 struct macio_chip* macio;
1265
1266 macio = &macio_chips[0];
1267 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1268 macio->type != macio_intrepid)
1269 return -ENODEV;
1270 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1271 return -ENODEV;
1272
1273 LOCK(flags);
1274 if (value) {
1275 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1276 (void)UN_IN(UNI_N_CLOCK_CNTL);
1277 } else {
1278 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1279 (void)UN_IN(UNI_N_CLOCK_CNTL);
1280 }
1281 UNLOCK(flags);
1282 mdelay(1);
1283
1284 return 0;
1285}
1286
1287static long
1288core99_firewire_cable_power(struct device_node* node, long param, long value)
1289{
1290 unsigned long flags;
1291 struct macio_chip* macio;
1292
1293 /* Trick: we allow NULL node */
1294 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1295 return -ENODEV;
1296 macio = &macio_chips[0];
1297 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1298 macio->type != macio_intrepid)
1299 return -ENODEV;
1300 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1301 return -ENODEV;
1302
1303 LOCK(flags);
1304 if (value) {
1305 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1306 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1307 udelay(10);
1308 } else {
1309 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1310 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1311 }
1312 UNLOCK(flags);
1313 mdelay(1);
1314
1315 return 0;
1316}
1317
1318static long
1319intrepid_aack_delay_enable(struct device_node* node, long param, long value)
1320{
1321 unsigned long flags;
1322
1323 if (uninorth_rev < 0xd2)
1324 return -ENODEV;
1325
1326 LOCK(flags);
1327 if (param)
1328 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1329 else
1330 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1331 UNLOCK(flags);
1332
1333 return 0;
1334}
1335
1336
1337#endif /* CONFIG_POWER4 */
1338
1339static long
1340core99_read_gpio(struct device_node* node, long param, long value)
1341{
1342 struct macio_chip* macio = &macio_chips[0];
1343
1344 return MACIO_IN8(param);
1345}
1346
1347
1348static long
1349core99_write_gpio(struct device_node* node, long param, long value)
1350{
1351 struct macio_chip* macio = &macio_chips[0];
1352
1353 MACIO_OUT8(param, (u8)(value & 0xff));
1354 return 0;
1355}
1356
1357#ifdef CONFIG_POWER4
1358
1359static long
1360g5_gmac_enable(struct device_node* node, long param, long value)
1361{
1362 struct macio_chip* macio = &macio_chips[0];
1363 unsigned long flags;
1364 u8 pbus, pid;
1365
1366 LOCK(flags);
1367 if (value) {
1368 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1369 mb();
1370 k2_skiplist[0] = NULL;
1371 } else {
1372 k2_skiplist[0] = node;
1373 mb();
1374 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1375 }
1376
1377 UNLOCK(flags);
1378 mdelay(1);
1379
1380 return 0;
1381}
1382
1383static long
1384g5_fw_enable(struct device_node* node, long param, long value)
1385{
1386 struct macio_chip* macio = &macio_chips[0];
1387 unsigned long flags;
1388
1389 LOCK(flags);
1390 if (value) {
1391 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1392 mb();
1393 k2_skiplist[1] = NULL;
1394 } else {
1395 k2_skiplist[1] = node;
1396 mb();
1397 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1398 }
1399
1400 UNLOCK(flags);
1401 mdelay(1);
1402
1403 return 0;
1404}
1405
1406static long
1407g5_mpic_enable(struct device_node* node, long param, long value)
1408{
1409 unsigned long flags;
1410
1411 if (node->parent == NULL || strcmp(node->parent->name, "u3"))
1412 return 0;
1413
1414 LOCK(flags);
1415 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1416 UNLOCK(flags);
1417
1418 return 0;
1419}
1420
1421#ifdef CONFIG_SMP
1422static long
1423g5_reset_cpu(struct device_node* node, long param, long value)
1424{
1425 unsigned int reset_io = 0;
1426 unsigned long flags;
1427 struct macio_chip* macio;
1428 struct device_node* np;
1429
1430 macio = &macio_chips[0];
1431 if (macio->type != macio_keylargo2)
1432 return -ENODEV;
1433
1434 np = find_path_device("/cpus");
1435 if (np == NULL)
1436 return -ENODEV;
1437 for (np = np->child; np != NULL; np = np->sibling) {
1438 u32* num = (u32 *)get_property(np, "reg", NULL);
1439 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1440 if (num == NULL || rst == NULL)
1441 continue;
1442 if (param == *num) {
1443 reset_io = *rst;
1444 break;
1445 }
1446 }
1447 if (np == NULL || reset_io == 0)
1448 return -ENODEV;
1449
1450 LOCK(flags);
1451 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1452 (void)MACIO_IN8(reset_io);
1453 udelay(1);
1454 MACIO_OUT8(reset_io, 0);
1455 (void)MACIO_IN8(reset_io);
1456 UNLOCK(flags);
1457
1458 return 0;
1459}
1460#endif /* CONFIG_SMP */
1461
1462/*
1463 * This can be called from pmac_smp so isn't static
1464 *
1465 * This takes the second CPU off the bus on dual CPU machines
1466 * running UP
1467 */
1468void g5_phy_disable_cpu1(void)
1469{
1470 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1471}
1472
1473#endif /* CONFIG_POWER4 */
1474
1475#ifndef CONFIG_POWER4
1476
1477static void
1478keylargo_shutdown(struct macio_chip* macio, int sleep_mode)
1479{
1480 u32 temp;
1481
1482 if (sleep_mode) {
1483 mdelay(1);
1484 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1485 (void)MACIO_IN32(KEYLARGO_FCR0);
1486 mdelay(1);
1487 }
1488
1489 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1490 KL0_SCC_CELL_ENABLE |
1491 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1492 KL0_IRDA_CLK19_ENABLE);
1493
1494 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1495 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1496
1497 MACIO_BIC(KEYLARGO_FCR1,
1498 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1499 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1500 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1501 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1502 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1503 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1504 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1505 KL1_UIDE_ENABLE);
1506
1507 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1508 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1509
1510 temp = MACIO_IN32(KEYLARGO_FCR3);
1511 if (macio->rev >= 2) {
1512 temp |= KL3_SHUTDOWN_PLL2X;
1513 if (sleep_mode)
1514 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1515 }
1516
1517 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1518 KL3_SHUTDOWN_PLLKW35;
1519 if (sleep_mode)
1520 temp |= KL3_SHUTDOWN_PLLKW12;
1521 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1522 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1523 if (sleep_mode)
1524 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1525 MACIO_OUT32(KEYLARGO_FCR3, temp);
1526
1527 /* Flush posted writes & wait a bit */
1528 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1529}
1530
1531static void
1532pangea_shutdown(struct macio_chip* macio, int sleep_mode)
1533{
1534 u32 temp;
1535
1536 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1537 KL0_SCC_CELL_ENABLE |
1538 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1539
1540 MACIO_BIC(KEYLARGO_FCR1,
1541 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1542 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1543 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1544 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1545 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1546 KL1_UIDE_ENABLE);
1547 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1548 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1549
1550 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1551
1552 temp = MACIO_IN32(KEYLARGO_FCR3);
1553 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1554 KL3_SHUTDOWN_PLLKW35;
1555 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1556 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1557 if (sleep_mode)
1558 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1559 MACIO_OUT32(KEYLARGO_FCR3, temp);
1560
1561 /* Flush posted writes & wait a bit */
1562 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1563}
1564
1565static void
1566intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
1567{
1568 u32 temp;
1569
1570 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1571 KL0_SCC_CELL_ENABLE);
1572
1573 MACIO_BIC(KEYLARGO_FCR1,
1574 /*KL1_USB2_CELL_ENABLE |*/
1575 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1576 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1577 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE);
1578 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1579 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1580
1581 temp = MACIO_IN32(KEYLARGO_FCR3);
1582 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1583 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1584 if (sleep_mode)
1585 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1586 MACIO_OUT32(KEYLARGO_FCR3, temp);
1587
1588 /* Flush posted writes & wait a bit */
1589 (void)MACIO_IN32(KEYLARGO_FCR0);
1590 mdelay(10);
1591}
1592
1593
1594void pmac_tweak_clock_spreading(int enable)
1595{
1596 struct macio_chip* macio = &macio_chips[0];
1597
1598 /* Hack for doing clock spreading on some machines PowerBooks and
1599 * iBooks. This implements the "platform-do-clockspreading" OF
1600 * property as decoded manually on various models. For safety, we also
1601 * check the product ID in the device-tree in cases we'll whack the i2c
1602 * chip to make reasonably sure we won't set wrong values in there
1603 *
1604 * Of course, ultimately, we have to implement a real parser for
1605 * the platform-do-* stuff...
1606 */
1607
1608 if (macio->type == macio_intrepid) {
1609 if (enable)
1610 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1611 else
1612 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1613 mdelay(40);
1614 }
1615
1616 while (machine_is_compatible("PowerBook5,2") ||
1617 machine_is_compatible("PowerBook5,3") ||
1618 machine_is_compatible("PowerBook6,2") ||
1619 machine_is_compatible("PowerBook6,3")) {
1620 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
1621 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
1622 u8 buffer[9];
1623 u32 *productID;
1624 int i, rc, changed = 0;
1625
1626 if (dt == NULL)
1627 break;
1628 productID = (u32 *)get_property(dt, "pid#", NULL);
1629 if (productID == NULL)
1630 break;
1631 while(ui2c) {
1632 struct device_node *p = of_get_parent(ui2c);
1633 if (p && !strcmp(p->name, "uni-n"))
1634 break;
1635 ui2c = of_find_node_by_type(ui2c, "i2c");
1636 }
1637 if (ui2c == NULL)
1638 break;
1639 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
1640 rc = pmac_low_i2c_open(ui2c, 1);
1641 if (rc != 0)
1642 break;
1643 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1644 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1645 DBG("read result: %d,", rc);
1646 if (rc != 0) {
1647 pmac_low_i2c_close(ui2c);
1648 break;
1649 }
1650 for (i=0; i<9; i++)
1651 DBG(" %02x", buffer[i]);
1652 DBG("\n");
1653
1654 switch(*productID) {
1655 case 0x1182: /* AlBook 12" rev 2 */
1656 case 0x1183: /* iBook G4 12" */
1657 buffer[0] = (buffer[0] & 0x8f) | 0x70;
1658 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1659 buffer[5] = (buffer[5] & 0x80) | 0x31;
1660 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1661 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
1662 buffer[8] = (buffer[8] & 0x00) | 0x30;
1663 changed = 1;
1664 break;
1665 case 0x3142: /* AlBook 15" (ATI M10) */
1666 case 0x3143: /* AlBook 17" (ATI M10) */
1667 buffer[0] = (buffer[0] & 0xaf) | 0x50;
1668 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1669 buffer[5] = (buffer[5] & 0x80) | 0x31;
1670 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1671 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
1672 buffer[8] = (buffer[8] & 0x00) | 0x30;
1673 changed = 1;
1674 break;
1675 default:
1676 DBG("i2c-hwclock: Machine model not handled\n");
1677 break;
1678 }
1679 if (!changed) {
1680 pmac_low_i2c_close(ui2c);
1681 break;
1682 }
1683 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
1684 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
1685 DBG("write result: %d,", rc);
1686 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1687 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1688 DBG("read result: %d,", rc);
1689 if (rc != 0) {
1690 pmac_low_i2c_close(ui2c);
1691 break;
1692 }
1693 for (i=0; i<9; i++)
1694 DBG(" %02x", buffer[i]);
1695 pmac_low_i2c_close(ui2c);
1696 break;
1697 }
1698}
1699
1700
1701static int
1702core99_sleep(void)
1703{
1704 struct macio_chip* macio;
1705 int i;
1706
1707 macio = &macio_chips[0];
1708 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1709 macio->type != macio_intrepid)
1710 return -ENODEV;
1711
1712 /* We power off the wireless slot in case it was not done
1713 * by the driver. We don't power it on automatically however
1714 */
1715 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1716 core99_airport_enable(macio->of_node, 0, 0);
1717
1718 /* We power off the FW cable. Should be done by the driver... */
1719 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1720 core99_firewire_enable(NULL, 0, 0);
1721 core99_firewire_cable_power(NULL, 0, 0);
1722 }
1723
1724 /* We make sure int. modem is off (in case driver lost it) */
1725 if (macio->type == macio_keylargo)
1726 core99_modem_enable(macio->of_node, 0, 0);
1727 else
1728 pangea_modem_enable(macio->of_node, 0, 0);
1729
1730 /* We make sure the sound is off as well */
1731 core99_sound_chip_enable(macio->of_node, 0, 0);
1732
1733 /*
1734 * Save various bits of KeyLargo
1735 */
1736
1737 /* Save the state of the various GPIOs */
1738 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1739 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1740 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1741 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1742 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1743 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1744
1745 /* Save the FCRs */
1746 if (macio->type == macio_keylargo)
1747 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1748 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1749 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1750 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1751 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1752 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1753 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1754 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1755
1756 /* Save state & config of DBDMA channels */
1757 dbdma_save(macio, save_dbdma);
1758
1759 /*
1760 * Turn off as much as we can
1761 */
1762 if (macio->type == macio_pangea)
1763 pangea_shutdown(macio, 1);
1764 else if (macio->type == macio_intrepid)
1765 intrepid_shutdown(macio, 1);
1766 else if (macio->type == macio_keylargo)
1767 keylargo_shutdown(macio, 1);
1768
1769 /*
1770 * Put the host bridge to sleep
1771 */
1772
1773 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1774 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1775 * enabled !
1776 */
1777 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1778 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1779 udelay(100);
1780 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1781 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1782 mdelay(10);
1783
1784 /*
1785 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1786 */
1787 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1788 MACIO_BIS(0x506e0, 0x00400000);
1789 MACIO_BIS(0x506e0, 0x80000000);
1790 }
1791 return 0;
1792}
1793
1794static int
1795core99_wake_up(void)
1796{
1797 struct macio_chip* macio;
1798 int i;
1799
1800 macio = &macio_chips[0];
1801 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1802 macio->type != macio_intrepid)
1803 return -ENODEV;
1804
1805 /*
1806 * Wakeup the host bridge
1807 */
1808 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1809 udelay(10);
1810 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1811 udelay(10);
1812
1813 /*
1814 * Restore KeyLargo
1815 */
1816
1817 if (macio->type == macio_keylargo) {
1818 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1819 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1820 }
1821 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1822 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1823 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1824 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1825 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1826 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1827 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1828 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1829 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1830 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1831 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1832 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1833 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1834 }
1835
1836 dbdma_restore(macio, save_dbdma);
1837
1838 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1839 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1840 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1841 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1842 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1843 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1844
1845 /* FIXME more black magic with OpenPIC ... */
1846 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1847 MACIO_BIC(0x506e0, 0x00400000);
1848 MACIO_BIC(0x506e0, 0x80000000);
1849 }
1850
1851 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1852 udelay(100);
1853
1854 return 0;
1855}
1856
1857static long
1858core99_sleep_state(struct device_node* node, long param, long value)
1859{
1860 /* Param == 1 means to enter the "fake sleep" mode that is
1861 * used for CPU speed switch
1862 */
1863 if (param == 1) {
1864 if (value == 1) {
1865 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1866 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1867 } else {
1868 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1869 udelay(10);
1870 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1871 udelay(10);
1872 }
1873 return 0;
1874 }
1875 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1876 return -EPERM;
1877
1878 if (value == 1)
1879 return core99_sleep();
1880 else if (value == 0)
1881 return core99_wake_up();
1882 return 0;
1883}
1884
1885#endif /* CONFIG_POWER4 */
1886
1887static long
1888generic_dev_can_wake(struct device_node* node, long param, long value)
1889{
1890 /* Todo: eventually check we are really dealing with on-board
1891 * video device ...
1892 */
1893
1894 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1895 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1896 return 0;
1897}
1898
1899static long
1900generic_get_mb_info(struct device_node* node, long param, long value)
1901{
1902 switch(param) {
1903 case PMAC_MB_INFO_MODEL:
1904 return pmac_mb.model_id;
1905 case PMAC_MB_INFO_FLAGS:
1906 return pmac_mb.board_flags;
1907 case PMAC_MB_INFO_NAME:
1908 /* hack hack hack... but should work */
1909 *((const char **)value) = pmac_mb.model_name;
1910 return 0;
1911 }
1912 return -EINVAL;
1913}
1914
1915
1916/*
1917 * Table definitions
1918 */
1919
1920/* Used on any machine
1921 */
1922static struct feature_table_entry any_features[] = {
1923 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1924 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1925 { 0, NULL }
1926};
1927
1928#ifndef CONFIG_POWER4
1929
1930/* OHare based motherboards. Currently, we only use these on the
1931 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1932 * to have issues with turning on/off those asic cells
1933 */
1934static struct feature_table_entry ohare_features[] = {
1935 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1936 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1937 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1938 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1939 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1940 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1941 { 0, NULL }
1942};
1943
1944/* Heathrow desktop machines (Beige G3).
1945 * Separated as some features couldn't be properly tested
1946 * and the serial port control bits appear to confuse it.
1947 */
1948static struct feature_table_entry heathrow_desktop_features[] = {
1949 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1950 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1951 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1952 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1953 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1954 { 0, NULL }
1955};
1956
1957/* Heathrow based laptop, that is the Wallstreet and mainstreet
1958 * powerbooks.
1959 */
1960static struct feature_table_entry heathrow_laptop_features[] = {
1961 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1962 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1963 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1964 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1965 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1966 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1967 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1968 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1969 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1970 { 0, NULL }
1971};
1972
1973/* Paddington based machines
1974 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1975 */
1976static struct feature_table_entry paddington_features[] = {
1977 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1978 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1979 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1980 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1981 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1982 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1983 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1984 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1985 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1986 { 0, NULL }
1987};
1988
1989/* Core99 & MacRISC 2 machines (all machines released since the
1990 * iBook (included), that is all AGP machines, except pangea
1991 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1992 * used on iBook2 & iMac "flow power".
1993 */
1994static struct feature_table_entry core99_features[] = {
1995 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1996 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
1997 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1998 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1999 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2000 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2001 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2002 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2003 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2004 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2005 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2006 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2007#ifdef CONFIG_SMP
2008 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2009#endif /* CONFIG_SMP */
2010 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2011 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2012 { 0, NULL }
2013};
2014
2015/* RackMac
2016 */
2017static struct feature_table_entry rackmac_features[] = {
2018 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2019 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2020 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2021 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2022 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2023 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2024 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2025 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2026 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2027#ifdef CONFIG_SMP
2028 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2029#endif /* CONFIG_SMP */
2030 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2031 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2032 { 0, NULL }
2033};
2034
2035/* Pangea features
2036 */
2037static struct feature_table_entry pangea_features[] = {
2038 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2039 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2040 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2041 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2042 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2043 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2044 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2045 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2046 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2047 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2048 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2049 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2050 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2051 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2052 { 0, NULL }
2053};
2054
2055/* Intrepid features
2056 */
2057static struct feature_table_entry intrepid_features[] = {
2058 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2059 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2060 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2061 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2062 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2063 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2064 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2065 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2066 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2067 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2068 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2069 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2070 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2071 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2072 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2073 { 0, NULL }
2074};
2075
2076#else /* CONFIG_POWER4 */
2077
2078/* G5 features
2079 */
2080static struct feature_table_entry g5_features[] = {
2081 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2082 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2083 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2084#ifdef CONFIG_SMP
2085 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2086#endif /* CONFIG_SMP */
2087 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2088 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2089 { 0, NULL }
2090};
2091
2092#endif /* CONFIG_POWER4 */
2093
2094static struct pmac_mb_def pmac_mb_defs[] = {
2095#ifndef CONFIG_POWER4
2096 /*
2097 * Desktops
2098 */
2099
2100 { "AAPL,8500", "PowerMac 8500/8600",
2101 PMAC_TYPE_PSURGE, NULL,
2102 0
2103 },
2104 { "AAPL,9500", "PowerMac 9500/9600",
2105 PMAC_TYPE_PSURGE, NULL,
2106 0
2107 },
2108 { "AAPL,7200", "PowerMac 7200",
2109 PMAC_TYPE_PSURGE, NULL,
2110 0
2111 },
2112 { "AAPL,7300", "PowerMac 7200/7300",
2113 PMAC_TYPE_PSURGE, NULL,
2114 0
2115 },
2116 { "AAPL,7500", "PowerMac 7500",
2117 PMAC_TYPE_PSURGE, NULL,
2118 0
2119 },
2120 { "AAPL,ShinerESB", "Apple Network Server",
2121 PMAC_TYPE_ANS, NULL,
2122 0
2123 },
2124 { "AAPL,e407", "Alchemy",
2125 PMAC_TYPE_ALCHEMY, NULL,
2126 0
2127 },
2128 { "AAPL,e411", "Gazelle",
2129 PMAC_TYPE_GAZELLE, NULL,
2130 0
2131 },
2132 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2133 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2134 0
2135 },
2136 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2137 PMAC_TYPE_SILK, heathrow_desktop_features,
2138 0
2139 },
2140 { "PowerMac1,1", "Blue&White G3",
2141 PMAC_TYPE_YOSEMITE, paddington_features,
2142 0
2143 },
2144 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2145 PMAC_TYPE_YIKES, paddington_features,
2146 0
2147 },
2148 { "PowerMac2,1", "iMac FireWire",
2149 PMAC_TYPE_FW_IMAC, core99_features,
2150 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2151 },
2152 { "PowerMac2,2", "iMac FireWire",
2153 PMAC_TYPE_FW_IMAC, core99_features,
2154 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2155 },
2156 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2157 PMAC_TYPE_SAWTOOTH, core99_features,
2158 PMAC_MB_OLD_CORE99
2159 },
2160 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2161 PMAC_TYPE_SAWTOOTH, core99_features,
2162 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2163 },
2164 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2165 PMAC_TYPE_SAWTOOTH, core99_features,
2166 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2167 },
2168 { "PowerMac3,4", "PowerMac G4 Silver",
2169 PMAC_TYPE_QUICKSILVER, core99_features,
2170 PMAC_MB_MAY_SLEEP
2171 },
2172 { "PowerMac3,5", "PowerMac G4 Silver",
2173 PMAC_TYPE_QUICKSILVER, core99_features,
2174 PMAC_MB_MAY_SLEEP
2175 },
2176 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2177 PMAC_TYPE_WINDTUNNEL, core99_features,
2178 PMAC_MB_MAY_SLEEP,
2179 },
2180 { "PowerMac4,1", "iMac \"Flower Power\"",
2181 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2182 PMAC_MB_MAY_SLEEP
2183 },
2184 { "PowerMac4,2", "Flat panel iMac",
2185 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2186 PMAC_MB_CAN_SLEEP
2187 },
2188 { "PowerMac4,4", "eMac",
2189 PMAC_TYPE_EMAC, core99_features,
2190 PMAC_MB_MAY_SLEEP
2191 },
2192 { "PowerMac5,1", "PowerMac G4 Cube",
2193 PMAC_TYPE_CUBE, core99_features,
2194 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2195 },
2196 { "PowerMac6,1", "Flat panel iMac",
2197 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2198 PMAC_MB_MAY_SLEEP,
2199 },
2200 { "PowerMac6,3", "Flat panel iMac",
2201 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2202 PMAC_MB_MAY_SLEEP,
2203 },
2204 { "PowerMac6,4", "eMac",
2205 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2206 PMAC_MB_MAY_SLEEP,
2207 },
2208 { "PowerMac10,1", "Mac mini",
2209 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2210 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER,
2211 },
2212 { "iMac,1", "iMac (first generation)",
2213 PMAC_TYPE_ORIG_IMAC, paddington_features,
2214 0
2215 },
2216
2217 /*
2218 * Xserve's
2219 */
2220
2221 { "RackMac1,1", "XServe",
2222 PMAC_TYPE_RACKMAC, rackmac_features,
2223 0,
2224 },
2225 { "RackMac1,2", "XServe rev. 2",
2226 PMAC_TYPE_RACKMAC, rackmac_features,
2227 0,
2228 },
2229
2230 /*
2231 * Laptops
2232 */
2233
2234 { "AAPL,3400/2400", "PowerBook 3400",
2235 PMAC_TYPE_HOOPER, ohare_features,
2236 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2237 },
2238 { "AAPL,3500", "PowerBook 3500",
2239 PMAC_TYPE_KANGA, ohare_features,
2240 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2241 },
2242 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2243 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2244 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2245 },
2246 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2247 PMAC_TYPE_101_PBOOK, paddington_features,
2248 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2249 },
2250 { "PowerBook2,1", "iBook (first generation)",
2251 PMAC_TYPE_ORIG_IBOOK, core99_features,
2252 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2253 },
2254 { "PowerBook2,2", "iBook FireWire",
2255 PMAC_TYPE_FW_IBOOK, core99_features,
2256 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2257 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2258 },
2259 { "PowerBook3,1", "PowerBook Pismo",
2260 PMAC_TYPE_PISMO, core99_features,
2261 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2262 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2263 },
2264 { "PowerBook3,2", "PowerBook Titanium",
2265 PMAC_TYPE_TITANIUM, core99_features,
2266 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2267 },
2268 { "PowerBook3,3", "PowerBook Titanium II",
2269 PMAC_TYPE_TITANIUM2, core99_features,
2270 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2271 },
2272 { "PowerBook3,4", "PowerBook Titanium III",
2273 PMAC_TYPE_TITANIUM3, core99_features,
2274 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2275 },
2276 { "PowerBook3,5", "PowerBook Titanium IV",
2277 PMAC_TYPE_TITANIUM4, core99_features,
2278 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2279 },
2280 { "PowerBook4,1", "iBook 2",
2281 PMAC_TYPE_IBOOK2, pangea_features,
2282 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2283 },
2284 { "PowerBook4,2", "iBook 2",
2285 PMAC_TYPE_IBOOK2, pangea_features,
2286 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2287 },
2288 { "PowerBook4,3", "iBook 2 rev. 2",
2289 PMAC_TYPE_IBOOK2, pangea_features,
2290 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2291 },
2292 { "PowerBook5,1", "PowerBook G4 17\"",
2293 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2294 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2295 },
2296 { "PowerBook5,2", "PowerBook G4 15\"",
2297 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2298 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2299 },
2300 { "PowerBook5,3", "PowerBook G4 17\"",
2301 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2302 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2303 },
2304 { "PowerBook5,4", "PowerBook G4 15\"",
2305 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2306 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2307 },
2308 { "PowerBook5,5", "PowerBook G4 17\"",
2309 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2310 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2311 },
2312 { "PowerBook5,6", "PowerBook G4 15\"",
2313 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2314 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2315 },
2316 { "PowerBook5,7", "PowerBook G4 17\"",
2317 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2318 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2319 },
2320 { "PowerBook6,1", "PowerBook G4 12\"",
2321 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2322 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2323 },
2324 { "PowerBook6,2", "PowerBook G4",
2325 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2326 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2327 },
2328 { "PowerBook6,3", "iBook G4",
2329 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2330 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2331 },
2332 { "PowerBook6,4", "PowerBook G4 12\"",
2333 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2334 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2335 },
2336 { "PowerBook6,5", "iBook G4",
2337 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2338 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2339 },
2340 { "PowerBook6,7", "iBook G4",
2341 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2342 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2343 },
2344 { "PowerBook6,8", "PowerBook G4 12\"",
2345 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2346 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2347 },
2348#else /* CONFIG_POWER4 */
2349 { "PowerMac7,2", "PowerMac G5",
2350 PMAC_TYPE_POWERMAC_G5, g5_features,
2351 0,
2352 },
2353#endif /* CONFIG_POWER4 */
2354};
2355
2356/*
2357 * The toplevel feature_call callback
2358 */
2359long
2360pmac_do_feature_call(unsigned int selector, ...)
2361{
2362 struct device_node* node;
2363 long param, value;
2364 int i;
2365 feature_call func = NULL;
2366 va_list args;
2367
2368 if (pmac_mb.features)
2369 for (i=0; pmac_mb.features[i].function; i++)
2370 if (pmac_mb.features[i].selector == selector) {
2371 func = pmac_mb.features[i].function;
2372 break;
2373 }
2374 if (!func)
2375 for (i=0; any_features[i].function; i++)
2376 if (any_features[i].selector == selector) {
2377 func = any_features[i].function;
2378 break;
2379 }
2380 if (!func)
2381 return -ENODEV;
2382
2383 va_start(args, selector);
2384 node = (struct device_node*)va_arg(args, void*);
2385 param = va_arg(args, long);
2386 value = va_arg(args, long);
2387 va_end(args);
2388
2389 return func(node, param, value);
2390}
2391
2392static int __init
2393probe_motherboard(void)
2394{
2395 int i;
2396 struct macio_chip* macio = &macio_chips[0];
2397 const char* model = NULL;
2398 struct device_node *dt;
2399
2400 /* Lookup known motherboard type in device-tree. First try an
2401 * exact match on the "model" property, then try a "compatible"
2402 * match is none is found.
2403 */
2404 dt = find_devices("device-tree");
2405 if (dt != NULL)
2406 model = (const char *) get_property(dt, "model", NULL);
2407 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2408 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2409 pmac_mb = pmac_mb_defs[i];
2410 goto found;
2411 }
2412 }
2413 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2414 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2415 pmac_mb = pmac_mb_defs[i];
2416 goto found;
2417 }
2418 }
2419
2420 /* Fallback to selection depending on mac-io chip type */
2421 switch(macio->type) {
2422#ifndef CONFIG_POWER4
2423 case macio_grand_central:
2424 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2425 pmac_mb.model_name = "Unknown PowerSurge";
2426 break;
2427 case macio_ohare:
2428 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2429 pmac_mb.model_name = "Unknown OHare-based";
2430 break;
2431 case macio_heathrow:
2432 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2433 pmac_mb.model_name = "Unknown Heathrow-based";
2434 pmac_mb.features = heathrow_desktop_features;
2435 break;
2436 case macio_paddington:
2437 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2438 pmac_mb.model_name = "Unknown Paddington-based";
2439 pmac_mb.features = paddington_features;
2440 break;
2441 case macio_keylargo:
2442 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2443 pmac_mb.model_name = "Unknown Keylargo-based";
2444 pmac_mb.features = core99_features;
2445 break;
2446 case macio_pangea:
2447 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2448 pmac_mb.model_name = "Unknown Pangea-based";
2449 pmac_mb.features = pangea_features;
2450 break;
2451 case macio_intrepid:
2452 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2453 pmac_mb.model_name = "Unknown Intrepid-based";
2454 pmac_mb.features = intrepid_features;
2455 break;
2456#else /* CONFIG_POWER4 */
2457 case macio_keylargo2:
2458 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2459 pmac_mb.model_name = "Unknown G5";
2460 pmac_mb.features = g5_features;
2461 break;
2462#endif /* CONFIG_POWER4 */
2463 default:
2464 return -ENODEV;
2465 }
2466found:
2467#ifndef CONFIG_POWER4
2468 /* Fixup Hooper vs. Comet */
2469 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2470 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2471 if (!mach_id_ptr)
2472 return -ENODEV;
2473 /* Here, I used to disable the media-bay on comet. It
2474 * appears this is wrong, the floppy connector is actually
2475 * a kind of media-bay and works with the current driver.
2476 */
2477 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2478 pmac_mb.model_id = PMAC_TYPE_COMET;
2479 iounmap(mach_id_ptr);
2480 }
2481#endif /* CONFIG_POWER4 */
2482
2483#ifdef CONFIG_6xx
2484 /* Set default value of powersave_nap on machines that support it.
2485 * It appears that uninorth rev 3 has a problem with it, we don't
2486 * enable it on those. In theory, the flush-on-lock property is
2487 * supposed to be set when not supported, but I'm not very confident
2488 * that all Apple OF revs did it properly, I do it the paranoid way.
2489 */
2490 while (uninorth_base && uninorth_rev > 3) {
2491 struct device_node* np = find_path_device("/cpus");
2492 if (!np || !np->child) {
2493 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2494 break;
2495 }
2496 np = np->child;
2497 /* Nap mode not supported on SMP */
2498 if (np->sibling)
2499 break;
2500 /* Nap mode not supported if flush-on-lock property is present */
2501 if (get_property(np, "flush-on-lock", NULL))
2502 break;
2503 powersave_nap = 1;
2504 printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
2505 break;
2506 }
2507
2508 /* On CPUs that support it (750FX), lowspeed by default during
2509 * NAP mode
2510 */
2511 powersave_lowspeed = 1;
2512#endif /* CONFIG_6xx */
2513#ifdef CONFIG_POWER4
2514 powersave_nap = 1;
2515#endif
2516 /* Check for "mobile" machine */
2517 if (model && (strncmp(model, "PowerBook", 9) == 0
2518 || strncmp(model, "iBook", 5) == 0))
2519 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2520
2521
2522 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2523 return 0;
2524}
2525
2526/* Initialize the Core99 UniNorth host bridge and memory controller
2527 */
2528static void __init
2529probe_uninorth(void)
2530{
2531 unsigned long actrl;
2532
2533 /* Locate core99 Uni-N */
2534 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2535 /* Locate G5 u3 */
2536 if (uninorth_node == NULL) {
2537 uninorth_node = of_find_node_by_name(NULL, "u3");
2538 uninorth_u3 = 1;
2539 }
2540 if (uninorth_node && uninorth_node->n_addrs > 0) {
2541 unsigned long address = uninorth_node->addrs[0].address;
2542 uninorth_base = ioremap(address, 0x40000);
2543 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2544 if (uninorth_u3)
2545 u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2546 } else
2547 uninorth_node = NULL;
2548
2549 if (!uninorth_node)
2550 return;
2551
2552 printk(KERN_INFO "Found %s memory controller & host bridge, revision: %d\n",
2553 uninorth_u3 ? "U3" : "UniNorth", uninorth_rev);
2554 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2555
2556 /* Set the arbitrer QAck delay according to what Apple does
2557 */
2558 if (uninorth_rev < 0x11) {
2559 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2560 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2561 UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2562 UN_OUT(UNI_N_ARB_CTRL, actrl);
2563 }
2564
2565 /* Some more magic as done by them in recent MacOS X on UniNorth
2566 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2567 * memory timeout
2568 */
2569 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
2570 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2571}
2572
2573static void __init
2574probe_one_macio(const char* name, const char* compat, int type)
2575{
2576 struct device_node* node;
2577 int i;
2578 volatile u32 __iomem * base;
2579 u32* revp;
2580
2581 node = find_devices(name);
2582 if (!node || !node->n_addrs)
2583 return;
2584 if (compat)
2585 do {
2586 if (device_is_compatible(node, compat))
2587 break;
2588 node = node->next;
2589 } while (node);
2590 if (!node)
2591 return;
2592 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2593 if (!macio_chips[i].of_node)
2594 break;
2595 if (macio_chips[i].of_node == node)
2596 return;
2597 }
2598 if (i >= MAX_MACIO_CHIPS) {
2599 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2600 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2601 return;
2602 }
2603 base = ioremap(node->addrs[0].address, node->addrs[0].size);
2604 if (!base) {
2605 printk(KERN_ERR "pmac_feature: Can't map mac-io chip !\n");
2606 return;
2607 }
2608 if (type == macio_keylargo) {
2609 u32* did = (u32 *)get_property(node, "device-id", NULL);
2610 if (*did == 0x00000025)
2611 type = macio_pangea;
2612 if (*did == 0x0000003e)
2613 type = macio_intrepid;
2614 }
2615 macio_chips[i].of_node = node;
2616 macio_chips[i].type = type;
2617 macio_chips[i].base = base;
2618 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2619 macio_chips[i].name = macio_names[type];
2620 revp = (u32 *)get_property(node, "revision-id", NULL);
2621 if (revp)
2622 macio_chips[i].rev = *revp;
2623 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2624 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2625}
2626
2627static int __init
2628probe_macios(void)
2629{
2630 /* Warning, ordering is important */
2631 probe_one_macio("gc", NULL, macio_grand_central);
2632 probe_one_macio("ohare", NULL, macio_ohare);
2633 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2634 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2635 probe_one_macio("mac-io", "paddington", macio_paddington);
2636 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2637 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2638 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2639
2640 /* Make sure the "main" macio chip appear first */
2641 if (macio_chips[0].type == macio_gatwick
2642 && macio_chips[1].type == macio_heathrow) {
2643 struct macio_chip temp = macio_chips[0];
2644 macio_chips[0] = macio_chips[1];
2645 macio_chips[1] = temp;
2646 }
2647 if (macio_chips[0].type == macio_ohareII
2648 && macio_chips[1].type == macio_ohare) {
2649 struct macio_chip temp = macio_chips[0];
2650 macio_chips[0] = macio_chips[1];
2651 macio_chips[1] = temp;
2652 }
2653 macio_chips[0].lbus.index = 0;
2654 macio_chips[1].lbus.index = 1;
2655
2656 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2657}
2658
2659static void __init
2660initial_serial_shutdown(struct device_node* np)
2661{
2662 int len;
2663 struct slot_names_prop {
2664 int count;
2665 char name[1];
2666 } *slots;
2667 char *conn;
2668 int port_type = PMAC_SCC_ASYNC;
2669 int modem = 0;
2670
2671 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
2672 conn = get_property(np, "AAPL,connector", &len);
2673 if (conn && (strcmp(conn, "infrared") == 0))
2674 port_type = PMAC_SCC_IRDA;
2675 else if (device_is_compatible(np, "cobalt"))
2676 modem = 1;
2677 else if (slots && slots->count > 0) {
2678 if (strcmp(slots->name, "IrDA") == 0)
2679 port_type = PMAC_SCC_IRDA;
2680 else if (strcmp(slots->name, "Modem") == 0)
2681 modem = 1;
2682 }
2683 if (modem)
2684 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2685 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2686}
2687
2688static void __init
2689set_initial_features(void)
2690{
2691 struct device_node* np;
2692
2693 /* That hack appears to be necessary for some StarMax motherboards
2694 * but I'm not too sure it was audited for side-effects on other
2695 * ohare based machines...
2696 * Since I still have difficulties figuring the right way to
2697 * differenciate them all and since that hack was there for a long
2698 * time, I'll keep it around
2699 */
2700 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2701 struct macio_chip* macio = &macio_chips[0];
2702 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2703 } else if (macio_chips[0].type == macio_ohare) {
2704 struct macio_chip* macio = &macio_chips[0];
2705 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2706 } else if (macio_chips[1].type == macio_ohare) {
2707 struct macio_chip* macio = &macio_chips[1];
2708 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2709 }
2710
2711#ifdef CONFIG_POWER4
2712 if (macio_chips[0].type == macio_keylargo2) {
2713#ifndef CONFIG_SMP
2714 /* On SMP machines running UP, we have the second CPU eating
2715 * bus cycles. We need to take it off the bus. This is done
2716 * from pmac_smp for SMP kernels running on one CPU
2717 */
2718 np = of_find_node_by_type(NULL, "cpu");
2719 if (np != NULL)
2720 np = of_find_node_by_type(np, "cpu");
2721 if (np != NULL) {
2722 g5_phy_disable_cpu1();
2723 of_node_put(np);
2724 }
2725#endif /* CONFIG_SMP */
2726 /* Enable GMAC for now for PCI probing. It will be disabled
2727 * later on after PCI probe
2728 */
2729 np = of_find_node_by_name(NULL, "ethernet");
2730 while(np) {
2731 if (device_is_compatible(np, "K2-GMAC"))
2732 g5_gmac_enable(np, 0, 1);
2733 np = of_find_node_by_name(np, "ethernet");
2734 }
2735
2736 /* Enable FW before PCI probe. Will be disabled later on
2737 * Note: We should have a batter way to check that we are
2738 * dealing with uninorth internal cell and not a PCI cell
2739 * on the external PCI. The code below works though.
2740 */
2741 np = of_find_node_by_name(NULL, "firewire");
2742 while(np) {
2743 if (device_is_compatible(np, "pci106b,5811")) {
2744 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2745 g5_fw_enable(np, 0, 1);
2746 }
2747 np = of_find_node_by_name(np, "firewire");
2748 }
2749 }
2750#else /* CONFIG_POWER4 */
2751
2752 if (macio_chips[0].type == macio_keylargo ||
2753 macio_chips[0].type == macio_pangea ||
2754 macio_chips[0].type == macio_intrepid) {
2755 /* Enable GMAC for now for PCI probing. It will be disabled
2756 * later on after PCI probe
2757 */
2758 np = of_find_node_by_name(NULL, "ethernet");
2759 while(np) {
2760 if (np->parent
2761 && device_is_compatible(np->parent, "uni-north")
2762 && device_is_compatible(np, "gmac"))
2763 core99_gmac_enable(np, 0, 1);
2764 np = of_find_node_by_name(np, "ethernet");
2765 }
2766
2767 /* Enable FW before PCI probe. Will be disabled later on
2768 * Note: We should have a batter way to check that we are
2769 * dealing with uninorth internal cell and not a PCI cell
2770 * on the external PCI. The code below works though.
2771 */
2772 np = of_find_node_by_name(NULL, "firewire");
2773 while(np) {
2774 if (np->parent
2775 && device_is_compatible(np->parent, "uni-north")
2776 && (device_is_compatible(np, "pci106b,18") ||
2777 device_is_compatible(np, "pci106b,30") ||
2778 device_is_compatible(np, "pci11c1,5811"))) {
2779 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2780 core99_firewire_enable(np, 0, 1);
2781 }
2782 np = of_find_node_by_name(np, "firewire");
2783 }
2784
2785 /* Enable ATA-100 before PCI probe. */
2786 np = of_find_node_by_name(NULL, "ata-6");
2787 while(np) {
2788 if (np->parent
2789 && device_is_compatible(np->parent, "uni-north")
2790 && device_is_compatible(np, "kauai-ata")) {
2791 core99_ata100_enable(np, 1);
2792 }
2793 np = of_find_node_by_name(np, "ata-6");
2794 }
2795
2796 /* Switch airport off */
2797 np = find_devices("radio");
2798 while(np) {
2799 if (np && np->parent == macio_chips[0].of_node) {
2800 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2801 core99_airport_enable(np, 0, 0);
2802 }
2803 np = np->next;
2804 }
2805 }
2806
2807 /* On all machines that support sound PM, switch sound off */
2808 if (macio_chips[0].of_node)
2809 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2810 macio_chips[0].of_node, 0, 0);
2811
2812 /* While on some desktop G3s, we turn it back on */
2813 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2814 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2815 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2816 struct macio_chip* macio = &macio_chips[0];
2817 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2818 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2819 }
2820
2821 /* Some machine models need the clock chip to be properly setup for
2822 * clock spreading now. This should be a platform function but we
2823 * don't do these at the moment
2824 */
2825 pmac_tweak_clock_spreading(1);
2826
2827#endif /* CONFIG_POWER4 */
2828
2829 /* On all machines, switch modem & serial ports off */
2830 np = find_devices("ch-a");
2831 while(np) {
2832 initial_serial_shutdown(np);
2833 np = np->next;
2834 }
2835 np = find_devices("ch-b");
2836 while(np) {
2837 initial_serial_shutdown(np);
2838 np = np->next;
2839 }
2840}
2841
2842void __init
2843pmac_feature_init(void)
2844{
2845 /* Detect the UniNorth memory controller */
2846 probe_uninorth();
2847
2848 /* Probe mac-io controllers */
2849 if (probe_macios()) {
2850 printk(KERN_WARNING "No mac-io chip found\n");
2851 return;
2852 }
2853
2854 /* Setup low-level i2c stuffs */
2855 pmac_init_low_i2c();
2856
2857 /* Probe machine type */
2858 if (probe_motherboard())
2859 printk(KERN_WARNING "Unknown PowerMac !\n");
2860
2861 /* Set some initial features (turn off some chips that will
2862 * be later turned on)
2863 */
2864 set_initial_features();
2865}
2866
2867int __init
2868pmac_feature_late_init(void)
2869{
2870 struct device_node* np;
2871
2872 /* Request some resources late */
2873 if (uninorth_node)
2874 request_OF_resource(uninorth_node, 0, NULL);
2875 np = find_devices("hammerhead");
2876 if (np)
2877 request_OF_resource(np, 0, NULL);
2878 np = find_devices("interrupt-controller");
2879 if (np)
2880 request_OF_resource(np, 0, NULL);
2881 return 0;
2882}
2883
2884device_initcall(pmac_feature_late_init);
2885
2886#ifdef CONFIG_POWER4
2887
2888static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2889{
2890 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2891 int bits[8] = { 8,16,0,32,2,4,0,0 };
2892 int freq = (frq >> 8) & 0xf;
2893
2894 if (freqs[freq] == 0)
2895 printk("%s: Unknown HT link frequency %x\n", name, freq);
2896 else
2897 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2898 name, freqs[freq],
2899 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2900}
2901
2902void __init pmac_check_ht_link(void)
2903{
2904 u32 ufreq, freq, ucfg, cfg;
2905 struct device_node *pcix_node;
2906 u8 px_bus, px_devfn;
2907 struct pci_controller *px_hose;
2908
2909 (void)in_be32(u3_ht + U3_HT_LINK_COMMAND);
2910 ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG);
2911 ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ);
2912 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2913
2914 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2915 if (pcix_node == NULL) {
2916 printk("No PCI-X bridge found\n");
2917 return;
2918 }
2919 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2920 printk("PCI-X bridge found but not matched to pci\n");
2921 return;
2922 }
2923 px_hose = pci_find_hose_for_OF_device(pcix_node);
2924 if (px_hose == NULL) {
2925 printk("PCI-X bridge found but not matched to host\n");
2926 return;
2927 }
2928 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2929 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2930 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2931 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2932 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2933 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2934}
2935
2936#endif /* CONFIG_POWER4 */
2937
2938/*
2939 * Early video resume hook
2940 */
2941
2942static void (*pmac_early_vresume_proc)(void *data);
2943static void *pmac_early_vresume_data;
2944
2945void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2946{
2947 if (_machine != _MACH_Pmac)
2948 return;
2949 preempt_disable();
2950 pmac_early_vresume_proc = proc;
2951 pmac_early_vresume_data = data;
2952 preempt_enable();
2953}
2954EXPORT_SYMBOL(pmac_set_early_video_resume);
2955
2956void pmac_call_early_video_resume(void)
2957{
2958 if (pmac_early_vresume_proc)
2959 pmac_early_vresume_proc(pmac_early_vresume_data);
2960}
2961
2962/*
2963 * AGP related suspend/resume code
2964 */
2965
2966static struct pci_dev *pmac_agp_bridge;
2967static int (*pmac_agp_suspend)(struct pci_dev *bridge);
2968static int (*pmac_agp_resume)(struct pci_dev *bridge);
2969
2970void pmac_register_agp_pm(struct pci_dev *bridge,
2971 int (*suspend)(struct pci_dev *bridge),
2972 int (*resume)(struct pci_dev *bridge))
2973{
2974 if (suspend || resume) {
2975 pmac_agp_bridge = bridge;
2976 pmac_agp_suspend = suspend;
2977 pmac_agp_resume = resume;
2978 return;
2979 }
2980 if (bridge != pmac_agp_bridge)
2981 return;
2982 pmac_agp_suspend = pmac_agp_resume = NULL;
2983 return;
2984}
2985EXPORT_SYMBOL(pmac_register_agp_pm);
2986
2987void pmac_suspend_agp_for_card(struct pci_dev *dev)
2988{
2989 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
2990 return;
2991 if (pmac_agp_bridge->bus != dev->bus)
2992 return;
2993 pmac_agp_suspend(pmac_agp_bridge);
2994}
2995EXPORT_SYMBOL(pmac_suspend_agp_for_card);
2996
2997void pmac_resume_agp_for_card(struct pci_dev *dev)
2998{
2999 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3000 return;
3001 if (pmac_agp_bridge->bus != dev->bus)
3002 return;
3003 pmac_agp_resume(pmac_agp_bridge);
3004}
3005EXPORT_SYMBOL(pmac_resume_agp_for_card);
diff --git a/arch/ppc/platforms/pmac_low_i2c.c b/arch/ppc/platforms/pmac_low_i2c.c
deleted file mode 100644
index 08583fce16..0000000000
--- a/arch/ppc/platforms/pmac_low_i2c.c
+++ /dev/null
@@ -1,511 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_low_i2c.c
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * This file contains some low-level i2c access routines that
12 * need to be used by various bits of the PowerMac platform code
13 * at times where the real asynchronous & interrupt driven driver
14 * cannot be used. The API borrows some semantics from the darwin
15 * driver in order to ease the implementation of the platform
16 * properties parser
17 */
18
19#include <linux/config.h>
20#include <linux/types.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <asm/keylargo.h>
28#include <asm/uninorth.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/machdep.h>
32#include <asm/pmac_low_i2c.h>
33
34#define MAX_LOW_I2C_HOST 4
35
36#if 1
37#define DBG(x...) do {\
38 printk(KERN_DEBUG "KW:" x); \
39 } while(0)
40#else
41#define DBGG(x...)
42#endif
43
44struct low_i2c_host;
45
46typedef int (*low_i2c_func_t)(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len);
47
48struct low_i2c_host
49{
50 struct device_node *np; /* OF device node */
51 struct semaphore mutex; /* Access mutex for use by i2c-keywest */
52 low_i2c_func_t func; /* Access function */
53 int is_open : 1; /* Poor man's access control */
54 int mode; /* Current mode */
55 int channel; /* Current channel */
56 int num_channels; /* Number of channels */
57 void __iomem * base; /* For keywest-i2c, base address */
58 int bsteps; /* And register stepping */
59 int speed; /* And speed */
60};
61
62static struct low_i2c_host low_i2c_hosts[MAX_LOW_I2C_HOST];
63
64/* No locking is necessary on allocation, we are running way before
65 * anything can race with us
66 */
67static struct low_i2c_host *find_low_i2c_host(struct device_node *np)
68{
69 int i;
70
71 for (i = 0; i < MAX_LOW_I2C_HOST; i++)
72 if (low_i2c_hosts[i].np == np)
73 return &low_i2c_hosts[i];
74 return NULL;
75}
76
77/*
78 *
79 * i2c-keywest implementation (UniNorth, U2, U3, Keylargo's)
80 *
81 */
82
83/*
84 * Keywest i2c definitions borrowed from drivers/i2c/i2c-keywest.h,
85 * should be moved somewhere in include/asm-ppc/
86 */
87/* Register indices */
88typedef enum {
89 reg_mode = 0,
90 reg_control,
91 reg_status,
92 reg_isr,
93 reg_ier,
94 reg_addr,
95 reg_subaddr,
96 reg_data
97} reg_t;
98
99
100/* Mode register */
101#define KW_I2C_MODE_100KHZ 0x00
102#define KW_I2C_MODE_50KHZ 0x01
103#define KW_I2C_MODE_25KHZ 0x02
104#define KW_I2C_MODE_DUMB 0x00
105#define KW_I2C_MODE_STANDARD 0x04
106#define KW_I2C_MODE_STANDARDSUB 0x08
107#define KW_I2C_MODE_COMBINED 0x0C
108#define KW_I2C_MODE_MODE_MASK 0x0C
109#define KW_I2C_MODE_CHAN_MASK 0xF0
110
111/* Control register */
112#define KW_I2C_CTL_AAK 0x01
113#define KW_I2C_CTL_XADDR 0x02
114#define KW_I2C_CTL_STOP 0x04
115#define KW_I2C_CTL_START 0x08
116
117/* Status register */
118#define KW_I2C_STAT_BUSY 0x01
119#define KW_I2C_STAT_LAST_AAK 0x02
120#define KW_I2C_STAT_LAST_RW 0x04
121#define KW_I2C_STAT_SDA 0x08
122#define KW_I2C_STAT_SCL 0x10
123
124/* IER & ISR registers */
125#define KW_I2C_IRQ_DATA 0x01
126#define KW_I2C_IRQ_ADDR 0x02
127#define KW_I2C_IRQ_STOP 0x04
128#define KW_I2C_IRQ_START 0x08
129#define KW_I2C_IRQ_MASK 0x0F
130
131/* State machine states */
132enum {
133 state_idle,
134 state_addr,
135 state_read,
136 state_write,
137 state_stop,
138 state_dead
139};
140
141#define WRONG_STATE(name) do {\
142 printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
143 name, __kw_state_names[state], isr); \
144 } while(0)
145
146static const char *__kw_state_names[] = {
147 "state_idle",
148 "state_addr",
149 "state_read",
150 "state_write",
151 "state_stop",
152 "state_dead"
153};
154
155static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg)
156{
157 return in_8(host->base + (((unsigned)reg) << host->bsteps));
158}
159
160static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val)
161{
162 out_8(host->base + (((unsigned)reg) << host->bsteps), val);
163 (void)__kw_read_reg(host, reg_subaddr);
164}
165
166#define kw_write_reg(reg, val) __kw_write_reg(host, reg, val)
167#define kw_read_reg(reg) __kw_read_reg(host, reg)
168
169
170/* Don't schedule, the g5 fan controller is too
171 * timing sensitive
172 */
173static u8 kw_wait_interrupt(struct low_i2c_host* host)
174{
175 int i;
176 u8 isr;
177
178 for (i = 0; i < 200000; i++) {
179 isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
180 if (isr != 0)
181 return isr;
182 udelay(1);
183 }
184 return isr;
185}
186
187static int kw_handle_interrupt(struct low_i2c_host *host, int state, int rw, int *rc, u8 **data, int *len, u8 isr)
188{
189 u8 ack;
190
191 if (isr == 0) {
192 if (state != state_stop) {
193 DBG("KW: Timeout !\n");
194 *rc = -EIO;
195 goto stop;
196 }
197 if (state == state_stop) {
198 ack = kw_read_reg(reg_status);
199 if (!(ack & KW_I2C_STAT_BUSY)) {
200 state = state_idle;
201 kw_write_reg(reg_ier, 0x00);
202 }
203 }
204 return state;
205 }
206
207 if (isr & KW_I2C_IRQ_ADDR) {
208 ack = kw_read_reg(reg_status);
209 if (state != state_addr) {
210 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
211 WRONG_STATE("KW_I2C_IRQ_ADDR");
212 *rc = -EIO;
213 goto stop;
214 }
215 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
216 *rc = -ENODEV;
217 DBG("KW: NAK on address\n");
218 return state_stop;
219 } else {
220 if (rw) {
221 state = state_read;
222 if (*len > 1)
223 kw_write_reg(reg_control, KW_I2C_CTL_AAK);
224 } else {
225 state = state_write;
226 kw_write_reg(reg_data, **data);
227 (*data)++; (*len)--;
228 }
229 }
230 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
231 }
232
233 if (isr & KW_I2C_IRQ_DATA) {
234 if (state == state_read) {
235 **data = kw_read_reg(reg_data);
236 (*data)++; (*len)--;
237 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
238 if ((*len) == 0)
239 state = state_stop;
240 else if ((*len) == 1)
241 kw_write_reg(reg_control, 0);
242 } else if (state == state_write) {
243 ack = kw_read_reg(reg_status);
244 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
245 DBG("KW: nack on data write\n");
246 *rc = -EIO;
247 goto stop;
248 } else if (*len) {
249 kw_write_reg(reg_data, **data);
250 (*data)++; (*len)--;
251 } else {
252 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
253 state = state_stop;
254 *rc = 0;
255 }
256 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
257 } else {
258 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
259 WRONG_STATE("KW_I2C_IRQ_DATA");
260 if (state != state_stop) {
261 *rc = -EIO;
262 goto stop;
263 }
264 }
265 }
266
267 if (isr & KW_I2C_IRQ_STOP) {
268 kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
269 if (state != state_stop) {
270 WRONG_STATE("KW_I2C_IRQ_STOP");
271 *rc = -EIO;
272 }
273 return state_idle;
274 }
275
276 if (isr & KW_I2C_IRQ_START)
277 kw_write_reg(reg_isr, KW_I2C_IRQ_START);
278
279 return state;
280
281 stop:
282 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
283 return state_stop;
284}
285
286static int keywest_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 subaddr, u8 *data, int len)
287{
288 u8 mode_reg = host->speed;
289 int state = state_addr;
290 int rc = 0;
291
292 /* Setup mode & subaddress if any */
293 switch(host->mode) {
294 case pmac_low_i2c_mode_dumb:
295 printk(KERN_ERR "low_i2c: Dumb mode not supported !\n");
296 return -EINVAL;
297 case pmac_low_i2c_mode_std:
298 mode_reg |= KW_I2C_MODE_STANDARD;
299 break;
300 case pmac_low_i2c_mode_stdsub:
301 mode_reg |= KW_I2C_MODE_STANDARDSUB;
302 kw_write_reg(reg_subaddr, subaddr);
303 break;
304 case pmac_low_i2c_mode_combined:
305 mode_reg |= KW_I2C_MODE_COMBINED;
306 kw_write_reg(reg_subaddr, subaddr);
307 break;
308 }
309
310 /* Setup channel & clear pending irqs */
311 kw_write_reg(reg_isr, kw_read_reg(reg_isr));
312 kw_write_reg(reg_mode, mode_reg | (host->channel << 4));
313 kw_write_reg(reg_status, 0);
314
315 /* Set up address and r/w bit */
316 kw_write_reg(reg_addr, addr);
317
318 /* Start sending address & disable interrupt*/
319 kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
320 kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
321
322 /* State machine, to turn into an interrupt handler */
323 while(state != state_idle) {
324 u8 isr = kw_wait_interrupt(host);
325 state = kw_handle_interrupt(host, state, addr & 1, &rc, &data, &len, isr);
326 }
327
328 return rc;
329}
330
331static void keywest_low_i2c_add(struct device_node *np)
332{
333 struct low_i2c_host *host = find_low_i2c_host(NULL);
334 unsigned long *psteps, *prate, steps, aoffset = 0;
335 struct device_node *parent;
336
337 if (host == NULL) {
338 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
339 np->full_name);
340 return;
341 }
342 memset(host, 0, sizeof(*host));
343
344 init_MUTEX(&host->mutex);
345 host->np = of_node_get(np);
346 psteps = (unsigned long *)get_property(np, "AAPL,address-step", NULL);
347 steps = psteps ? (*psteps) : 0x10;
348 for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
349 steps >>= 1;
350 parent = of_get_parent(np);
351 host->num_channels = 1;
352 if (parent && parent->name[0] == 'u') {
353 host->num_channels = 2;
354 aoffset = 3;
355 }
356 /* Select interface rate */
357 host->speed = KW_I2C_MODE_100KHZ;
358 prate = (unsigned long *)get_property(np, "AAPL,i2c-rate", NULL);
359 if (prate) switch(*prate) {
360 case 100:
361 host->speed = KW_I2C_MODE_100KHZ;
362 break;
363 case 50:
364 host->speed = KW_I2C_MODE_50KHZ;
365 break;
366 case 25:
367 host->speed = KW_I2C_MODE_25KHZ;
368 break;
369 }
370 host->mode = pmac_low_i2c_mode_std;
371 host->base = ioremap(np->addrs[0].address + aoffset,
372 np->addrs[0].size);
373 host->func = keywest_low_i2c_func;
374}
375
376/*
377 *
378 * PMU implementation
379 *
380 */
381
382
383#ifdef CONFIG_ADB_PMU
384
385static int pmu_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len)
386{
387 // TODO
388 return -ENODEV;
389}
390
391static void pmu_low_i2c_add(struct device_node *np)
392{
393 struct low_i2c_host *host = find_low_i2c_host(NULL);
394
395 if (host == NULL) {
396 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
397 np->full_name);
398 return;
399 }
400 memset(host, 0, sizeof(*host));
401
402 init_MUTEX(&host->mutex);
403 host->np = of_node_get(np);
404 host->num_channels = 3;
405 host->mode = pmac_low_i2c_mode_std;
406 host->func = pmu_low_i2c_func;
407}
408
409#endif /* CONFIG_ADB_PMU */
410
411void __init pmac_init_low_i2c(void)
412{
413 struct device_node *np;
414
415 /* Probe keywest-i2c busses */
416 np = of_find_compatible_node(NULL, "i2c", "keywest-i2c");
417 while(np) {
418 keywest_low_i2c_add(np);
419 np = of_find_compatible_node(np, "i2c", "keywest-i2c");
420 }
421
422#ifdef CONFIG_ADB_PMU
423 /* Probe PMU busses */
424 np = of_find_node_by_name(NULL, "via-pmu");
425 if (np)
426 pmu_low_i2c_add(np);
427#endif /* CONFIG_ADB_PMU */
428
429 /* TODO: Add CUDA support as well */
430}
431
432int pmac_low_i2c_lock(struct device_node *np)
433{
434 struct low_i2c_host *host = find_low_i2c_host(np);
435
436 if (!host)
437 return -ENODEV;
438 down(&host->mutex);
439 return 0;
440}
441EXPORT_SYMBOL(pmac_low_i2c_lock);
442
443int pmac_low_i2c_unlock(struct device_node *np)
444{
445 struct low_i2c_host *host = find_low_i2c_host(np);
446
447 if (!host)
448 return -ENODEV;
449 up(&host->mutex);
450 return 0;
451}
452EXPORT_SYMBOL(pmac_low_i2c_unlock);
453
454
455int pmac_low_i2c_open(struct device_node *np, int channel)
456{
457 struct low_i2c_host *host = find_low_i2c_host(np);
458
459 if (!host)
460 return -ENODEV;
461
462 if (channel >= host->num_channels)
463 return -EINVAL;
464
465 down(&host->mutex);
466 host->is_open = 1;
467 host->channel = channel;
468
469 return 0;
470}
471EXPORT_SYMBOL(pmac_low_i2c_open);
472
473int pmac_low_i2c_close(struct device_node *np)
474{
475 struct low_i2c_host *host = find_low_i2c_host(np);
476
477 if (!host)
478 return -ENODEV;
479
480 host->is_open = 0;
481 up(&host->mutex);
482
483 return 0;
484}
485EXPORT_SYMBOL(pmac_low_i2c_close);
486
487int pmac_low_i2c_setmode(struct device_node *np, int mode)
488{
489 struct low_i2c_host *host = find_low_i2c_host(np);
490
491 if (!host)
492 return -ENODEV;
493 WARN_ON(!host->is_open);
494 host->mode = mode;
495
496 return 0;
497}
498EXPORT_SYMBOL(pmac_low_i2c_setmode);
499
500int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len)
501{
502 struct low_i2c_host *host = find_low_i2c_host(np);
503
504 if (!host)
505 return -ENODEV;
506 WARN_ON(!host->is_open);
507
508 return host->func(host, addrdir, subaddr, data, len);
509}
510EXPORT_SYMBOL(pmac_low_i2c_xfer);
511
diff --git a/arch/ppc/platforms/pmac_nvram.c b/arch/ppc/platforms/pmac_nvram.c
deleted file mode 100644
index 8c9b008c72..0000000000
--- a/arch/ppc/platforms/pmac_nvram.c
+++ /dev/null
@@ -1,584 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_nvram.c
3 *
4 * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Todo: - add support for the OF persistent properties
12 */
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/stddef.h>
17#include <linux/string.h>
18#include <linux/nvram.h>
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/adb.h>
24#include <linux/pmu.h>
25#include <linux/bootmem.h>
26#include <linux/completion.h>
27#include <linux/spinlock.h>
28#include <asm/sections.h>
29#include <asm/io.h>
30#include <asm/system.h>
31#include <asm/prom.h>
32#include <asm/machdep.h>
33#include <asm/nvram.h>
34
35#define DEBUG
36
37#ifdef DEBUG
38#define DBG(x...) printk(x)
39#else
40#define DBG(x...)
41#endif
42
43#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
44
45#define CORE99_SIGNATURE 0x5a
46#define CORE99_ADLER_START 0x14
47
48/* On Core99, nvram is either a sharp, a micron or an AMD flash */
49#define SM_FLASH_STATUS_DONE 0x80
50#define SM_FLASH_STATUS_ERR 0x38
51#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
52#define SM_FLASH_CMD_ERASE_SETUP 0x20
53#define SM_FLASH_CMD_RESET 0xff
54#define SM_FLASH_CMD_WRITE_SETUP 0x40
55#define SM_FLASH_CMD_CLEAR_STATUS 0x50
56#define SM_FLASH_CMD_READ_STATUS 0x70
57
58/* CHRP NVRAM header */
59struct chrp_header {
60 u8 signature;
61 u8 cksum;
62 u16 len;
63 char name[12];
64 u8 data[0];
65};
66
67struct core99_header {
68 struct chrp_header hdr;
69 u32 adler;
70 u32 generation;
71 u32 reserved[2];
72};
73
74/*
75 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
76 */
77static int nvram_naddrs;
78static volatile unsigned char *nvram_addr;
79static volatile unsigned char *nvram_data;
80static int nvram_mult, is_core_99;
81static int core99_bank = 0;
82static int nvram_partitions[3];
83static DEFINE_SPINLOCK(nv_lock);
84
85extern int pmac_newworld;
86extern int system_running;
87
88static int (*core99_write_bank)(int bank, u8* datas);
89static int (*core99_erase_bank)(int bank);
90
91static char *nvram_image;
92
93
94static unsigned char core99_nvram_read_byte(int addr)
95{
96 if (nvram_image == NULL)
97 return 0xff;
98 return nvram_image[addr];
99}
100
101static void core99_nvram_write_byte(int addr, unsigned char val)
102{
103 if (nvram_image == NULL)
104 return;
105 nvram_image[addr] = val;
106}
107
108
109static unsigned char direct_nvram_read_byte(int addr)
110{
111 return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
112}
113
114static void direct_nvram_write_byte(int addr, unsigned char val)
115{
116 out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
117}
118
119
120static unsigned char indirect_nvram_read_byte(int addr)
121{
122 unsigned char val;
123 unsigned long flags;
124
125 spin_lock_irqsave(&nv_lock, flags);
126 out_8(nvram_addr, addr >> 5);
127 val = in_8(&nvram_data[(addr & 0x1f) << 4]);
128 spin_unlock_irqrestore(&nv_lock, flags);
129
130 return val;
131}
132
133static void indirect_nvram_write_byte(int addr, unsigned char val)
134{
135 unsigned long flags;
136
137 spin_lock_irqsave(&nv_lock, flags);
138 out_8(nvram_addr, addr >> 5);
139 out_8(&nvram_data[(addr & 0x1f) << 4], val);
140 spin_unlock_irqrestore(&nv_lock, flags);
141}
142
143
144#ifdef CONFIG_ADB_PMU
145
146static void pmu_nvram_complete(struct adb_request *req)
147{
148 if (req->arg)
149 complete((struct completion *)req->arg);
150}
151
152static unsigned char pmu_nvram_read_byte(int addr)
153{
154 struct adb_request req;
155 DECLARE_COMPLETION(req_complete);
156
157 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
158 if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
159 (addr >> 8) & 0xff, addr & 0xff))
160 return 0xff;
161 if (system_state == SYSTEM_RUNNING)
162 wait_for_completion(&req_complete);
163 while (!req.complete)
164 pmu_poll();
165 return req.reply[0];
166}
167
168static void pmu_nvram_write_byte(int addr, unsigned char val)
169{
170 struct adb_request req;
171 DECLARE_COMPLETION(req_complete);
172
173 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
174 if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
175 (addr >> 8) & 0xff, addr & 0xff, val))
176 return;
177 if (system_state == SYSTEM_RUNNING)
178 wait_for_completion(&req_complete);
179 while (!req.complete)
180 pmu_poll();
181}
182
183#endif /* CONFIG_ADB_PMU */
184
185
186static u8 chrp_checksum(struct chrp_header* hdr)
187{
188 u8 *ptr;
189 u16 sum = hdr->signature;
190 for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
191 sum += *ptr;
192 while (sum > 0xFF)
193 sum = (sum & 0xFF) + (sum>>8);
194 return sum;
195}
196
197static u32 core99_calc_adler(u8 *buffer)
198{
199 int cnt;
200 u32 low, high;
201
202 buffer += CORE99_ADLER_START;
203 low = 1;
204 high = 0;
205 for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
206 if ((cnt % 5000) == 0) {
207 high %= 65521UL;
208 high %= 65521UL;
209 }
210 low += buffer[cnt];
211 high += low;
212 }
213 low %= 65521UL;
214 high %= 65521UL;
215
216 return (high << 16) | low;
217}
218
219static u32 core99_check(u8* datas)
220{
221 struct core99_header* hdr99 = (struct core99_header*)datas;
222
223 if (hdr99->hdr.signature != CORE99_SIGNATURE) {
224 DBG("Invalid signature\n");
225 return 0;
226 }
227 if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
228 DBG("Invalid checksum\n");
229 return 0;
230 }
231 if (hdr99->adler != core99_calc_adler(datas)) {
232 DBG("Invalid adler\n");
233 return 0;
234 }
235 return hdr99->generation;
236}
237
238static int sm_erase_bank(int bank)
239{
240 int stat, i;
241 unsigned long timeout;
242
243 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
244
245 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
246
247 out_8(base, SM_FLASH_CMD_ERASE_SETUP);
248 out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
249 timeout = 0;
250 do {
251 if (++timeout > 1000000) {
252 printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
253 break;
254 }
255 out_8(base, SM_FLASH_CMD_READ_STATUS);
256 stat = in_8(base);
257 } while (!(stat & SM_FLASH_STATUS_DONE));
258
259 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
260 out_8(base, SM_FLASH_CMD_RESET);
261
262 for (i=0; i<NVRAM_SIZE; i++)
263 if (base[i] != 0xff) {
264 printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
265 return -ENXIO;
266 }
267 return 0;
268}
269
270static int sm_write_bank(int bank, u8* datas)
271{
272 int i, stat = 0;
273 unsigned long timeout;
274
275 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
276
277 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
278
279 for (i=0; i<NVRAM_SIZE; i++) {
280 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
281 udelay(1);
282 out_8(base+i, datas[i]);
283 timeout = 0;
284 do {
285 if (++timeout > 1000000) {
286 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
287 break;
288 }
289 out_8(base, SM_FLASH_CMD_READ_STATUS);
290 stat = in_8(base);
291 } while (!(stat & SM_FLASH_STATUS_DONE));
292 if (!(stat & SM_FLASH_STATUS_DONE))
293 break;
294 }
295 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
296 out_8(base, SM_FLASH_CMD_RESET);
297 for (i=0; i<NVRAM_SIZE; i++)
298 if (base[i] != datas[i]) {
299 printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
300 return -ENXIO;
301 }
302 return 0;
303}
304
305static int amd_erase_bank(int bank)
306{
307 int i, stat = 0;
308 unsigned long timeout;
309
310 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
311
312 DBG("nvram: AMD Erasing bank %d...\n", bank);
313
314 /* Unlock 1 */
315 out_8(base+0x555, 0xaa);
316 udelay(1);
317 /* Unlock 2 */
318 out_8(base+0x2aa, 0x55);
319 udelay(1);
320
321 /* Sector-Erase */
322 out_8(base+0x555, 0x80);
323 udelay(1);
324 out_8(base+0x555, 0xaa);
325 udelay(1);
326 out_8(base+0x2aa, 0x55);
327 udelay(1);
328 out_8(base, 0x30);
329 udelay(1);
330
331 timeout = 0;
332 do {
333 if (++timeout > 1000000) {
334 printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
335 break;
336 }
337 stat = in_8(base) ^ in_8(base);
338 } while (stat != 0);
339
340 /* Reset */
341 out_8(base, 0xf0);
342 udelay(1);
343
344 for (i=0; i<NVRAM_SIZE; i++)
345 if (base[i] != 0xff) {
346 printk(KERN_ERR "nvram: AMD flash erase failed !\n");
347 return -ENXIO;
348 }
349 return 0;
350}
351
352static int amd_write_bank(int bank, u8* datas)
353{
354 int i, stat = 0;
355 unsigned long timeout;
356
357 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
358
359 DBG("nvram: AMD Writing bank %d...\n", bank);
360
361 for (i=0; i<NVRAM_SIZE; i++) {
362 /* Unlock 1 */
363 out_8(base+0x555, 0xaa);
364 udelay(1);
365 /* Unlock 2 */
366 out_8(base+0x2aa, 0x55);
367 udelay(1);
368
369 /* Write single word */
370 out_8(base+0x555, 0xa0);
371 udelay(1);
372 out_8(base+i, datas[i]);
373
374 timeout = 0;
375 do {
376 if (++timeout > 1000000) {
377 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
378 break;
379 }
380 stat = in_8(base) ^ in_8(base);
381 } while (stat != 0);
382 if (stat != 0)
383 break;
384 }
385
386 /* Reset */
387 out_8(base, 0xf0);
388 udelay(1);
389
390 for (i=0; i<NVRAM_SIZE; i++)
391 if (base[i] != datas[i]) {
392 printk(KERN_ERR "nvram: AMD flash write failed !\n");
393 return -ENXIO;
394 }
395 return 0;
396}
397
398static void __init lookup_partitions(void)
399{
400 u8 buffer[17];
401 int i, offset;
402 struct chrp_header* hdr;
403
404 if (pmac_newworld) {
405 nvram_partitions[pmac_nvram_OF] = -1;
406 nvram_partitions[pmac_nvram_XPRAM] = -1;
407 nvram_partitions[pmac_nvram_NR] = -1;
408 hdr = (struct chrp_header *)buffer;
409
410 offset = 0;
411 buffer[16] = 0;
412 do {
413 for (i=0;i<16;i++)
414 buffer[i] = nvram_read_byte(offset+i);
415 if (!strcmp(hdr->name, "common"))
416 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
417 if (!strcmp(hdr->name, "APL,MacOS75")) {
418 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
419 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
420 }
421 offset += (hdr->len * 0x10);
422 } while(offset < NVRAM_SIZE);
423 } else {
424 nvram_partitions[pmac_nvram_OF] = 0x1800;
425 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
426 nvram_partitions[pmac_nvram_NR] = 0x1400;
427 }
428 DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
429 DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
430 DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
431}
432
433static void core99_nvram_sync(void)
434{
435 struct core99_header* hdr99;
436 unsigned long flags;
437
438 if (!is_core_99 || !nvram_data || !nvram_image)
439 return;
440
441 spin_lock_irqsave(&nv_lock, flags);
442 if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
443 NVRAM_SIZE))
444 goto bail;
445
446 DBG("Updating nvram...\n");
447
448 hdr99 = (struct core99_header*)nvram_image;
449 hdr99->generation++;
450 hdr99->hdr.signature = CORE99_SIGNATURE;
451 hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
452 hdr99->adler = core99_calc_adler(nvram_image);
453 core99_bank = core99_bank ? 0 : 1;
454 if (core99_erase_bank)
455 if (core99_erase_bank(core99_bank)) {
456 printk("nvram: Error erasing bank %d\n", core99_bank);
457 goto bail;
458 }
459 if (core99_write_bank)
460 if (core99_write_bank(core99_bank, nvram_image))
461 printk("nvram: Error writing bank %d\n", core99_bank);
462 bail:
463 spin_unlock_irqrestore(&nv_lock, flags);
464
465#ifdef DEBUG
466 mdelay(2000);
467#endif
468}
469
470void __init pmac_nvram_init(void)
471{
472 struct device_node *dp;
473
474 nvram_naddrs = 0;
475
476 dp = find_devices("nvram");
477 if (dp == NULL) {
478 printk(KERN_ERR "Can't find NVRAM device\n");
479 return;
480 }
481 nvram_naddrs = dp->n_addrs;
482 is_core_99 = device_is_compatible(dp, "nvram,flash");
483 if (is_core_99) {
484 int i;
485 u32 gen_bank0, gen_bank1;
486
487 if (nvram_naddrs < 1) {
488 printk(KERN_ERR "nvram: no address\n");
489 return;
490 }
491 nvram_image = alloc_bootmem(NVRAM_SIZE);
492 if (nvram_image == NULL) {
493 printk(KERN_ERR "nvram: can't allocate ram image\n");
494 return;
495 }
496 nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
497 nvram_naddrs = 1; /* Make sure we get the correct case */
498
499 DBG("nvram: Checking bank 0...\n");
500
501 gen_bank0 = core99_check((u8 *)nvram_data);
502 gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
503 core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
504
505 DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
506 DBG("nvram: Active bank is: %d\n", core99_bank);
507
508 for (i=0; i<NVRAM_SIZE; i++)
509 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
510
511 ppc_md.nvram_read_val = core99_nvram_read_byte;
512 ppc_md.nvram_write_val = core99_nvram_write_byte;
513 ppc_md.nvram_sync = core99_nvram_sync;
514 /*
515 * Maybe we could be smarter here though making an exclusive list
516 * of known flash chips is a bit nasty as older OF didn't provide us
517 * with a useful "compatible" entry. A solution would be to really
518 * identify the chip using flash id commands and base ourselves on
519 * a list of known chips IDs
520 */
521 if (device_is_compatible(dp, "amd-0137")) {
522 core99_erase_bank = amd_erase_bank;
523 core99_write_bank = amd_write_bank;
524 } else {
525 core99_erase_bank = sm_erase_bank;
526 core99_write_bank = sm_write_bank;
527 }
528 } else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
529 nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
530 dp->addrs[0].size);
531 nvram_mult = 1;
532 ppc_md.nvram_read_val = direct_nvram_read_byte;
533 ppc_md.nvram_write_val = direct_nvram_write_byte;
534 } else if (nvram_naddrs == 1) {
535 nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
536 nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
537 ppc_md.nvram_read_val = direct_nvram_read_byte;
538 ppc_md.nvram_write_val = direct_nvram_write_byte;
539 } else if (nvram_naddrs == 2) {
540 nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
541 nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
542 ppc_md.nvram_read_val = indirect_nvram_read_byte;
543 ppc_md.nvram_write_val = indirect_nvram_write_byte;
544 } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
545#ifdef CONFIG_ADB_PMU
546 nvram_naddrs = -1;
547 ppc_md.nvram_read_val = pmu_nvram_read_byte;
548 ppc_md.nvram_write_val = pmu_nvram_write_byte;
549#endif /* CONFIG_ADB_PMU */
550 } else {
551 printk(KERN_ERR "Don't know how to access NVRAM with %d addresses\n",
552 nvram_naddrs);
553 }
554 lookup_partitions();
555}
556
557int pmac_get_partition(int partition)
558{
559 return nvram_partitions[partition];
560}
561
562u8 pmac_xpram_read(int xpaddr)
563{
564 int offset = nvram_partitions[pmac_nvram_XPRAM];
565
566 if (offset < 0)
567 return 0xff;
568
569 return ppc_md.nvram_read_val(xpaddr + offset);
570}
571
572void pmac_xpram_write(int xpaddr, u8 data)
573{
574 int offset = nvram_partitions[pmac_nvram_XPRAM];
575
576 if (offset < 0)
577 return;
578
579 ppc_md.nvram_write_val(xpaddr + offset, data);
580}
581
582EXPORT_SYMBOL(pmac_get_partition);
583EXPORT_SYMBOL(pmac_xpram_read);
584EXPORT_SYMBOL(pmac_xpram_write);
diff --git a/arch/ppc/platforms/pmac_pci.c b/arch/ppc/platforms/pmac_pci.c
deleted file mode 100644
index 786295b6dd..0000000000
--- a/arch/ppc/platforms/pmac_pci.c
+++ /dev/null
@@ -1,1124 +0,0 @@
1/*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/pmac_feature.h>
27
28#undef DEBUG
29
30#ifdef DEBUG
31#ifdef CONFIG_XMON
32extern void xmon_printf(const char *fmt, ...);
33#define DBG(x...) xmon_printf(x)
34#else
35#define DBG(x...) printk(x)
36#endif
37#else
38#define DBG(x...)
39#endif
40
41static int add_bridge(struct device_node *dev);
42extern void pmac_check_ht_link(void);
43
44/* XXX Could be per-controller, but I don't think we risk anything by
45 * assuming we won't have both UniNorth and Bandit */
46static int has_uninorth;
47#ifdef CONFIG_POWER4
48static struct pci_controller *u3_agp;
49#endif /* CONFIG_POWER4 */
50
51extern u8 pci_cache_line_size;
52extern int pcibios_assign_bus_offset;
53
54struct device_node *k2_skiplist[2];
55
56/*
57 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
58 */
59#define BANDIT_DEVID_2 8
60#define BANDIT_REVID 3
61
62#define BANDIT_DEVNUM 11
63#define BANDIT_MAGIC 0x50
64#define BANDIT_COHERENT 0x40
65
66static int __init
67fixup_one_level_bus_range(struct device_node *node, int higher)
68{
69 for (; node != 0;node = node->sibling) {
70 int * bus_range;
71 unsigned int *class_code;
72 int len;
73
74 /* For PCI<->PCI bridges or CardBus bridges, we go down */
75 class_code = (unsigned int *) get_property(node, "class-code", NULL);
76 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
77 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
78 continue;
79 bus_range = (int *) get_property(node, "bus-range", &len);
80 if (bus_range != NULL && len > 2 * sizeof(int)) {
81 if (bus_range[1] > higher)
82 higher = bus_range[1];
83 }
84 higher = fixup_one_level_bus_range(node->child, higher);
85 }
86 return higher;
87}
88
89/* This routine fixes the "bus-range" property of all bridges in the
90 * system since they tend to have their "last" member wrong on macs
91 *
92 * Note that the bus numbers manipulated here are OF bus numbers, they
93 * are not Linux bus numbers.
94 */
95static void __init
96fixup_bus_range(struct device_node *bridge)
97{
98 int * bus_range;
99 int len;
100
101 /* Lookup the "bus-range" property for the hose */
102 bus_range = (int *) get_property(bridge, "bus-range", &len);
103 if (bus_range == NULL || len < 2 * sizeof(int)) {
104 printk(KERN_WARNING "Can't get bus-range for %s\n",
105 bridge->full_name);
106 return;
107 }
108 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
109}
110
111/*
112 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
113 *
114 * The "Bandit" version is present in all early PCI PowerMacs,
115 * and up to the first ones using Grackle. Some machines may
116 * have 2 bandit controllers (2 PCI busses).
117 *
118 * "Chaos" is used in some "Bandit"-type machines as a bridge
119 * for the separate display bus. It is accessed the same
120 * way as bandit, but cannot be probed for devices. It therefore
121 * has its own config access functions.
122 *
123 * The "UniNorth" version is present in all Core99 machines
124 * (iBook, G4, new IMacs, and all the recent Apple machines).
125 * It contains 3 controllers in one ASIC.
126 *
127 * The U3 is the bridge used on G5 machines. It contains an
128 * AGP bus which is dealt with the old UniNorth access routines
129 * and a HyperTransport bus which uses its own set of access
130 * functions.
131 */
132
133#define MACRISC_CFA0(devfn, off) \
134 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
135 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
136 | (((unsigned long)(off)) & 0xFCUL))
137
138#define MACRISC_CFA1(bus, devfn, off) \
139 ((((unsigned long)(bus)) << 16) \
140 |(((unsigned long)(devfn)) << 8) \
141 |(((unsigned long)(off)) & 0xFCUL) \
142 |1UL)
143
144static void volatile __iomem *
145macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
146{
147 unsigned int caddr;
148
149 if (bus == hose->first_busno) {
150 if (dev_fn < (11 << 3))
151 return NULL;
152 caddr = MACRISC_CFA0(dev_fn, offset);
153 } else
154 caddr = MACRISC_CFA1(bus, dev_fn, offset);
155
156 /* Uninorth will return garbage if we don't read back the value ! */
157 do {
158 out_le32(hose->cfg_addr, caddr);
159 } while (in_le32(hose->cfg_addr) != caddr);
160
161 offset &= has_uninorth ? 0x07 : 0x03;
162 return hose->cfg_data + offset;
163}
164
165static int
166macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
167 int len, u32 *val)
168{
169 struct pci_controller *hose = bus->sysdata;
170 void volatile __iomem *addr;
171
172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 if (!addr)
174 return PCIBIOS_DEVICE_NOT_FOUND;
175 /*
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
178 */
179 switch (len) {
180 case 1:
181 *val = in_8(addr);
182 break;
183 case 2:
184 *val = in_le16(addr);
185 break;
186 default:
187 *val = in_le32(addr);
188 break;
189 }
190 return PCIBIOS_SUCCESSFUL;
191}
192
193static int
194macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
195 int len, u32 val)
196{
197 struct pci_controller *hose = bus->sysdata;
198 void volatile __iomem *addr;
199
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
201 if (!addr)
202 return PCIBIOS_DEVICE_NOT_FOUND;
203 /*
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
206 */
207 switch (len) {
208 case 1:
209 out_8(addr, val);
210 (void) in_8(addr);
211 break;
212 case 2:
213 out_le16(addr, val);
214 (void) in_le16(addr);
215 break;
216 default:
217 out_le32(addr, val);
218 (void) in_le32(addr);
219 break;
220 }
221 return PCIBIOS_SUCCESSFUL;
222}
223
224static struct pci_ops macrisc_pci_ops =
225{
226 macrisc_read_config,
227 macrisc_write_config
228};
229
230/*
231 * Verifiy that a specific (bus, dev_fn) exists on chaos
232 */
233static int
234chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
235{
236 struct device_node *np;
237 u32 *vendor, *device;
238
239 np = pci_busdev_to_OF_node(bus, devfn);
240 if (np == NULL)
241 return PCIBIOS_DEVICE_NOT_FOUND;
242
243 vendor = (u32 *)get_property(np, "vendor-id", NULL);
244 device = (u32 *)get_property(np, "device-id", NULL);
245 if (vendor == NULL || device == NULL)
246 return PCIBIOS_DEVICE_NOT_FOUND;
247
248 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
250 return PCIBIOS_BAD_REGISTER_NUMBER;
251
252 return PCIBIOS_SUCCESSFUL;
253}
254
255static int
256chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
257 int len, u32 *val)
258{
259 int result = chaos_validate_dev(bus, devfn, offset);
260 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
261 *val = ~0U;
262 if (result != PCIBIOS_SUCCESSFUL)
263 return result;
264 return macrisc_read_config(bus, devfn, offset, len, val);
265}
266
267static int
268chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
269 int len, u32 val)
270{
271 int result = chaos_validate_dev(bus, devfn, offset);
272 if (result != PCIBIOS_SUCCESSFUL)
273 return result;
274 return macrisc_write_config(bus, devfn, offset, len, val);
275}
276
277static struct pci_ops chaos_pci_ops =
278{
279 chaos_read_config,
280 chaos_write_config
281};
282
283#ifdef CONFIG_POWER4
284
285/*
286 * These versions of U3 HyperTransport config space access ops do not
287 * implement self-view of the HT host yet
288 */
289
290#define U3_HT_CFA0(devfn, off) \
291 ((((unsigned long)devfn) << 8) | offset)
292#define U3_HT_CFA1(bus, devfn, off) \
293 (U3_HT_CFA0(devfn, off) \
294 + (((unsigned long)bus) << 16) \
295 + 0x01000000UL)
296
297static void volatile __iomem *
298u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset)
299{
300 if (bus == hose->first_busno) {
301 /* For now, we don't self probe U3 HT bridge */
302 if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 ||
303 PCI_SLOT(devfn) < 1)
304 return 0;
305 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
306 } else
307 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
308}
309
310static int
311u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
312 int len, u32 *val)
313{
314 struct pci_controller *hose = bus->sysdata;
315 void volatile __iomem *addr;
316 int i;
317
318 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
319 if (np == NULL)
320 return PCIBIOS_DEVICE_NOT_FOUND;
321
322 /*
323 * When a device in K2 is powered down, we die on config
324 * cycle accesses. Fix that here.
325 */
326 for (i=0; i<2; i++)
327 if (k2_skiplist[i] == np) {
328 switch (len) {
329 case 1:
330 *val = 0xff; break;
331 case 2:
332 *val = 0xffff; break;
333 default:
334 *val = 0xfffffffful; break;
335 }
336 return PCIBIOS_SUCCESSFUL;
337 }
338
339 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
340 if (!addr)
341 return PCIBIOS_DEVICE_NOT_FOUND;
342 /*
343 * Note: the caller has already checked that offset is
344 * suitably aligned and that len is 1, 2 or 4.
345 */
346 switch (len) {
347 case 1:
348 *val = in_8(addr);
349 break;
350 case 2:
351 *val = in_le16(addr);
352 break;
353 default:
354 *val = in_le32(addr);
355 break;
356 }
357 return PCIBIOS_SUCCESSFUL;
358}
359
360static int
361u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
362 int len, u32 val)
363{
364 struct pci_controller *hose = bus->sysdata;
365 void volatile __iomem *addr;
366 int i;
367
368 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
369 if (np == NULL)
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 /*
372 * When a device in K2 is powered down, we die on config
373 * cycle accesses. Fix that here.
374 */
375 for (i=0; i<2; i++)
376 if (k2_skiplist[i] == np)
377 return PCIBIOS_SUCCESSFUL;
378
379 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
380 if (!addr)
381 return PCIBIOS_DEVICE_NOT_FOUND;
382 /*
383 * Note: the caller has already checked that offset is
384 * suitably aligned and that len is 1, 2 or 4.
385 */
386 switch (len) {
387 case 1:
388 out_8(addr, val);
389 (void) in_8(addr);
390 break;
391 case 2:
392 out_le16(addr, val);
393 (void) in_le16(addr);
394 break;
395 default:
396 out_le32(addr, val);
397 (void) in_le32(addr);
398 break;
399 }
400 return PCIBIOS_SUCCESSFUL;
401}
402
403static struct pci_ops u3_ht_pci_ops =
404{
405 u3_ht_read_config,
406 u3_ht_write_config
407};
408
409#endif /* CONFIG_POWER4 */
410
411/*
412 * For a bandit bridge, turn on cache coherency if necessary.
413 * N.B. we could clean this up using the hose ops directly.
414 */
415static void __init
416init_bandit(struct pci_controller *bp)
417{
418 unsigned int vendev, magic;
419 int rev;
420
421 /* read the word at offset 0 in config space for device 11 */
422 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
423 udelay(2);
424 vendev = in_le32(bp->cfg_data);
425 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
426 PCI_VENDOR_ID_APPLE) {
427 /* read the revision id */
428 out_le32(bp->cfg_addr,
429 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
430 udelay(2);
431 rev = in_8(bp->cfg_data);
432 if (rev != BANDIT_REVID)
433 printk(KERN_WARNING
434 "Unknown revision %d for bandit\n", rev);
435 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
436 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
437 return;
438 }
439
440 /* read the word at offset 0x50 */
441 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
442 udelay(2);
443 magic = in_le32(bp->cfg_data);
444 if ((magic & BANDIT_COHERENT) != 0)
445 return;
446 magic |= BANDIT_COHERENT;
447 udelay(2);
448 out_le32(bp->cfg_data, magic);
449 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
450}
451
452
453/*
454 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
455 */
456static void __init
457init_p2pbridge(void)
458{
459 struct device_node *p2pbridge;
460 struct pci_controller* hose;
461 u8 bus, devfn;
462 u16 val;
463
464 /* XXX it would be better here to identify the specific
465 PCI-PCI bridge chip we have. */
466 if ((p2pbridge = find_devices("pci-bridge")) == 0
467 || p2pbridge->parent == NULL
468 || strcmp(p2pbridge->parent->name, "pci") != 0)
469 return;
470 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
471 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
472 return;
473 }
474 /* Warning: At this point, we have not yet renumbered all busses.
475 * So we must use OF walking to find out hose
476 */
477 hose = pci_find_hose_for_OF_device(p2pbridge);
478 if (!hose) {
479 DBG("Can't find hose for PCI<->PCI bridge\n");
480 return;
481 }
482 if (early_read_config_word(hose, bus, devfn,
483 PCI_BRIDGE_CONTROL, &val) < 0) {
484 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
485 return;
486 }
487 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
488 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
489}
490
491/*
492 * Some Apple desktop machines have a NEC PD720100A USB2 controller
493 * on the motherboard. Open Firmware, on these, will disable the
494 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
495 * code re-enables it ;)
496 */
497static void __init
498fixup_nec_usb2(void)
499{
500 struct device_node *nec;
501
502 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
503 struct pci_controller *hose;
504 u32 data, *prop;
505 u8 bus, devfn;
506
507 prop = (u32 *)get_property(nec, "vendor-id", NULL);
508 if (prop == NULL)
509 continue;
510 if (0x1033 != *prop)
511 continue;
512 prop = (u32 *)get_property(nec, "device-id", NULL);
513 if (prop == NULL)
514 continue;
515 if (0x0035 != *prop)
516 continue;
517 prop = (u32 *)get_property(nec, "reg", NULL);
518 if (prop == NULL)
519 continue;
520 devfn = (prop[0] >> 8) & 0xff;
521 bus = (prop[0] >> 16) & 0xff;
522 if (PCI_FUNC(devfn) != 0)
523 continue;
524 hose = pci_find_hose_for_OF_device(nec);
525 if (!hose)
526 continue;
527 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
528 if (data & 1UL) {
529 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
530 data &= ~1UL;
531 early_write_config_dword(hose, bus, devfn, 0xe4, data);
532 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
533 nec->intrs[0].line);
534 }
535 }
536}
537
538void __init
539pmac_find_bridges(void)
540{
541 struct device_node *np, *root;
542 struct device_node *ht = NULL;
543
544 root = of_find_node_by_path("/");
545 if (root == NULL) {
546 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
547 return;
548 }
549 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
550 if (np->name == NULL)
551 continue;
552 if (strcmp(np->name, "bandit") == 0
553 || strcmp(np->name, "chaos") == 0
554 || strcmp(np->name, "pci") == 0) {
555 if (add_bridge(np) == 0)
556 of_node_get(np);
557 }
558 if (strcmp(np->name, "ht") == 0) {
559 of_node_get(np);
560 ht = np;
561 }
562 }
563 of_node_put(root);
564
565 /* Probe HT last as it relies on the agp resources to be already
566 * setup
567 */
568 if (ht && add_bridge(ht) != 0)
569 of_node_put(ht);
570
571 init_p2pbridge();
572 fixup_nec_usb2();
573
574 /* We are still having some issues with the Xserve G4, enabling
575 * some offset between bus number and domains for now when we
576 * assign all busses should help for now
577 */
578 if (pci_assign_all_buses)
579 pcibios_assign_bus_offset = 0x10;
580
581#ifdef CONFIG_POWER4
582 /* There is something wrong with DMA on U3/HT. I haven't figured out
583 * the details yet, but if I set the cache line size to 128 bytes like
584 * it should, I'm getting memory corruption caused by devices like
585 * sungem (even without the MWI bit set, but maybe sungem doesn't
586 * care). Right now, it appears that setting up a 64 bytes line size
587 * works properly, 64 bytes beeing the max transfer size of HT, I
588 * suppose this is related the way HT/PCI are hooked together. I still
589 * need to dive into more specs though to be really sure of what's
590 * going on. --BenH.
591 *
592 * Ok, apparently, it's just that HT can't do more than 64 bytes
593 * transactions. MWI seem to be meaningless there as well, it may
594 * be worth nop'ing out pci_set_mwi too though I haven't done that
595 * yet.
596 *
597 * Note that it's a bit different for whatever is in the AGP slot.
598 * For now, I don't care, but this can become a real issue, we
599 * should probably hook pci_set_mwi anyway to make sure it sets
600 * the real cache line size in there.
601 */
602 if (machine_is_compatible("MacRISC4"))
603 pci_cache_line_size = 16; /* 64 bytes */
604
605 pmac_check_ht_link();
606#endif /* CONFIG_POWER4 */
607}
608
609#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
610 | (((o) & ~3) << 24))
611
612#define GRACKLE_PICR1_STG 0x00000040
613#define GRACKLE_PICR1_LOOPSNOOP 0x00000010
614
615/* N.B. this is called before bridges is initialized, so we can't
616 use grackle_pcibios_{read,write}_config_dword. */
617static inline void grackle_set_stg(struct pci_controller* bp, int enable)
618{
619 unsigned int val;
620
621 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
622 val = in_le32(bp->cfg_data);
623 val = enable? (val | GRACKLE_PICR1_STG) :
624 (val & ~GRACKLE_PICR1_STG);
625 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
626 out_le32(bp->cfg_data, val);
627 (void)in_le32(bp->cfg_data);
628}
629
630static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
631{
632 unsigned int val;
633
634 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
635 val = in_le32(bp->cfg_data);
636 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
637 (val & ~GRACKLE_PICR1_LOOPSNOOP);
638 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
639 out_le32(bp->cfg_data, val);
640 (void)in_le32(bp->cfg_data);
641}
642
643static int __init
644setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
645{
646 pci_assign_all_buses = 1;
647 has_uninorth = 1;
648 hose->ops = &macrisc_pci_ops;
649 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
650 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
651 /* We "know" that the bridge at f2000000 has the PCI slots. */
652 return addr->address == 0xf2000000;
653}
654
655static void __init
656setup_bandit(struct pci_controller* hose, struct reg_property* addr)
657{
658 hose->ops = &macrisc_pci_ops;
659 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
660 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
661 init_bandit(hose);
662}
663
664static void __init
665setup_chaos(struct pci_controller* hose, struct reg_property* addr)
666{
667 /* assume a `chaos' bridge */
668 hose->ops = &chaos_pci_ops;
669 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
670 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
671}
672
673#ifdef CONFIG_POWER4
674
675static void __init
676setup_u3_agp(struct pci_controller* hose, struct reg_property* addr)
677{
678 /* On G5, we move AGP up to high bus number so we don't need
679 * to reassign bus numbers for HT. If we ever have P2P bridges
680 * on AGP, we'll have to move pci_assign_all_buses to the
681 * pci_controller structure so we enable it for AGP and not for
682 * HT childs.
683 * We hard code the address because of the different size of
684 * the reg address cell, we shall fix that by killing struct
685 * reg_property and using some accessor functions instead
686 */
687 hose->first_busno = 0xf0;
688 hose->last_busno = 0xff;
689 has_uninorth = 1;
690 hose->ops = &macrisc_pci_ops;
691 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
692 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
693
694 u3_agp = hose;
695}
696
697static void __init
698setup_u3_ht(struct pci_controller* hose, struct reg_property *addr)
699{
700 struct device_node *np = (struct device_node *)hose->arch_data;
701 int i, cur;
702
703 hose->ops = &u3_ht_pci_ops;
704
705 /* We hard code the address because of the different size of
706 * the reg address cell, we shall fix that by killing struct
707 * reg_property and using some accessor functions instead
708 */
709 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
710
711 /*
712 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
713 * have been allocated to AGP. So far, this version of the code doesn't assign
714 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
715 * We need to fix that sooner or later by either parsing all child "ranges"
716 * properties or figuring out the U3 address space decoding logic and
717 * then read its configuration register (if any).
718 */
719 hose->io_base_phys = 0xf4000000;
720 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
721 isa_io_base = (unsigned long) hose->io_base_virt;
722 hose->io_resource.name = np->full_name;
723 hose->io_resource.start = 0;
724 hose->io_resource.end = 0x003fffff;
725 hose->io_resource.flags = IORESOURCE_IO;
726 hose->pci_mem_offset = 0;
727 hose->first_busno = 0;
728 hose->last_busno = 0xef;
729 hose->mem_resources[0].name = np->full_name;
730 hose->mem_resources[0].start = 0x80000000;
731 hose->mem_resources[0].end = 0xefffffff;
732 hose->mem_resources[0].flags = IORESOURCE_MEM;
733
734 if (u3_agp == NULL) {
735 DBG("U3 has no AGP, using full resource range\n");
736 return;
737 }
738
739 /* We "remove" the AGP resources from the resources allocated to HT, that
740 * is we create "holes". However, that code does assumptions that so far
741 * happen to be true (cross fingers...), typically that resources in the
742 * AGP node are properly ordered
743 */
744 cur = 0;
745 for (i=0; i<3; i++) {
746 struct resource *res = &u3_agp->mem_resources[i];
747 if (res->flags != IORESOURCE_MEM)
748 continue;
749 /* We don't care about "fine" resources */
750 if (res->start >= 0xf0000000)
751 continue;
752 /* Check if it's just a matter of "shrinking" us in one direction */
753 if (hose->mem_resources[cur].start == res->start) {
754 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
755 cur, hose->mem_resources[cur].start, res->end + 1);
756 hose->mem_resources[cur].start = res->end + 1;
757 continue;
758 }
759 if (hose->mem_resources[cur].end == res->end) {
760 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
761 cur, hose->mem_resources[cur].end, res->start - 1);
762 hose->mem_resources[cur].end = res->start - 1;
763 continue;
764 }
765 /* No, it's not the case, we need a hole */
766 if (cur == 2) {
767 /* not enough resources to make a hole, we drop part of the range */
768 printk(KERN_WARNING "Running out of resources for /ht host !\n");
769 hose->mem_resources[cur].end = res->start - 1;
770 continue;
771 }
772 cur++;
773 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
774 cur-1, res->start - 1, cur, res->end + 1);
775 hose->mem_resources[cur].name = np->full_name;
776 hose->mem_resources[cur].flags = IORESOURCE_MEM;
777 hose->mem_resources[cur].start = res->end + 1;
778 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
779 hose->mem_resources[cur-1].end = res->start - 1;
780 }
781}
782
783#endif /* CONFIG_POWER4 */
784
785void __init
786setup_grackle(struct pci_controller *hose)
787{
788 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
789 if (machine_is_compatible("AAPL,PowerBook1998"))
790 grackle_set_loop_snoop(hose, 1);
791#if 0 /* Disabled for now, HW problems ??? */
792 grackle_set_stg(hose, 1);
793#endif
794}
795
796/*
797 * We assume that if we have a G3 powermac, we have one bridge called
798 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
799 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
800 */
801static int __init
802add_bridge(struct device_node *dev)
803{
804 int len;
805 struct pci_controller *hose;
806 struct reg_property *addr;
807 char* disp_name;
808 int *bus_range;
809 int primary = 1;
810
811 DBG("Adding PCI host bridge %s\n", dev->full_name);
812
813 addr = (struct reg_property *) get_property(dev, "reg", &len);
814 if (addr == NULL || len < sizeof(*addr)) {
815 printk(KERN_WARNING "Can't use %s: no address\n",
816 dev->full_name);
817 return -ENODEV;
818 }
819 bus_range = (int *) get_property(dev, "bus-range", &len);
820 if (bus_range == NULL || len < 2 * sizeof(int)) {
821 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
822 dev->full_name);
823 }
824
825 hose = pcibios_alloc_controller();
826 if (!hose)
827 return -ENOMEM;
828 hose->arch_data = dev;
829 hose->first_busno = bus_range ? bus_range[0] : 0;
830 hose->last_busno = bus_range ? bus_range[1] : 0xff;
831
832 disp_name = NULL;
833#ifdef CONFIG_POWER4
834 if (device_is_compatible(dev, "u3-agp")) {
835 setup_u3_agp(hose, addr);
836 disp_name = "U3-AGP";
837 primary = 0;
838 } else if (device_is_compatible(dev, "u3-ht")) {
839 setup_u3_ht(hose, addr);
840 disp_name = "U3-HT";
841 primary = 1;
842 } else
843#endif /* CONFIG_POWER4 */
844 if (device_is_compatible(dev, "uni-north")) {
845 primary = setup_uninorth(hose, addr);
846 disp_name = "UniNorth";
847 } else if (strcmp(dev->name, "pci") == 0) {
848 /* XXX assume this is a mpc106 (grackle) */
849 setup_grackle(hose);
850 disp_name = "Grackle (MPC106)";
851 } else if (strcmp(dev->name, "bandit") == 0) {
852 setup_bandit(hose, addr);
853 disp_name = "Bandit";
854 } else if (strcmp(dev->name, "chaos") == 0) {
855 setup_chaos(hose, addr);
856 disp_name = "Chaos";
857 primary = 0;
858 }
859 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
860 disp_name, addr->address, hose->first_busno, hose->last_busno);
861 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
862 hose, hose->cfg_addr, hose->cfg_data);
863
864 /* Interpret the "ranges" property */
865 /* This also maps the I/O region and sets isa_io/mem_base */
866 pci_process_bridge_OF_ranges(hose, dev, primary);
867
868 /* Fixup "bus-range" OF property */
869 fixup_bus_range(dev);
870
871 return 0;
872}
873
874static void __init
875pcibios_fixup_OF_interrupts(void)
876{
877 struct pci_dev* dev = NULL;
878
879 /*
880 * Open Firmware often doesn't initialize the
881 * PCI_INTERRUPT_LINE config register properly, so we
882 * should find the device node and apply the interrupt
883 * obtained from the OF device-tree
884 */
885 for_each_pci_dev(dev) {
886 struct device_node *node;
887 node = pci_device_to_OF_node(dev);
888 /* this is the node, see if it has interrupts */
889 if (node && node->n_intrs > 0)
890 dev->irq = node->intrs[0].line;
891 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
892 }
893}
894
895void __init
896pmac_pcibios_fixup(void)
897{
898 /* Fixup interrupts according to OF tree */
899 pcibios_fixup_OF_interrupts();
900}
901
902int
903pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
904{
905 struct device_node* node;
906 int updatecfg = 0;
907 int uninorth_child;
908
909 node = pci_device_to_OF_node(dev);
910
911 /* We don't want to enable USB controllers absent from the OF tree
912 * (iBook second controller)
913 */
914 if (dev->vendor == PCI_VENDOR_ID_APPLE
915 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
916 && !node) {
917 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
918 pci_name(dev));
919 return -EINVAL;
920 }
921
922 if (!node)
923 return 0;
924
925 uninorth_child = node->parent &&
926 device_is_compatible(node->parent, "uni-north");
927
928 /* Firewire & GMAC were disabled after PCI probe, the driver is
929 * claiming them, we must re-enable them now.
930 */
931 if (uninorth_child && !strcmp(node->name, "firewire") &&
932 (device_is_compatible(node, "pci106b,18") ||
933 device_is_compatible(node, "pci106b,30") ||
934 device_is_compatible(node, "pci11c1,5811"))) {
935 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
936 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
937 updatecfg = 1;
938 }
939 if (uninorth_child && !strcmp(node->name, "ethernet") &&
940 device_is_compatible(node, "gmac")) {
941 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
942 updatecfg = 1;
943 }
944
945 if (updatecfg) {
946 u16 cmd;
947
948 /*
949 * Make sure PCI is correctly configured
950 *
951 * We use old pci_bios versions of the function since, by
952 * default, gmac is not powered up, and so will be absent
953 * from the kernel initial PCI lookup.
954 *
955 * Should be replaced by 2.4 new PCI mechanisms and really
956 * register the device.
957 */
958 pci_read_config_word(dev, PCI_COMMAND, &cmd);
959 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
960 pci_write_config_word(dev, PCI_COMMAND, cmd);
961 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
962 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
963 }
964
965 return 0;
966}
967
968/* We power down some devices after they have been probed. They'll
969 * be powered back on later on
970 */
971void __init
972pmac_pcibios_after_init(void)
973{
974 struct device_node* nd;
975
976#ifdef CONFIG_BLK_DEV_IDE
977 struct pci_dev *dev = NULL;
978
979 /* OF fails to initialize IDE controllers on macs
980 * (and maybe other machines)
981 *
982 * Ideally, this should be moved to the IDE layer, but we need
983 * to check specifically with Andre Hedrick how to do it cleanly
984 * since the common IDE code seem to care about the fact that the
985 * BIOS may have disabled a controller.
986 *
987 * -- BenH
988 */
989 for_each_pci_dev(dev) {
990 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
991 pci_enable_device(dev);
992 }
993#endif /* CONFIG_BLK_DEV_IDE */
994
995 nd = find_devices("firewire");
996 while (nd) {
997 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
998 device_is_compatible(nd, "pci106b,30") ||
999 device_is_compatible(nd, "pci11c1,5811"))
1000 && device_is_compatible(nd->parent, "uni-north")) {
1001 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1002 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1003 }
1004 nd = nd->next;
1005 }
1006 nd = find_devices("ethernet");
1007 while (nd) {
1008 if (nd->parent && device_is_compatible(nd, "gmac")
1009 && device_is_compatible(nd->parent, "uni-north"))
1010 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1011 nd = nd->next;
1012 }
1013}
1014
1015void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1016{
1017 if (_machine != _MACH_Pmac)
1018 return;
1019 /*
1020 * Fix the interrupt routing on the various cardbus bridges
1021 * used on powerbooks
1022 */
1023 if (dev->vendor != PCI_VENDOR_ID_TI)
1024 return;
1025 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1026 dev->device == PCI_DEVICE_ID_TI_1131) {
1027 u8 val;
1028 /* Enable PCI interrupt */
1029 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1030 pci_write_config_byte(dev, 0x91, val | 0x30);
1031 /* Disable ISA interrupt mode */
1032 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1033 pci_write_config_byte(dev, 0x92, val & ~0x06);
1034 }
1035 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1036 dev->device == PCI_DEVICE_ID_TI_1211 ||
1037 dev->device == PCI_DEVICE_ID_TI_1410 ||
1038 dev->device == PCI_DEVICE_ID_TI_1510) {
1039 u8 val;
1040 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1041 signal out the MFUNC0 pin */
1042 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1043 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1044 /* Disable ISA interrupt mode */
1045 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1046 pci_write_config_byte(dev, 0x92, val & ~0x06);
1047 }
1048}
1049
1050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1051
1052void pmac_pci_fixup_pciata(struct pci_dev* dev)
1053{
1054 u8 progif = 0;
1055
1056 /*
1057 * On PowerMacs, we try to switch any PCI ATA controller to
1058 * fully native mode
1059 */
1060 if (_machine != _MACH_Pmac)
1061 return;
1062 /* Some controllers don't have the class IDE */
1063 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1064 switch(dev->device) {
1065 case PCI_DEVICE_ID_PROMISE_20246:
1066 case PCI_DEVICE_ID_PROMISE_20262:
1067 case PCI_DEVICE_ID_PROMISE_20263:
1068 case PCI_DEVICE_ID_PROMISE_20265:
1069 case PCI_DEVICE_ID_PROMISE_20267:
1070 case PCI_DEVICE_ID_PROMISE_20268:
1071 case PCI_DEVICE_ID_PROMISE_20269:
1072 case PCI_DEVICE_ID_PROMISE_20270:
1073 case PCI_DEVICE_ID_PROMISE_20271:
1074 case PCI_DEVICE_ID_PROMISE_20275:
1075 case PCI_DEVICE_ID_PROMISE_20276:
1076 case PCI_DEVICE_ID_PROMISE_20277:
1077 goto good;
1078 }
1079 /* Others, check PCI class */
1080 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1081 return;
1082 good:
1083 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1084 if ((progif & 5) != 5) {
1085 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1086 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1087 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1088 (progif & 5) != 5)
1089 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1090 }
1091}
1092DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1093
1094
1095/*
1096 * Disable second function on K2-SATA, it's broken
1097 * and disable IO BARs on first one
1098 */
1099void pmac_pci_fixup_k2_sata(struct pci_dev* dev)
1100{
1101 int i;
1102 u16 cmd;
1103
1104 if (PCI_FUNC(dev->devfn) > 0) {
1105 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1106 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1107 pci_write_config_word(dev, PCI_COMMAND, cmd);
1108 for (i = 0; i < 6; i++) {
1109 dev->resource[i].start = dev->resource[i].end = 0;
1110 dev->resource[i].flags = 0;
1111 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1112 }
1113 } else {
1114 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1115 cmd &= ~PCI_COMMAND_IO;
1116 pci_write_config_word(dev, PCI_COMMAND, cmd);
1117 for (i = 0; i < 5; i++) {
1118 dev->resource[i].start = dev->resource[i].end = 0;
1119 dev->resource[i].flags = 0;
1120 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1121 }
1122 }
1123}
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata);
diff --git a/arch/ppc/platforms/pmac_pic.c b/arch/ppc/platforms/pmac_pic.c
deleted file mode 100644
index 4742bf6093..0000000000
--- a/arch/ppc/platforms/pmac_pic.c
+++ /dev/null
@@ -1,693 +0,0 @@
1/*
2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
5 * in a separate file
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/stddef.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/signal.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h>
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29#include <asm/sections.h>
30#include <asm/io.h>
31#include <asm/smp.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/time.h>
35#include <asm/open_pic.h>
36#include <asm/xmon.h>
37#include <asm/pmac_feature.h>
38#include <asm/machdep.h>
39
40#include "pmac_pic.h"
41
42/*
43 * XXX this should be in xmon.h, but putting it there means xmon.h
44 * has to include <linux/interrupt.h> (to get irqreturn_t), which
45 * causes all sorts of problems. -- paulus
46 */
47extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
48
49struct pmac_irq_hw {
50 unsigned int event;
51 unsigned int enable;
52 unsigned int ack;
53 unsigned int level;
54};
55
56/* Default addresses */
57static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
58 (struct pmac_irq_hw *) 0xf3000020,
59 (struct pmac_irq_hw *) 0xf3000010,
60 (struct pmac_irq_hw *) 0xf4000020,
61 (struct pmac_irq_hw *) 0xf4000010,
62};
63
64#define GC_LEVEL_MASK 0x3ff00000
65#define OHARE_LEVEL_MASK 0x1ff00000
66#define HEATHROW_LEVEL_MASK 0x1ff00000
67
68static int max_irqs;
69static int max_real_irqs;
70static u32 level_mask[4];
71
72static DEFINE_SPINLOCK(pmac_pic_lock);
73
74
75#define GATWICK_IRQ_POOL_SIZE 10
76static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
77
78#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
79static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
80
81/*
82 * Mark an irq as "lost". This is only used on the pmac
83 * since it can lose interrupts (see pmac_set_irq_mask).
84 * -- Cort
85 */
86void
87__set_lost(unsigned long irq_nr, int nokick)
88{
89 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
90 atomic_inc(&ppc_n_lost_interrupts);
91 if (!nokick)
92 set_dec(1);
93 }
94}
95
96static void
97pmac_mask_and_ack_irq(unsigned int irq_nr)
98{
99 unsigned long bit = 1UL << (irq_nr & 0x1f);
100 int i = irq_nr >> 5;
101 unsigned long flags;
102
103 if ((unsigned)irq_nr >= max_irqs)
104 return;
105
106 clear_bit(irq_nr, ppc_cached_irq_mask);
107 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
108 atomic_dec(&ppc_n_lost_interrupts);
109 spin_lock_irqsave(&pmac_pic_lock, flags);
110 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
111 out_le32(&pmac_irq_hw[i]->ack, bit);
112 do {
113 /* make sure ack gets to controller before we enable
114 interrupts */
115 mb();
116 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
117 != (ppc_cached_irq_mask[i] & bit));
118 spin_unlock_irqrestore(&pmac_pic_lock, flags);
119}
120
121static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
122{
123 unsigned long bit = 1UL << (irq_nr & 0x1f);
124 int i = irq_nr >> 5;
125 unsigned long flags;
126
127 if ((unsigned)irq_nr >= max_irqs)
128 return;
129
130 spin_lock_irqsave(&pmac_pic_lock, flags);
131 /* enable unmasked interrupts */
132 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
133
134 do {
135 /* make sure mask gets to controller before we
136 return to user */
137 mb();
138 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
139 != (ppc_cached_irq_mask[i] & bit));
140
141 /*
142 * Unfortunately, setting the bit in the enable register
143 * when the device interrupt is already on *doesn't* set
144 * the bit in the flag register or request another interrupt.
145 */
146 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
147 __set_lost((ulong)irq_nr, nokicklost);
148 spin_unlock_irqrestore(&pmac_pic_lock, flags);
149}
150
151/* When an irq gets requested for the first client, if it's an
152 * edge interrupt, we clear any previous one on the controller
153 */
154static unsigned int pmac_startup_irq(unsigned int irq_nr)
155{
156 unsigned long bit = 1UL << (irq_nr & 0x1f);
157 int i = irq_nr >> 5;
158
159 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
160 out_le32(&pmac_irq_hw[i]->ack, bit);
161 set_bit(irq_nr, ppc_cached_irq_mask);
162 pmac_set_irq_mask(irq_nr, 0);
163
164 return 0;
165}
166
167static void pmac_mask_irq(unsigned int irq_nr)
168{
169 clear_bit(irq_nr, ppc_cached_irq_mask);
170 pmac_set_irq_mask(irq_nr, 0);
171 mb();
172}
173
174static void pmac_unmask_irq(unsigned int irq_nr)
175{
176 set_bit(irq_nr, ppc_cached_irq_mask);
177 pmac_set_irq_mask(irq_nr, 0);
178}
179
180static void pmac_end_irq(unsigned int irq_nr)
181{
182 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
183 && irq_desc[irq_nr].action) {
184 set_bit(irq_nr, ppc_cached_irq_mask);
185 pmac_set_irq_mask(irq_nr, 1);
186 }
187}
188
189
190struct hw_interrupt_type pmac_pic = {
191 .typename = " PMAC-PIC ",
192 .startup = pmac_startup_irq,
193 .enable = pmac_unmask_irq,
194 .disable = pmac_mask_irq,
195 .ack = pmac_mask_and_ack_irq,
196 .end = pmac_end_irq,
197};
198
199struct hw_interrupt_type gatwick_pic = {
200 .typename = " GATWICK ",
201 .startup = pmac_startup_irq,
202 .enable = pmac_unmask_irq,
203 .disable = pmac_mask_irq,
204 .ack = pmac_mask_and_ack_irq,
205 .end = pmac_end_irq,
206};
207
208static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
209{
210 int irq, bits;
211
212 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
213 int i = irq >> 5;
214 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
215 /* We must read level interrupts from the level register */
216 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
217 bits &= ppc_cached_irq_mask[i];
218 if (bits == 0)
219 continue;
220 irq += __ilog2(bits);
221 __do_IRQ(irq, regs);
222 return IRQ_HANDLED;
223 }
224 printk("gatwick irq not from gatwick pic\n");
225 return IRQ_NONE;
226}
227
228int
229pmac_get_irq(struct pt_regs *regs)
230{
231 int irq;
232 unsigned long bits = 0;
233
234#ifdef CONFIG_SMP
235 void psurge_smp_message_recv(struct pt_regs *);
236
237 /* IPI's are a hack on the powersurge -- Cort */
238 if ( smp_processor_id() != 0 ) {
239 psurge_smp_message_recv(regs);
240 return -2; /* ignore, already handled */
241 }
242#endif /* CONFIG_SMP */
243 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
244 int i = irq >> 5;
245 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
246 /* We must read level interrupts from the level register */
247 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
248 bits &= ppc_cached_irq_mask[i];
249 if (bits == 0)
250 continue;
251 irq += __ilog2(bits);
252 break;
253 }
254
255 return irq;
256}
257
258/* This routine will fix some missing interrupt values in the device tree
259 * on the gatwick mac-io controller used by some PowerBooks
260 */
261static void __init
262pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
263{
264 struct device_node *node;
265 int count;
266
267 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
268 node = gw->child;
269 count = 0;
270 while(node)
271 {
272 /* Fix SCC */
273 if (strcasecmp(node->name, "escc") == 0)
274 if (node->child) {
275 if (node->child->n_intrs < 3) {
276 node->child->intrs = &gatwick_int_pool[count];
277 count += 3;
278 }
279 node->child->n_intrs = 3;
280 node->child->intrs[0].line = 15+irq_base;
281 node->child->intrs[1].line = 4+irq_base;
282 node->child->intrs[2].line = 5+irq_base;
283 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
284 node->child->intrs[0].line,
285 node->child->intrs[1].line,
286 node->child->intrs[2].line);
287 }
288 /* Fix media-bay & left SWIM */
289 if (strcasecmp(node->name, "media-bay") == 0) {
290 struct device_node* ya_node;
291
292 if (node->n_intrs == 0)
293 node->intrs = &gatwick_int_pool[count++];
294 node->n_intrs = 1;
295 node->intrs[0].line = 29+irq_base;
296 printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
297 node->intrs[0].line);
298
299 ya_node = node->child;
300 while(ya_node)
301 {
302 if (strcasecmp(ya_node->name, "floppy") == 0) {
303 if (ya_node->n_intrs < 2) {
304 ya_node->intrs = &gatwick_int_pool[count];
305 count += 2;
306 }
307 ya_node->n_intrs = 2;
308 ya_node->intrs[0].line = 19+irq_base;
309 ya_node->intrs[1].line = 1+irq_base;
310 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
311 ya_node->intrs[0].line, ya_node->intrs[1].line);
312 }
313 if (strcasecmp(ya_node->name, "ata4") == 0) {
314 if (ya_node->n_intrs < 2) {
315 ya_node->intrs = &gatwick_int_pool[count];
316 count += 2;
317 }
318 ya_node->n_intrs = 2;
319 ya_node->intrs[0].line = 14+irq_base;
320 ya_node->intrs[1].line = 3+irq_base;
321 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
322 ya_node->intrs[0].line, ya_node->intrs[1].line);
323 }
324 ya_node = ya_node->sibling;
325 }
326 }
327 node = node->sibling;
328 }
329 if (count > 10) {
330 printk("WARNING !! Gatwick interrupt pool overflow\n");
331 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
332 printk(" requested = %d\n", count);
333 }
334}
335
336/*
337 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
338 * card which includes an ohare chip that acts as a second interrupt
339 * controller. If we find this second ohare, set it up and fix the
340 * interrupt value in the device tree for the ethernet chip.
341 */
342static int __init enable_second_ohare(void)
343{
344 unsigned char bus, devfn;
345 unsigned short cmd;
346 unsigned long addr;
347 struct device_node *irqctrler = find_devices("pci106b,7");
348 struct device_node *ether;
349
350 if (irqctrler == NULL || irqctrler->n_addrs <= 0)
351 return -1;
352 addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
353 pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
354 max_irqs = 64;
355 if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
356 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
357 if (!hose)
358 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
359 else {
360 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
361 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
362 cmd &= ~PCI_COMMAND_IO;
363 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
364 }
365 }
366
367 /* Fix interrupt for the modem/ethernet combo controller. The number
368 in the device tree (27) is bogus (correct for the ethernet-only
369 board but not the combo ethernet/modem board).
370 The real interrupt is 28 on the second controller -> 28+32 = 60.
371 */
372 ether = find_devices("pci1011,14");
373 if (ether && ether->n_intrs > 0) {
374 ether->intrs[0].line = 60;
375 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
376 ether->intrs[0].line);
377 }
378
379 /* Return the interrupt number of the cascade */
380 return irqctrler->intrs[0].line;
381}
382
383#ifdef CONFIG_POWER4
384static irqreturn_t k2u3_action(int cpl, void *dev_id, struct pt_regs *regs)
385{
386 int irq;
387
388 irq = openpic2_get_irq(regs);
389 if (irq != -1)
390 __do_IRQ(irq, regs);
391 return IRQ_HANDLED;
392}
393
394static struct irqaction k2u3_cascade_action = {
395 .handler = k2u3_action,
396 .flags = 0,
397 .mask = CPU_MASK_NONE,
398 .name = "U3->K2 Cascade",
399};
400#endif /* CONFIG_POWER4 */
401
402#ifdef CONFIG_XMON
403static struct irqaction xmon_action = {
404 .handler = xmon_irq,
405 .flags = 0,
406 .mask = CPU_MASK_NONE,
407 .name = "NMI - XMON"
408};
409#endif
410
411static struct irqaction gatwick_cascade_action = {
412 .handler = gatwick_action,
413 .flags = SA_INTERRUPT,
414 .mask = CPU_MASK_NONE,
415 .name = "cascade",
416};
417
418void __init pmac_pic_init(void)
419{
420 int i;
421 struct device_node *irqctrler = NULL;
422 struct device_node *irqctrler2 = NULL;
423 struct device_node *np;
424 unsigned long addr;
425 int irq_cascade = -1;
426
427 /* We first try to detect Apple's new Core99 chipset, since mac-io
428 * is quite different on those machines and contains an IBM MPIC2.
429 */
430 np = find_type_devices("open-pic");
431 while(np) {
432 if (np->parent && !strcmp(np->parent->name, "u3"))
433 irqctrler2 = np;
434 else
435 irqctrler = np;
436 np = np->next;
437 }
438 if (irqctrler != NULL)
439 {
440 if (irqctrler->n_addrs > 0)
441 {
442 unsigned char senses[128];
443
444 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
445 irqctrler->addrs[0].address);
446
447 prom_get_irq_senses(senses, 0, 128);
448 OpenPIC_InitSenses = senses;
449 OpenPIC_NumInitSenses = 128;
450 ppc_md.get_irq = openpic_get_irq;
451 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
452 OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
453 irqctrler->addrs[0].size);
454 openpic_init(0);
455
456#ifdef CONFIG_POWER4
457 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
458 irqctrler2->n_addrs > 0) {
459 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
460 irqctrler2->addrs[0].address,
461 irqctrler2->intrs[0].line);
462 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
463 OpenPIC2_Addr = ioremap(irqctrler2->addrs[0].address,
464 irqctrler2->addrs[0].size);
465 prom_get_irq_senses(senses, PMAC_OPENPIC2_OFFSET,
466 PMAC_OPENPIC2_OFFSET+128);
467 OpenPIC_InitSenses = senses;
468 OpenPIC_NumInitSenses = 128;
469 openpic2_init(PMAC_OPENPIC2_OFFSET);
470
471 if (setup_irq(irqctrler2->intrs[0].line,
472 &k2u3_cascade_action))
473 printk("Unable to get OpenPIC IRQ for cascade\n");
474 }
475#endif /* CONFIG_POWER4 */
476
477#ifdef CONFIG_XMON
478 {
479 struct device_node* pswitch;
480 int nmi_irq;
481
482 pswitch = find_devices("programmer-switch");
483 if (pswitch && pswitch->n_intrs) {
484 nmi_irq = pswitch->intrs[0].line;
485 openpic_init_nmi_irq(nmi_irq);
486 setup_irq(nmi_irq, &xmon_action);
487 }
488 }
489#endif /* CONFIG_XMON */
490 return;
491 }
492 irqctrler = NULL;
493 }
494
495 /* Get the level/edge settings, assume if it's not
496 * a Grand Central nor an OHare, then it's an Heathrow
497 * (or Paddington).
498 */
499 if (find_devices("gc"))
500 level_mask[0] = GC_LEVEL_MASK;
501 else if (find_devices("ohare")) {
502 level_mask[0] = OHARE_LEVEL_MASK;
503 /* We might have a second cascaded ohare */
504 level_mask[1] = OHARE_LEVEL_MASK;
505 } else {
506 level_mask[0] = HEATHROW_LEVEL_MASK;
507 level_mask[1] = 0;
508 /* We might have a second cascaded heathrow */
509 level_mask[2] = HEATHROW_LEVEL_MASK;
510 level_mask[3] = 0;
511 }
512
513 /*
514 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
515 * 1998 G3 Series PowerBooks have 128,
516 * other powermacs have 32.
517 * The combo ethernet/modem card for the Powerstar powerbooks
518 * (2400/3400/3500, ohare based) has a second ohare chip
519 * effectively making a total of 64.
520 */
521 max_irqs = max_real_irqs = 32;
522 irqctrler = find_devices("mac-io");
523 if (irqctrler)
524 {
525 max_real_irqs = 64;
526 if (irqctrler->next)
527 max_irqs = 128;
528 else
529 max_irqs = 64;
530 }
531 for ( i = 0; i < max_real_irqs ; i++ )
532 irq_desc[i].handler = &pmac_pic;
533
534 /* get addresses of first controller */
535 if (irqctrler) {
536 if (irqctrler->n_addrs > 0) {
537 addr = (unsigned long)
538 ioremap(irqctrler->addrs[0].address, 0x40);
539 for (i = 0; i < 2; ++i)
540 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
541 (addr + (2 - i) * 0x10);
542 }
543
544 /* get addresses of second controller */
545 irqctrler = irqctrler->next;
546 if (irqctrler && irqctrler->n_addrs > 0) {
547 addr = (unsigned long)
548 ioremap(irqctrler->addrs[0].address, 0x40);
549 for (i = 2; i < 4; ++i)
550 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
551 (addr + (4 - i) * 0x10);
552 irq_cascade = irqctrler->intrs[0].line;
553 if (device_is_compatible(irqctrler, "gatwick"))
554 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
555 }
556 } else {
557 /* older powermacs have a GC (grand central) or ohare at
558 f3000000, with interrupt control registers at f3000020. */
559 addr = (unsigned long) ioremap(0xf3000000, 0x40);
560 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
561 }
562
563 /* PowerBooks 3400 and 3500 can have a second controller in a second
564 ohare chip, on the combo ethernet/modem card */
565 if (machine_is_compatible("AAPL,3400/2400")
566 || machine_is_compatible("AAPL,3500"))
567 irq_cascade = enable_second_ohare();
568
569 /* disable all interrupts in all controllers */
570 for (i = 0; i * 32 < max_irqs; ++i)
571 out_le32(&pmac_irq_hw[i]->enable, 0);
572 /* mark level interrupts */
573 for (i = 0; i < max_irqs; i++)
574 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
575 irq_desc[i].status = IRQ_LEVEL;
576
577 /* get interrupt line of secondary interrupt controller */
578 if (irq_cascade >= 0) {
579 printk(KERN_INFO "irq: secondary controller on irq %d\n",
580 (int)irq_cascade);
581 for ( i = max_real_irqs ; i < max_irqs ; i++ )
582 irq_desc[i].handler = &gatwick_pic;
583 setup_irq(irq_cascade, &gatwick_cascade_action);
584 }
585 printk("System has %d possible interrupts\n", max_irqs);
586 if (max_irqs != max_real_irqs)
587 printk(KERN_DEBUG "%d interrupts on main controller\n",
588 max_real_irqs);
589
590#ifdef CONFIG_XMON
591 setup_irq(20, &xmon_action);
592#endif /* CONFIG_XMON */
593}
594
595#ifdef CONFIG_PM
596/*
597 * These procedures are used in implementing sleep on the powerbooks.
598 * sleep_save_intrs() saves the states of all interrupt enables
599 * and disables all interrupts except for the nominated one.
600 * sleep_restore_intrs() restores the states of all interrupt enables.
601 */
602unsigned long sleep_save_mask[2];
603
604/* This used to be passed by the PMU driver but that link got
605 * broken with the new driver model. We use this tweak for now...
606 */
607static int pmacpic_find_viaint(void)
608{
609 int viaint = -1;
610
611#ifdef CONFIG_ADB_PMU
612 struct device_node *np;
613
614 if (pmu_get_model() != PMU_OHARE_BASED)
615 goto not_found;
616 np = of_find_node_by_name(NULL, "via-pmu");
617 if (np == NULL)
618 goto not_found;
619 viaint = np->intrs[0].line;
620#endif /* CONFIG_ADB_PMU */
621
622not_found:
623 return viaint;
624}
625
626static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
627{
628 int viaint = pmacpic_find_viaint();
629
630 sleep_save_mask[0] = ppc_cached_irq_mask[0];
631 sleep_save_mask[1] = ppc_cached_irq_mask[1];
632 ppc_cached_irq_mask[0] = 0;
633 ppc_cached_irq_mask[1] = 0;
634 if (viaint > 0)
635 set_bit(viaint, ppc_cached_irq_mask);
636 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
637 if (max_real_irqs > 32)
638 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
639 (void)in_le32(&pmac_irq_hw[0]->event);
640 /* make sure mask gets to controller before we return to caller */
641 mb();
642 (void)in_le32(&pmac_irq_hw[0]->enable);
643
644 return 0;
645}
646
647static int pmacpic_resume(struct sys_device *sysdev)
648{
649 int i;
650
651 out_le32(&pmac_irq_hw[0]->enable, 0);
652 if (max_real_irqs > 32)
653 out_le32(&pmac_irq_hw[1]->enable, 0);
654 mb();
655 for (i = 0; i < max_real_irqs; ++i)
656 if (test_bit(i, sleep_save_mask))
657 pmac_unmask_irq(i);
658
659 return 0;
660}
661
662#endif /* CONFIG_PM */
663
664static struct sysdev_class pmacpic_sysclass = {
665 set_kset_name("pmac_pic"),
666};
667
668static struct sys_device device_pmacpic = {
669 .id = 0,
670 .cls = &pmacpic_sysclass,
671};
672
673static struct sysdev_driver driver_pmacpic = {
674#ifdef CONFIG_PM
675 .suspend = &pmacpic_suspend,
676 .resume = &pmacpic_resume,
677#endif /* CONFIG_PM */
678};
679
680static int __init init_pmacpic_sysfs(void)
681{
682 if (max_irqs == 0)
683 return -ENODEV;
684
685 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
686 sysdev_class_register(&pmacpic_sysclass);
687 sysdev_register(&device_pmacpic);
688 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
689 return 0;
690}
691
692subsys_initcall(init_pmacpic_sysfs);
693
diff --git a/arch/ppc/platforms/pmac_pic.h b/arch/ppc/platforms/pmac_pic.h
deleted file mode 100644
index 664103dfee..0000000000
--- a/arch/ppc/platforms/pmac_pic.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __PPC_PLATFORMS_PMAC_PIC_H
2#define __PPC_PLATFORMS_PMAC_PIC_H
3
4#include <linux/irq.h>
5
6extern struct hw_interrupt_type pmac_pic;
7
8void pmac_pic_init(void);
9int pmac_get_irq(struct pt_regs *regs);
10
11#endif /* __PPC_PLATFORMS_PMAC_PIC_H */
diff --git a/arch/ppc/platforms/pmac_setup.c b/arch/ppc/platforms/pmac_setup.c
deleted file mode 100644
index 55d2beffe5..0000000000
--- a/arch/ppc/platforms/pmac_setup.c
+++ /dev/null
@@ -1,745 +0,0 @@
1/*
2 * arch/ppc/platforms/setup.c
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Adapted for Power Macintosh by Paul Mackerras
8 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
9 *
10 * Derived from "arch/alpha/kernel/setup.c"
11 * Copyright (C) 1995 Linus Torvalds
12 *
13 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
21
22/*
23 * bootup setup stuff..
24 */
25
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/stddef.h>
33#include <linux/unistd.h>
34#include <linux/ptrace.h>
35#include <linux/slab.h>
36#include <linux/user.h>
37#include <linux/a.out.h>
38#include <linux/tty.h>
39#include <linux/string.h>
40#include <linux/delay.h>
41#include <linux/ioport.h>
42#include <linux/major.h>
43#include <linux/initrd.h>
44#include <linux/vt_kern.h>
45#include <linux/console.h>
46#include <linux/ide.h>
47#include <linux/pci.h>
48#include <linux/adb.h>
49#include <linux/cuda.h>
50#include <linux/pmu.h>
51#include <linux/seq_file.h>
52#include <linux/root_dev.h>
53#include <linux/bitops.h>
54#include <linux/suspend.h>
55
56#include <asm/reg.h>
57#include <asm/sections.h>
58#include <asm/prom.h>
59#include <asm/system.h>
60#include <asm/pgtable.h>
61#include <asm/io.h>
62#include <asm/pci-bridge.h>
63#include <asm/ohare.h>
64#include <asm/mediabay.h>
65#include <asm/machdep.h>
66#include <asm/dma.h>
67#include <asm/bootx.h>
68#include <asm/cputable.h>
69#include <asm/btext.h>
70#include <asm/pmac_feature.h>
71#include <asm/time.h>
72#include <asm/of_device.h>
73#include <asm/mmu_context.h>
74
75#include "pmac_pic.h"
76#include "mem_pieces.h"
77
78#undef SHOW_GATWICK_IRQS
79
80extern long pmac_time_init(void);
81extern unsigned long pmac_get_rtc_time(void);
82extern int pmac_set_rtc_time(unsigned long nowtime);
83extern void pmac_read_rtc_time(void);
84extern void pmac_calibrate_decr(void);
85extern void pmac_pcibios_fixup(void);
86extern void pmac_find_bridges(void);
87extern unsigned long pmac_ide_get_base(int index);
88extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
89 unsigned long data_port, unsigned long ctrl_port, int *irq);
90
91extern void pmac_nvram_update(void);
92extern unsigned char pmac_nvram_read_byte(int addr);
93extern void pmac_nvram_write_byte(int addr, unsigned char val);
94extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial);
95extern void pmac_pcibios_after_init(void);
96extern int of_show_percpuinfo(struct seq_file *m, int i);
97
98struct device_node *memory_node;
99
100unsigned char drive_info;
101
102int ppc_override_l2cr = 0;
103int ppc_override_l2cr_value;
104int has_l2cache = 0;
105
106static int current_root_goodness = -1;
107
108extern int pmac_newworld;
109
110#define DEFAULT_ROOT_DEVICE Root_SDA1 /* sda1 - slightly silly choice */
111
112extern void zs_kgdb_hook(int tty_num);
113static void ohare_init(void);
114#ifdef CONFIG_BOOTX_TEXT
115static void pmac_progress(char *s, unsigned short hex);
116#endif
117
118sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
119
120#ifdef CONFIG_SMP
121extern struct smp_ops_t psurge_smp_ops;
122extern struct smp_ops_t core99_smp_ops;
123#endif /* CONFIG_SMP */
124
125static int
126pmac_show_cpuinfo(struct seq_file *m)
127{
128 struct device_node *np;
129 char *pp;
130 int plen;
131 int mbmodel = pmac_call_feature(PMAC_FTR_GET_MB_INFO,
132 NULL, PMAC_MB_INFO_MODEL, 0);
133 unsigned int mbflags = (unsigned int)pmac_call_feature(PMAC_FTR_GET_MB_INFO,
134 NULL, PMAC_MB_INFO_FLAGS, 0);
135 char* mbname;
136
137 if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME, (int)&mbname) != 0)
138 mbname = "Unknown";
139
140 /* find motherboard type */
141 seq_printf(m, "machine\t\t: ");
142 np = find_devices("device-tree");
143 if (np != NULL) {
144 pp = (char *) get_property(np, "model", NULL);
145 if (pp != NULL)
146 seq_printf(m, "%s\n", pp);
147 else
148 seq_printf(m, "PowerMac\n");
149 pp = (char *) get_property(np, "compatible", &plen);
150 if (pp != NULL) {
151 seq_printf(m, "motherboard\t:");
152 while (plen > 0) {
153 int l = strlen(pp) + 1;
154 seq_printf(m, " %s", pp);
155 plen -= l;
156 pp += l;
157 }
158 seq_printf(m, "\n");
159 }
160 } else
161 seq_printf(m, "PowerMac\n");
162
163 /* print parsed model */
164 seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
165 seq_printf(m, "pmac flags\t: %08x\n", mbflags);
166
167 /* find l2 cache info */
168 np = find_devices("l2-cache");
169 if (np == 0)
170 np = find_type_devices("cache");
171 if (np != 0) {
172 unsigned int *ic = (unsigned int *)
173 get_property(np, "i-cache-size", NULL);
174 unsigned int *dc = (unsigned int *)
175 get_property(np, "d-cache-size", NULL);
176 seq_printf(m, "L2 cache\t:");
177 has_l2cache = 1;
178 if (get_property(np, "cache-unified", NULL) != 0 && dc) {
179 seq_printf(m, " %dK unified", *dc / 1024);
180 } else {
181 if (ic)
182 seq_printf(m, " %dK instruction", *ic / 1024);
183 if (dc)
184 seq_printf(m, "%s %dK data",
185 (ic? " +": ""), *dc / 1024);
186 }
187 pp = get_property(np, "ram-type", NULL);
188 if (pp)
189 seq_printf(m, " %s", pp);
190 seq_printf(m, "\n");
191 }
192
193 /* find ram info */
194 np = find_devices("memory");
195 if (np != 0) {
196 int n;
197 struct reg_property *reg = (struct reg_property *)
198 get_property(np, "reg", &n);
199
200 if (reg != 0) {
201 unsigned long total = 0;
202
203 for (n /= sizeof(struct reg_property); n > 0; --n)
204 total += (reg++)->size;
205 seq_printf(m, "memory\t\t: %luMB\n", total >> 20);
206 }
207 }
208
209 /* Checks "l2cr-value" property in the registry */
210 np = find_devices("cpus");
211 if (np == 0)
212 np = find_type_devices("cpu");
213 if (np != 0) {
214 unsigned int *l2cr = (unsigned int *)
215 get_property(np, "l2cr-value", NULL);
216 if (l2cr != 0) {
217 seq_printf(m, "l2cr override\t: 0x%x\n", *l2cr);
218 }
219 }
220
221 /* Indicate newworld/oldworld */
222 seq_printf(m, "pmac-generation\t: %s\n",
223 pmac_newworld ? "NewWorld" : "OldWorld");
224
225
226 return 0;
227}
228
229static int
230pmac_show_percpuinfo(struct seq_file *m, int i)
231{
232#ifdef CONFIG_CPU_FREQ_PMAC
233 extern unsigned int pmac_get_one_cpufreq(int i);
234 unsigned int freq = pmac_get_one_cpufreq(i);
235 if (freq != 0) {
236 seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
237 return 0;
238 }
239#endif /* CONFIG_CPU_FREQ_PMAC */
240 return of_show_percpuinfo(m, i);
241}
242
243static volatile u32 *sysctrl_regs;
244
245void __init
246pmac_setup_arch(void)
247{
248 struct device_node *cpu;
249 int *fp;
250 unsigned long pvr;
251
252 pvr = PVR_VER(mfspr(SPRN_PVR));
253
254 /* Set loops_per_jiffy to a half-way reasonable value,
255 for use until calibrate_delay gets called. */
256 cpu = find_type_devices("cpu");
257 if (cpu != 0) {
258 fp = (int *) get_property(cpu, "clock-frequency", NULL);
259 if (fp != 0) {
260 if (pvr == 4 || pvr >= 8)
261 /* 604, G3, G4 etc. */
262 loops_per_jiffy = *fp / HZ;
263 else
264 /* 601, 603, etc. */
265 loops_per_jiffy = *fp / (2*HZ);
266 } else
267 loops_per_jiffy = 50000000 / HZ;
268 }
269
270 /* this area has the CPU identification register
271 and some registers used by smp boards */
272 sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);
273 ohare_init();
274
275 /* Lookup PCI hosts */
276 pmac_find_bridges();
277
278 /* Checks "l2cr-value" property in the registry */
279 if (cpu_has_feature(CPU_FTR_L2CR)) {
280 struct device_node *np = find_devices("cpus");
281 if (np == 0)
282 np = find_type_devices("cpu");
283 if (np != 0) {
284 unsigned int *l2cr = (unsigned int *)
285 get_property(np, "l2cr-value", NULL);
286 if (l2cr != 0) {
287 ppc_override_l2cr = 1;
288 ppc_override_l2cr_value = *l2cr;
289 _set_L2CR(0);
290 _set_L2CR(ppc_override_l2cr_value);
291 }
292 }
293 }
294
295 if (ppc_override_l2cr)
296 printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",
297 ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)
298 ? "enabled" : "disabled");
299
300#ifdef CONFIG_KGDB
301 zs_kgdb_hook(0);
302#endif
303
304#ifdef CONFIG_ADB_CUDA
305 find_via_cuda();
306#else
307 if (find_devices("via-cuda")) {
308 printk("WARNING ! Your machine is Cuda based but your kernel\n");
309 printk(" wasn't compiled with CONFIG_ADB_CUDA option !\n");
310 }
311#endif
312#ifdef CONFIG_ADB_PMU
313 find_via_pmu();
314#else
315 if (find_devices("via-pmu")) {
316 printk("WARNING ! Your machine is PMU based but your kernel\n");
317 printk(" wasn't compiled with CONFIG_ADB_PMU option !\n");
318 }
319#endif
320#ifdef CONFIG_NVRAM
321 pmac_nvram_init();
322#endif
323#ifdef CONFIG_BLK_DEV_INITRD
324 if (initrd_start)
325 ROOT_DEV = Root_RAM0;
326 else
327#endif
328 ROOT_DEV = DEFAULT_ROOT_DEVICE;
329
330#ifdef CONFIG_SMP
331 /* Check for Core99 */
332 if (find_devices("uni-n") || find_devices("u3"))
333 smp_ops = &core99_smp_ops;
334 else
335 smp_ops = &psurge_smp_ops;
336#endif /* CONFIG_SMP */
337
338 pci_create_OF_bus_map();
339}
340
341static void __init ohare_init(void)
342{
343 /*
344 * Turn on the L2 cache.
345 * We assume that we have a PSX memory controller iff
346 * we have an ohare I/O controller.
347 */
348 if (find_devices("ohare") != NULL) {
349 if (((sysctrl_regs[2] >> 24) & 0xf) >= 3) {
350 if (sysctrl_regs[4] & 0x10)
351 sysctrl_regs[4] |= 0x04000020;
352 else
353 sysctrl_regs[4] |= 0x04000000;
354 if(has_l2cache)
355 printk(KERN_INFO "Level 2 cache enabled\n");
356 }
357 }
358}
359
360extern char *bootpath;
361extern char *bootdevice;
362void *boot_host;
363int boot_target;
364int boot_part;
365extern dev_t boot_dev;
366
367#ifdef CONFIG_SCSI
368void __init
369note_scsi_host(struct device_node *node, void *host)
370{
371 int l;
372 char *p;
373
374 l = strlen(node->full_name);
375 if (bootpath != NULL && bootdevice != NULL
376 && strncmp(node->full_name, bootdevice, l) == 0
377 && (bootdevice[l] == '/' || bootdevice[l] == 0)) {
378 boot_host = host;
379 /*
380 * There's a bug in OF 1.0.5. (Why am I not surprised.)
381 * If you pass a path like scsi/sd@1:0 to canon, it returns
382 * something like /bandit@F2000000/gc@10/53c94@10000/sd@0,0
383 * That is, the scsi target number doesn't get preserved.
384 * So we pick the target number out of bootpath and use that.
385 */
386 p = strstr(bootpath, "/sd@");
387 if (p != NULL) {
388 p += 4;
389 boot_target = simple_strtoul(p, NULL, 10);
390 p = strchr(p, ':');
391 if (p != NULL)
392 boot_part = simple_strtoul(p + 1, NULL, 10);
393 }
394 }
395}
396#endif
397
398#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
399static dev_t __init
400find_ide_boot(void)
401{
402 char *p;
403 int n;
404 dev_t __init pmac_find_ide_boot(char *bootdevice, int n);
405
406 if (bootdevice == NULL)
407 return 0;
408 p = strrchr(bootdevice, '/');
409 if (p == NULL)
410 return 0;
411 n = p - bootdevice;
412
413 return pmac_find_ide_boot(bootdevice, n);
414}
415#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
416
417static void __init
418find_boot_device(void)
419{
420#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
421 boot_dev = find_ide_boot();
422#endif
423}
424
425static int initializing = 1;
426/* TODO: Merge the suspend-to-ram with the common code !!!
427 * currently, this is a stub implementation for suspend-to-disk
428 * only
429 */
430
431#ifdef CONFIG_SOFTWARE_SUSPEND
432
433static int pmac_pm_prepare(suspend_state_t state)
434{
435 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
436
437 return 0;
438}
439
440static int pmac_pm_enter(suspend_state_t state)
441{
442 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
443
444 /* Giveup the lazy FPU & vec so we don't have to back them
445 * up from the low level code
446 */
447 enable_kernel_fp();
448
449#ifdef CONFIG_ALTIVEC
450 if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC)
451 enable_kernel_altivec();
452#endif /* CONFIG_ALTIVEC */
453
454 return 0;
455}
456
457static int pmac_pm_finish(suspend_state_t state)
458{
459 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
460
461 /* Restore userland MMU context */
462 set_context(current->active_mm->context, current->active_mm->pgd);
463
464 return 0;
465}
466
467static struct pm_ops pmac_pm_ops = {
468 .pm_disk_mode = PM_DISK_SHUTDOWN,
469 .prepare = pmac_pm_prepare,
470 .enter = pmac_pm_enter,
471 .finish = pmac_pm_finish,
472};
473
474#endif /* CONFIG_SOFTWARE_SUSPEND */
475
476static int pmac_late_init(void)
477{
478 initializing = 0;
479#ifdef CONFIG_SOFTWARE_SUSPEND
480 pm_set_ops(&pmac_pm_ops);
481#endif /* CONFIG_SOFTWARE_SUSPEND */
482 return 0;
483}
484
485late_initcall(pmac_late_init);
486
487/* can't be __init - can be called whenever a disk is first accessed */
488void
489note_bootable_part(dev_t dev, int part, int goodness)
490{
491 static int found_boot = 0;
492 char *p;
493
494 if (!initializing)
495 return;
496 if ((goodness <= current_root_goodness) &&
497 ROOT_DEV != DEFAULT_ROOT_DEVICE)
498 return;
499 p = strstr(saved_command_line, "root=");
500 if (p != NULL && (p == saved_command_line || p[-1] == ' '))
501 return;
502
503 if (!found_boot) {
504 find_boot_device();
505 found_boot = 1;
506 }
507 if (!boot_dev || dev == boot_dev) {
508 ROOT_DEV = dev + part;
509 boot_dev = 0;
510 current_root_goodness = goodness;
511 }
512}
513
514static void
515pmac_restart(char *cmd)
516{
517#ifdef CONFIG_ADB_CUDA
518 struct adb_request req;
519#endif /* CONFIG_ADB_CUDA */
520
521 switch (sys_ctrler) {
522#ifdef CONFIG_ADB_CUDA
523 case SYS_CTRLER_CUDA:
524 cuda_request(&req, NULL, 2, CUDA_PACKET,
525 CUDA_RESET_SYSTEM);
526 for (;;)
527 cuda_poll();
528 break;
529#endif /* CONFIG_ADB_CUDA */
530#ifdef CONFIG_ADB_PMU
531 case SYS_CTRLER_PMU:
532 pmu_restart();
533 break;
534#endif /* CONFIG_ADB_PMU */
535 default: ;
536 }
537}
538
539static void
540pmac_power_off(void)
541{
542#ifdef CONFIG_ADB_CUDA
543 struct adb_request req;
544#endif /* CONFIG_ADB_CUDA */
545
546 switch (sys_ctrler) {
547#ifdef CONFIG_ADB_CUDA
548 case SYS_CTRLER_CUDA:
549 cuda_request(&req, NULL, 2, CUDA_PACKET,
550 CUDA_POWERDOWN);
551 for (;;)
552 cuda_poll();
553 break;
554#endif /* CONFIG_ADB_CUDA */
555#ifdef CONFIG_ADB_PMU
556 case SYS_CTRLER_PMU:
557 pmu_shutdown();
558 break;
559#endif /* CONFIG_ADB_PMU */
560 default: ;
561 }
562}
563
564static void
565pmac_halt(void)
566{
567 pmac_power_off();
568}
569
570/*
571 * Read in a property describing some pieces of memory.
572 */
573
574static int __init
575get_mem_prop(char *name, struct mem_pieces *mp)
576{
577 struct reg_property *rp;
578 int i, s;
579 unsigned int *ip;
580 int nac = prom_n_addr_cells(memory_node);
581 int nsc = prom_n_size_cells(memory_node);
582
583 ip = (unsigned int *) get_property(memory_node, name, &s);
584 if (ip == NULL) {
585 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
586 name);
587 return 0;
588 }
589 s /= (nsc + nac) * 4;
590 rp = mp->regions;
591 for (i = 0; i < s; ++i, ip += nac+nsc) {
592 if (nac >= 2 && ip[nac-2] != 0)
593 continue;
594 rp->address = ip[nac-1];
595 if (nsc >= 2 && ip[nac+nsc-2] != 0)
596 rp->size = ~0U;
597 else
598 rp->size = ip[nac+nsc-1];
599 ++rp;
600 }
601 mp->n_regions = rp - mp->regions;
602
603 /* Make sure the pieces are sorted. */
604 mem_pieces_sort(mp);
605 mem_pieces_coalesce(mp);
606 return 1;
607}
608
609/*
610 * On systems with Open Firmware, collect information about
611 * physical RAM and which pieces are already in use.
612 * At this point, we have (at least) the first 8MB mapped with a BAT.
613 * Our text, data, bss use something over 1MB, starting at 0.
614 * Open Firmware may be using 1MB at the 4MB point.
615 */
616unsigned long __init
617pmac_find_end_of_memory(void)
618{
619 unsigned long a, total;
620 struct mem_pieces phys_mem;
621
622 /*
623 * Find out where physical memory is, and check that it
624 * starts at 0 and is contiguous. It seems that RAM is
625 * always physically contiguous on Power Macintoshes.
626 *
627 * Supporting discontiguous physical memory isn't hard,
628 * it just makes the virtual <-> physical mapping functions
629 * more complicated (or else you end up wasting space
630 * in mem_map).
631 */
632 memory_node = find_devices("memory");
633 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
634 || phys_mem.n_regions == 0)
635 panic("No RAM??");
636 a = phys_mem.regions[0].address;
637 if (a != 0)
638 panic("RAM doesn't start at physical address 0");
639 total = phys_mem.regions[0].size;
640
641 if (phys_mem.n_regions > 1) {
642 printk("RAM starting at 0x%x is not contiguous\n",
643 phys_mem.regions[1].address);
644 printk("Using RAM from 0 to 0x%lx\n", total-1);
645 }
646
647 return total;
648}
649
650void __init
651pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
652 unsigned long r6, unsigned long r7)
653{
654 /* isa_io_base gets set in pmac_find_bridges */
655 isa_mem_base = PMAC_ISA_MEM_BASE;
656 pci_dram_offset = PMAC_PCI_DRAM_OFFSET;
657 ISA_DMA_THRESHOLD = ~0L;
658 DMA_MODE_READ = 1;
659 DMA_MODE_WRITE = 2;
660
661 ppc_md.setup_arch = pmac_setup_arch;
662 ppc_md.show_cpuinfo = pmac_show_cpuinfo;
663 ppc_md.show_percpuinfo = pmac_show_percpuinfo;
664 ppc_md.init_IRQ = pmac_pic_init;
665 ppc_md.get_irq = pmac_get_irq; /* Changed later on ... */
666
667 ppc_md.pcibios_fixup = pmac_pcibios_fixup;
668 ppc_md.pcibios_enable_device_hook = pmac_pci_enable_device_hook;
669 ppc_md.pcibios_after_init = pmac_pcibios_after_init;
670 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
671
672 ppc_md.restart = pmac_restart;
673 ppc_md.power_off = pmac_power_off;
674 ppc_md.halt = pmac_halt;
675
676 ppc_md.time_init = pmac_time_init;
677 ppc_md.set_rtc_time = pmac_set_rtc_time;
678 ppc_md.get_rtc_time = pmac_get_rtc_time;
679 ppc_md.calibrate_decr = pmac_calibrate_decr;
680
681 ppc_md.find_end_of_memory = pmac_find_end_of_memory;
682
683 ppc_md.feature_call = pmac_do_feature_call;
684
685#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
686#ifdef CONFIG_BLK_DEV_IDE_PMAC
687 ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports;
688 ppc_ide_md.default_io_base = pmac_ide_get_base;
689#endif /* CONFIG_BLK_DEV_IDE_PMAC */
690#endif /* defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) */
691
692#ifdef CONFIG_BOOTX_TEXT
693 ppc_md.progress = pmac_progress;
694#endif /* CONFIG_BOOTX_TEXT */
695
696 if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0);
697
698}
699
700#ifdef CONFIG_BOOTX_TEXT
701static void __init
702pmac_progress(char *s, unsigned short hex)
703{
704 if (boot_text_mapped) {
705 btext_drawstring(s);
706 btext_drawchar('\n');
707 }
708}
709#endif /* CONFIG_BOOTX_TEXT */
710
711static int __init
712pmac_declare_of_platform_devices(void)
713{
714 struct device_node *np;
715
716 np = find_devices("uni-n");
717 if (np) {
718 for (np = np->child; np != NULL; np = np->sibling)
719 if (strncmp(np->name, "i2c", 3) == 0) {
720 of_platform_device_create(np, "uni-n-i2c",
721 NULL);
722 break;
723 }
724 }
725 np = find_devices("u3");
726 if (np) {
727 for (np = np->child; np != NULL; np = np->sibling)
728 if (strncmp(np->name, "i2c", 3) == 0) {
729 of_platform_device_create(np, "u3-i2c",
730 NULL);
731 break;
732 }
733 }
734
735 np = find_devices("valkyrie");
736 if (np)
737 of_platform_device_create(np, "valkyrie", NULL);
738 np = find_devices("platinum");
739 if (np)
740 of_platform_device_create(np, "platinum", NULL);
741
742 return 0;
743}
744
745device_initcall(pmac_declare_of_platform_devices);
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
deleted file mode 100644
index 22b113d19b..0000000000
--- a/arch/ppc/platforms/pmac_sleep.S
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/config.h>
14#include <asm/processor.h>
15#include <asm/page.h>
16#include <asm/ppc_asm.h>
17#include <asm/cputable.h>
18#include <asm/cache.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21
22#define MAGIC 0x4c617273 /* 'Lars' */
23
24/*
25 * Structure for storing CPU registers on the stack.
26 */
27#define SL_SP 0
28#define SL_PC 4
29#define SL_MSR 8
30#define SL_SDR1 0xc
31#define SL_SPRG0 0x10 /* 4 sprg's */
32#define SL_DBAT0 0x20
33#define SL_IBAT0 0x28
34#define SL_DBAT1 0x30
35#define SL_IBAT1 0x38
36#define SL_DBAT2 0x40
37#define SL_IBAT2 0x48
38#define SL_DBAT3 0x50
39#define SL_IBAT3 0x58
40#define SL_TB 0x60
41#define SL_R2 0x68
42#define SL_CR 0x6c
43#define SL_R12 0x70 /* r12 to r31 */
44#define SL_SIZE (SL_R12 + 80)
45
46 .section .text
47 .align 5
48
49#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC)
50
51/* This gets called by via-pmu.c late during the sleep process.
52 * The PMU was already send the sleep command and will shut us down
53 * soon. We need to save all that is needed and setup the wakeup
54 * vector that will be called by the ROM on wakeup
55 */
56_GLOBAL(low_sleep_handler)
57#ifndef CONFIG_6xx
58 blr
59#else
60 mflr r0
61 stw r0,4(r1)
62 stwu r1,-SL_SIZE(r1)
63 mfcr r0
64 stw r0,SL_CR(r1)
65 stw r2,SL_R2(r1)
66 stmw r12,SL_R12(r1)
67
68 /* Save MSR & SDR1 */
69 mfmsr r4
70 stw r4,SL_MSR(r1)
71 mfsdr1 r4
72 stw r4,SL_SDR1(r1)
73
74 /* Get a stable timebase and save it */
751: mftbu r4
76 stw r4,SL_TB(r1)
77 mftb r5
78 stw r5,SL_TB+4(r1)
79 mftbu r3
80 cmpw r3,r4
81 bne 1b
82
83 /* Save SPRGs */
84 mfsprg r4,0
85 stw r4,SL_SPRG0(r1)
86 mfsprg r4,1
87 stw r4,SL_SPRG0+4(r1)
88 mfsprg r4,2
89 stw r4,SL_SPRG0+8(r1)
90 mfsprg r4,3
91 stw r4,SL_SPRG0+12(r1)
92
93 /* Save BATs */
94 mfdbatu r4,0
95 stw r4,SL_DBAT0(r1)
96 mfdbatl r4,0
97 stw r4,SL_DBAT0+4(r1)
98 mfdbatu r4,1
99 stw r4,SL_DBAT1(r1)
100 mfdbatl r4,1
101 stw r4,SL_DBAT1+4(r1)
102 mfdbatu r4,2
103 stw r4,SL_DBAT2(r1)
104 mfdbatl r4,2
105 stw r4,SL_DBAT2+4(r1)
106 mfdbatu r4,3
107 stw r4,SL_DBAT3(r1)
108 mfdbatl r4,3
109 stw r4,SL_DBAT3+4(r1)
110 mfibatu r4,0
111 stw r4,SL_IBAT0(r1)
112 mfibatl r4,0
113 stw r4,SL_IBAT0+4(r1)
114 mfibatu r4,1
115 stw r4,SL_IBAT1(r1)
116 mfibatl r4,1
117 stw r4,SL_IBAT1+4(r1)
118 mfibatu r4,2
119 stw r4,SL_IBAT2(r1)
120 mfibatl r4,2
121 stw r4,SL_IBAT2+4(r1)
122 mfibatu r4,3
123 stw r4,SL_IBAT3(r1)
124 mfibatl r4,3
125 stw r4,SL_IBAT3+4(r1)
126
127 /* Backup various CPU config stuffs */
128 bl __save_cpu_setup
129
130 /* The ROM can wake us up via 2 different vectors:
131 * - On wallstreet & lombard, we must write a magic
132 * value 'Lars' at address 4 and a pointer to a
133 * memory location containing the PC to resume from
134 * at address 0.
135 * - On Core99, we must store the wakeup vector at
136 * address 0x80 and eventually it's parameters
137 * at address 0x84. I've have some trouble with those
138 * parameters however and I no longer use them.
139 */
140 lis r5,grackle_wake_up@ha
141 addi r5,r5,grackle_wake_up@l
142 tophys(r5,r5)
143 stw r5,SL_PC(r1)
144 lis r4,KERNELBASE@h
145 tophys(r5,r1)
146 addi r5,r5,SL_PC
147 lis r6,MAGIC@ha
148 addi r6,r6,MAGIC@l
149 stw r5,0(r4)
150 stw r6,4(r4)
151 /* Setup stuffs at 0x80-0x84 for Core99 */
152 lis r3,core99_wake_up@ha
153 addi r3,r3,core99_wake_up@l
154 tophys(r3,r3)
155 stw r3,0x80(r4)
156 stw r5,0x84(r4)
157 /* Store a pointer to our backup storage into
158 * a kernel global
159 */
160 lis r3,sleep_storage@ha
161 addi r3,r3,sleep_storage@l
162 stw r5,0(r3)
163
164 .globl low_cpu_die
165low_cpu_die:
166 /* Flush & disable all caches */
167 bl flush_disable_caches
168
169 /* Turn off data relocation. */
170 mfmsr r3 /* Save MSR in r7 */
171 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
172 sync
173 mtmsr r3
174 isync
175
176BEGIN_FTR_SECTION
177 /* Flush any pending L2 data prefetches to work around HW bug */
178 sync
179 lis r3,0xfff0
180 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
181 sync /* (caches are disabled at this point) */
182END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
183
184/*
185 * Set the HID0 and MSR for sleep.
186 */
187 mfspr r2,SPRN_HID0
188 rlwinm r2,r2,0,10,7 /* clear doze, nap */
189 oris r2,r2,HID0_SLEEP@h
190 sync
191 isync
192 mtspr SPRN_HID0,r2
193 sync
194
195/* This loop puts us back to sleep in case we have a spurrious
196 * wakeup so that the host bridge properly stays asleep. The
197 * CPU will be turned off, either after a known time (about 1
198 * second) on wallstreet & lombard, or as soon as the CPU enters
199 * SLEEP mode on core99
200 */
201 mfmsr r2
202 oris r2,r2,MSR_POW@h
2031: sync
204 mtmsr r2
205 isync
206 b 1b
207
208/*
209 * Here is the resume code.
210 */
211
212
213/*
214 * Core99 machines resume here
215 * r4 has the physical address of SL_PC(sp) (unused)
216 */
217_GLOBAL(core99_wake_up)
218 /* Make sure HID0 no longer contains any sleep bit and that data cache
219 * is disabled
220 */
221 mfspr r3,SPRN_HID0
222 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
223 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
224 mtspr SPRN_HID0,r3
225 sync
226 isync
227
228 /* sanitize MSR */
229 mfmsr r3
230 ori r3,r3,MSR_EE|MSR_IP
231 xori r3,r3,MSR_EE|MSR_IP
232 sync
233 isync
234 mtmsr r3
235 sync
236 isync
237
238 /* Recover sleep storage */
239 lis r3,sleep_storage@ha
240 addi r3,r3,sleep_storage@l
241 tophys(r3,r3)
242 lwz r1,0(r3)
243
244 /* Pass thru to older resume code ... */
245/*
246 * Here is the resume code for older machines.
247 * r1 has the physical address of SL_PC(sp).
248 */
249
250grackle_wake_up:
251
252 /* Restore the kernel's segment registers before
253 * we do any r1 memory access as we are not sure they
254 * are in a sane state above the first 256Mb region
255 */
256 li r0,16 /* load up segment register values */
257 mtctr r0 /* for context 0 */
258 lis r3,0x2000 /* Ku = 1, VSID = 0 */
259 li r4,0
2603: mtsrin r3,r4
261 addi r3,r3,0x111 /* increment VSID */
262 addis r4,r4,0x1000 /* address of next segment */
263 bdnz 3b
264 sync
265 isync
266
267 subi r1,r1,SL_PC
268
269 /* Restore various CPU config stuffs */
270 bl __restore_cpu_setup
271
272 /* Make sure all FPRs have been initialized */
273 bl reloc_offset
274 bl __init_fpu_registers
275
276 /* Invalidate & enable L1 cache, we don't care about
277 * whatever the ROM may have tried to write to memory
278 */
279 bl __inval_enable_L1
280
281 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
282 lwz r4,SL_SDR1(r1)
283 mtsdr1 r4
284 lwz r4,SL_SPRG0(r1)
285 mtsprg 0,r4
286 lwz r4,SL_SPRG0+4(r1)
287 mtsprg 1,r4
288 lwz r4,SL_SPRG0+8(r1)
289 mtsprg 2,r4
290 lwz r4,SL_SPRG0+12(r1)
291 mtsprg 3,r4
292
293 lwz r4,SL_DBAT0(r1)
294 mtdbatu 0,r4
295 lwz r4,SL_DBAT0+4(r1)
296 mtdbatl 0,r4
297 lwz r4,SL_DBAT1(r1)
298 mtdbatu 1,r4
299 lwz r4,SL_DBAT1+4(r1)
300 mtdbatl 1,r4
301 lwz r4,SL_DBAT2(r1)
302 mtdbatu 2,r4
303 lwz r4,SL_DBAT2+4(r1)
304 mtdbatl 2,r4
305 lwz r4,SL_DBAT3(r1)
306 mtdbatu 3,r4
307 lwz r4,SL_DBAT3+4(r1)
308 mtdbatl 3,r4
309 lwz r4,SL_IBAT0(r1)
310 mtibatu 0,r4
311 lwz r4,SL_IBAT0+4(r1)
312 mtibatl 0,r4
313 lwz r4,SL_IBAT1(r1)
314 mtibatu 1,r4
315 lwz r4,SL_IBAT1+4(r1)
316 mtibatl 1,r4
317 lwz r4,SL_IBAT2(r1)
318 mtibatu 2,r4
319 lwz r4,SL_IBAT2+4(r1)
320 mtibatl 2,r4
321 lwz r4,SL_IBAT3(r1)
322 mtibatu 3,r4
323 lwz r4,SL_IBAT3+4(r1)
324 mtibatl 3,r4
325
326BEGIN_FTR_SECTION
327 li r4,0
328 mtspr SPRN_DBAT4U,r4
329 mtspr SPRN_DBAT4L,r4
330 mtspr SPRN_DBAT5U,r4
331 mtspr SPRN_DBAT5L,r4
332 mtspr SPRN_DBAT6U,r4
333 mtspr SPRN_DBAT6L,r4
334 mtspr SPRN_DBAT7U,r4
335 mtspr SPRN_DBAT7L,r4
336 mtspr SPRN_IBAT4U,r4
337 mtspr SPRN_IBAT4L,r4
338 mtspr SPRN_IBAT5U,r4
339 mtspr SPRN_IBAT5L,r4
340 mtspr SPRN_IBAT6U,r4
341 mtspr SPRN_IBAT6L,r4
342 mtspr SPRN_IBAT7U,r4
343 mtspr SPRN_IBAT7L,r4
344END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
345
346 /* Flush all TLBs */
347 lis r4,0x1000
3481: addic. r4,r4,-0x1000
349 tlbie r4
350 blt 1b
351 sync
352
353 /* restore the MSR and turn on the MMU */
354 lwz r3,SL_MSR(r1)
355 bl turn_on_mmu
356
357 /* get back the stack pointer */
358 tovirt(r1,r1)
359
360 /* Restore TB */
361 li r3,0
362 mttbl r3
363 lwz r3,SL_TB(r1)
364 lwz r4,SL_TB+4(r1)
365 mttbu r3
366 mttbl r4
367
368 /* Restore the callee-saved registers and return */
369 lwz r0,SL_CR(r1)
370 mtcr r0
371 lwz r2,SL_R2(r1)
372 lmw r12,SL_R12(r1)
373 addi r1,r1,SL_SIZE
374 lwz r0,4(r1)
375 mtlr r0
376 blr
377
378turn_on_mmu:
379 mflr r4
380 tovirt(r4,r4)
381 mtsrr0 r4
382 mtsrr1 r3
383 sync
384 isync
385 rfi
386
387#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
388
389 .section .data
390 .balign L1_CACHE_BYTES
391sleep_storage:
392 .long 0
393 .balign L1_CACHE_BYTES, 0
394
395#endif /* CONFIG_6xx */
396 .section .text
diff --git a/arch/ppc/platforms/pmac_smp.c b/arch/ppc/platforms/pmac_smp.c
deleted file mode 100644
index 26ff26238f..0000000000
--- a/arch/ppc/platforms/pmac_smp.c
+++ /dev/null
@@ -1,692 +0,0 @@
1/*
2 * SMP support for power macintosh.
3 *
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
6 *
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
12 *
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15 *
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/smp.h>
28#include <linux/smp_lock.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/hardirq.h>
36#include <linux/cpu.h>
37
38#include <asm/ptrace.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/sections.h>
44#include <asm/io.h>
45#include <asm/prom.h>
46#include <asm/smp.h>
47#include <asm/residual.h>
48#include <asm/machdep.h>
49#include <asm/pmac_feature.h>
50#include <asm/time.h>
51#include <asm/open_pic.h>
52#include <asm/cacheflush.h>
53#include <asm/keylargo.h>
54
55/*
56 * Powersurge (old powermac SMP) support.
57 */
58
59extern void __secondary_start_pmac_0(void);
60
61/* Addresses for powersurge registers */
62#define HAMMERHEAD_BASE 0xf8000000
63#define HHEAD_CONFIG 0x90
64#define HHEAD_SEC_INTR 0xc0
65
66/* register for interrupting the primary processor on the powersurge */
67/* N.B. this is actually the ethernet ROM! */
68#define PSURGE_PRI_INTR 0xf3019000
69
70/* register for storing the start address for the secondary processor */
71/* N.B. this is the PCI config space address register for the 1st bridge */
72#define PSURGE_START 0xf2800000
73
74/* Daystar/XLR8 4-CPU card */
75#define PSURGE_QUAD_REG_ADDR 0xf8800000
76
77#define PSURGE_QUAD_IRQ_SET 0
78#define PSURGE_QUAD_IRQ_CLR 1
79#define PSURGE_QUAD_IRQ_PRIMARY 2
80#define PSURGE_QUAD_CKSTOP_CTL 3
81#define PSURGE_QUAD_PRIMARY_ARB 4
82#define PSURGE_QUAD_BOARD_ID 6
83#define PSURGE_QUAD_WHICH_CPU 7
84#define PSURGE_QUAD_CKSTOP_RDBK 8
85#define PSURGE_QUAD_RESET_CTL 11
86
87#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
88#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
89#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
90#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
91
92/* virtual addresses for the above */
93static volatile u8 __iomem *hhead_base;
94static volatile u8 __iomem *quad_base;
95static volatile u32 __iomem *psurge_pri_intr;
96static volatile u8 __iomem *psurge_sec_intr;
97static volatile u32 __iomem *psurge_start;
98
99/* values for psurge_type */
100#define PSURGE_NONE -1
101#define PSURGE_DUAL 0
102#define PSURGE_QUAD_OKEE 1
103#define PSURGE_QUAD_COTTON 2
104#define PSURGE_QUAD_ICEGRASS 3
105
106/* what sort of powersurge board we have */
107static int psurge_type = PSURGE_NONE;
108
109/* L2 and L3 cache settings to pass from CPU0 to CPU1 */
110volatile static long int core99_l2_cache;
111volatile static long int core99_l3_cache;
112
113/* Timebase freeze GPIO */
114static unsigned int core99_tb_gpio;
115
116/* Sync flag for HW tb sync */
117static volatile int sec_tb_reset = 0;
118static unsigned int pri_tb_hi, pri_tb_lo;
119static unsigned int pri_tb_stamp;
120
121static void __devinit core99_init_caches(int cpu)
122{
123 if (!cpu_has_feature(CPU_FTR_L2CR))
124 return;
125
126 if (cpu == 0) {
127 core99_l2_cache = _get_L2CR();
128 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
129 } else {
130 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
131 _set_L2CR(0);
132 _set_L2CR(core99_l2_cache);
133 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
134 }
135
136 if (!cpu_has_feature(CPU_FTR_L3CR))
137 return;
138
139 if (cpu == 0){
140 core99_l3_cache = _get_L3CR();
141 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
142 } else {
143 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
144 _set_L3CR(0);
145 _set_L3CR(core99_l3_cache);
146 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
147 }
148}
149
150/*
151 * Set and clear IPIs for powersurge.
152 */
153static inline void psurge_set_ipi(int cpu)
154{
155 if (psurge_type == PSURGE_NONE)
156 return;
157 if (cpu == 0)
158 in_be32(psurge_pri_intr);
159 else if (psurge_type == PSURGE_DUAL)
160 out_8(psurge_sec_intr, 0);
161 else
162 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
163}
164
165static inline void psurge_clr_ipi(int cpu)
166{
167 if (cpu > 0) {
168 switch(psurge_type) {
169 case PSURGE_DUAL:
170 out_8(psurge_sec_intr, ~0);
171 case PSURGE_NONE:
172 break;
173 default:
174 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
175 }
176 }
177}
178
179/*
180 * On powersurge (old SMP powermac architecture) we don't have
181 * separate IPIs for separate messages like openpic does. Instead
182 * we have a bitmap for each processor, where a 1 bit means that
183 * the corresponding message is pending for that processor.
184 * Ideally each cpu's entry would be in a different cache line.
185 * -- paulus.
186 */
187static unsigned long psurge_smp_message[NR_CPUS];
188
189void psurge_smp_message_recv(struct pt_regs *regs)
190{
191 int cpu = smp_processor_id();
192 int msg;
193
194 /* clear interrupt */
195 psurge_clr_ipi(cpu);
196
197 if (num_online_cpus() < 2)
198 return;
199
200 /* make sure there is a message there */
201 for (msg = 0; msg < 4; msg++)
202 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
203 smp_message_recv(msg, regs);
204}
205
206irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
207{
208 psurge_smp_message_recv(regs);
209 return IRQ_HANDLED;
210}
211
212static void smp_psurge_message_pass(int target, int msg)
213{
214 int i;
215
216 if (num_online_cpus() < 2)
217 return;
218
219 for (i = 0; i < NR_CPUS; i++) {
220 if (!cpu_online(i))
221 continue;
222 if (target == MSG_ALL
223 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
224 || target == i) {
225 set_bit(msg, &psurge_smp_message[i]);
226 psurge_set_ipi(i);
227 }
228 }
229}
230
231/*
232 * Determine a quad card presence. We read the board ID register, we
233 * force the data bus to change to something else, and we read it again.
234 * It it's stable, then the register probably exist (ugh !)
235 */
236static int __init psurge_quad_probe(void)
237{
238 int type;
239 unsigned int i;
240
241 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
242 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
243 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
244 return PSURGE_DUAL;
245
246 /* looks OK, try a slightly more rigorous test */
247 /* bogus is not necessarily cacheline-aligned,
248 though I don't suppose that really matters. -- paulus */
249 for (i = 0; i < 100; i++) {
250 volatile u32 bogus[8];
251 bogus[(0+i)%8] = 0x00000000;
252 bogus[(1+i)%8] = 0x55555555;
253 bogus[(2+i)%8] = 0xFFFFFFFF;
254 bogus[(3+i)%8] = 0xAAAAAAAA;
255 bogus[(4+i)%8] = 0x33333333;
256 bogus[(5+i)%8] = 0xCCCCCCCC;
257 bogus[(6+i)%8] = 0xCCCCCCCC;
258 bogus[(7+i)%8] = 0x33333333;
259 wmb();
260 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
261 mb();
262 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
263 return PSURGE_DUAL;
264 }
265 return type;
266}
267
268static void __init psurge_quad_init(void)
269{
270 int procbits;
271
272 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
273 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
274 if (psurge_type == PSURGE_QUAD_ICEGRASS)
275 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
276 else
277 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
278 mdelay(33);
279 out_8(psurge_sec_intr, ~0);
280 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
281 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
282 if (psurge_type != PSURGE_QUAD_ICEGRASS)
283 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
284 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
285 mdelay(33);
286 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
287 mdelay(33);
288 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
289 mdelay(33);
290}
291
292static int __init smp_psurge_probe(void)
293{
294 int i, ncpus;
295
296 /* We don't do SMP on the PPC601 -- paulus */
297 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
298 return 1;
299
300 /*
301 * The powersurge cpu board can be used in the generation
302 * of powermacs that have a socket for an upgradeable cpu card,
303 * including the 7500, 8500, 9500, 9600.
304 * The device tree doesn't tell you if you have 2 cpus because
305 * OF doesn't know anything about the 2nd processor.
306 * Instead we look for magic bits in magic registers,
307 * in the hammerhead memory controller in the case of the
308 * dual-cpu powersurge board. -- paulus.
309 */
310 if (find_devices("hammerhead") == NULL)
311 return 1;
312
313 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
314 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
315 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
316
317 psurge_type = psurge_quad_probe();
318 if (psurge_type != PSURGE_DUAL) {
319 psurge_quad_init();
320 /* All released cards using this HW design have 4 CPUs */
321 ncpus = 4;
322 } else {
323 iounmap(quad_base);
324 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
325 /* not a dual-cpu card */
326 iounmap(hhead_base);
327 psurge_type = PSURGE_NONE;
328 return 1;
329 }
330 ncpus = 2;
331 }
332
333 psurge_start = ioremap(PSURGE_START, 4);
334 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
335
336 /* this is not actually strictly necessary -- paulus. */
337 for (i = 1; i < ncpus; ++i)
338 smp_hw_index[i] = i;
339
340 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
341
342 return ncpus;
343}
344
345static void __init smp_psurge_kick_cpu(int nr)
346{
347 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
348 unsigned long a;
349
350 /* may need to flush here if secondary bats aren't setup */
351 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
352 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
353 asm volatile("sync");
354
355 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
356
357 out_be32(psurge_start, start);
358 mb();
359
360 psurge_set_ipi(nr);
361 udelay(10);
362 psurge_clr_ipi(nr);
363
364 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
365}
366
367/*
368 * With the dual-cpu powersurge board, the decrementers and timebases
369 * of both cpus are frozen after the secondary cpu is started up,
370 * until we give the secondary cpu another interrupt. This routine
371 * uses this to get the timebases synchronized.
372 * -- paulus.
373 */
374static void __init psurge_dual_sync_tb(int cpu_nr)
375{
376 int t;
377
378 set_dec(tb_ticks_per_jiffy);
379 set_tb(0, 0);
380 last_jiffy_stamp(cpu_nr) = 0;
381
382 if (cpu_nr > 0) {
383 mb();
384 sec_tb_reset = 1;
385 return;
386 }
387
388 /* wait for the secondary to have reset its TB before proceeding */
389 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
390 ;
391
392 /* now interrupt the secondary, starting both TBs */
393 psurge_set_ipi(1);
394
395 smp_tb_synchronized = 1;
396}
397
398static struct irqaction psurge_irqaction = {
399 .handler = psurge_primary_intr,
400 .flags = SA_INTERRUPT,
401 .mask = CPU_MASK_NONE,
402 .name = "primary IPI",
403};
404
405static void __init smp_psurge_setup_cpu(int cpu_nr)
406{
407
408 if (cpu_nr == 0) {
409 /* If we failed to start the second CPU, we should still
410 * send it an IPI to start the timebase & DEC or we might
411 * have them stuck.
412 */
413 if (num_online_cpus() < 2) {
414 if (psurge_type == PSURGE_DUAL)
415 psurge_set_ipi(1);
416 return;
417 }
418 /* reset the entry point so if we get another intr we won't
419 * try to startup again */
420 out_be32(psurge_start, 0x100);
421 if (setup_irq(30, &psurge_irqaction))
422 printk(KERN_ERR "Couldn't get primary IPI interrupt");
423 }
424
425 if (psurge_type == PSURGE_DUAL)
426 psurge_dual_sync_tb(cpu_nr);
427}
428
429void __init smp_psurge_take_timebase(void)
430{
431 /* Dummy implementation */
432}
433
434void __init smp_psurge_give_timebase(void)
435{
436 /* Dummy implementation */
437}
438
439static int __init smp_core99_probe(void)
440{
441#ifdef CONFIG_6xx
442 extern int powersave_nap;
443#endif
444 struct device_node *cpus, *firstcpu;
445 int i, ncpus = 0, boot_cpu = -1;
446 u32 *tbprop = NULL;
447
448 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
449 cpus = firstcpu = find_type_devices("cpu");
450 while(cpus != NULL) {
451 u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
452 char *stateprop = (char *)get_property(cpus, "state", NULL);
453 if (regprop != NULL && stateprop != NULL &&
454 !strncmp(stateprop, "running", 7))
455 boot_cpu = *regprop;
456 ++ncpus;
457 cpus = cpus->next;
458 }
459 if (boot_cpu == -1)
460 printk(KERN_WARNING "Couldn't detect boot CPU !\n");
461 if (boot_cpu != 0)
462 printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
463
464 if (machine_is_compatible("MacRISC4")) {
465 extern struct smp_ops_t core99_smp_ops;
466
467 core99_smp_ops.take_timebase = smp_generic_take_timebase;
468 core99_smp_ops.give_timebase = smp_generic_give_timebase;
469 } else {
470 if (firstcpu != NULL)
471 tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
472 if (tbprop)
473 core99_tb_gpio = *tbprop;
474 else
475 core99_tb_gpio = KL_GPIO_TB_ENABLE;
476 }
477
478 if (ncpus > 1) {
479 openpic_request_IPIs();
480 for (i = 1; i < ncpus; ++i)
481 smp_hw_index[i] = i;
482#ifdef CONFIG_6xx
483 powersave_nap = 0;
484#endif
485 core99_init_caches(0);
486 }
487
488 return ncpus;
489}
490
491static void __devinit smp_core99_kick_cpu(int nr)
492{
493 unsigned long save_vector, new_vector;
494 unsigned long flags;
495
496 volatile unsigned long *vector
497 = ((volatile unsigned long *)(KERNELBASE+0x100));
498 if (nr < 0 || nr > 3)
499 return;
500 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
501
502 local_irq_save(flags);
503 local_irq_disable();
504
505 /* Save reset vector */
506 save_vector = *vector;
507
508 /* Setup fake reset vector that does
509 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE
510 */
511 new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
512 *vector = 0x48000002 + new_vector - KERNELBASE;
513
514 /* flush data cache and inval instruction cache */
515 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
516
517 /* Put some life in our friend */
518 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
519
520 /* FIXME: We wait a bit for the CPU to take the exception, I should
521 * instead wait for the entry code to set something for me. Well,
522 * ideally, all that crap will be done in prom.c and the CPU left
523 * in a RAM-based wait loop like CHRP.
524 */
525 mdelay(1);
526
527 /* Restore our exception vector */
528 *vector = save_vector;
529 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
530
531 local_irq_restore(flags);
532 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
533}
534
535static void __devinit smp_core99_setup_cpu(int cpu_nr)
536{
537 /* Setup L2/L3 */
538 if (cpu_nr != 0)
539 core99_init_caches(cpu_nr);
540
541 /* Setup openpic */
542 do_openpic_setup_cpu();
543
544 if (cpu_nr == 0) {
545#ifdef CONFIG_POWER4
546 extern void g5_phy_disable_cpu1(void);
547
548 /* If we didn't start the second CPU, we must take
549 * it off the bus
550 */
551 if (machine_is_compatible("MacRISC4") &&
552 num_online_cpus() < 2)
553 g5_phy_disable_cpu1();
554#endif /* CONFIG_POWER4 */
555 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
556 }
557}
558
559/* not __init, called in sleep/wakeup code */
560void smp_core99_take_timebase(void)
561{
562 unsigned long flags;
563
564 /* tell the primary we're here */
565 sec_tb_reset = 1;
566 mb();
567
568 /* wait for the primary to set pri_tb_hi/lo */
569 while (sec_tb_reset < 2)
570 mb();
571
572 /* set our stuff the same as the primary */
573 local_irq_save(flags);
574 set_dec(1);
575 set_tb(pri_tb_hi, pri_tb_lo);
576 last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
577 mb();
578
579 /* tell the primary we're done */
580 sec_tb_reset = 0;
581 mb();
582 local_irq_restore(flags);
583}
584
585/* not __init, called in sleep/wakeup code */
586void smp_core99_give_timebase(void)
587{
588 unsigned long flags;
589 unsigned int t;
590
591 /* wait for the secondary to be in take_timebase */
592 for (t = 100000; t > 0 && !sec_tb_reset; --t)
593 udelay(10);
594 if (!sec_tb_reset) {
595 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
596 return;
597 }
598
599 /* freeze the timebase and read it */
600 /* disable interrupts so the timebase is disabled for the
601 shortest possible time */
602 local_irq_save(flags);
603 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
604 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
605 mb();
606 pri_tb_hi = get_tbu();
607 pri_tb_lo = get_tbl();
608 pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
609 mb();
610
611 /* tell the secondary we're ready */
612 sec_tb_reset = 2;
613 mb();
614
615 /* wait for the secondary to have taken it */
616 for (t = 100000; t > 0 && sec_tb_reset; --t)
617 udelay(10);
618 if (sec_tb_reset)
619 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
620 else
621 smp_tb_synchronized = 1;
622
623 /* Now, restart the timebase by leaving the GPIO to an open collector */
624 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
625 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
626 local_irq_restore(flags);
627}
628
629
630/* PowerSurge-style Macs */
631struct smp_ops_t psurge_smp_ops = {
632 .message_pass = smp_psurge_message_pass,
633 .probe = smp_psurge_probe,
634 .kick_cpu = smp_psurge_kick_cpu,
635 .setup_cpu = smp_psurge_setup_cpu,
636 .give_timebase = smp_psurge_give_timebase,
637 .take_timebase = smp_psurge_take_timebase,
638};
639
640/* Core99 Macs (dual G4s) */
641struct smp_ops_t core99_smp_ops = {
642 .message_pass = smp_openpic_message_pass,
643 .probe = smp_core99_probe,
644 .kick_cpu = smp_core99_kick_cpu,
645 .setup_cpu = smp_core99_setup_cpu,
646 .give_timebase = smp_core99_give_timebase,
647 .take_timebase = smp_core99_take_timebase,
648};
649
650#ifdef CONFIG_HOTPLUG_CPU
651
652int __cpu_disable(void)
653{
654 cpu_clear(smp_processor_id(), cpu_online_map);
655
656 /* XXX reset cpu affinity here */
657 openpic_set_priority(0xf);
658 asm volatile("mtdec %0" : : "r" (0x7fffffff));
659 mb();
660 udelay(20);
661 asm volatile("mtdec %0" : : "r" (0x7fffffff));
662 return 0;
663}
664
665extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */
666static int cpu_dead[NR_CPUS];
667
668void cpu_die(void)
669{
670 local_irq_disable();
671 cpu_dead[smp_processor_id()] = 1;
672 mb();
673 low_cpu_die();
674}
675
676void __cpu_die(unsigned int cpu)
677{
678 int timeout;
679
680 timeout = 1000;
681 while (!cpu_dead[cpu]) {
682 if (--timeout == 0) {
683 printk("CPU %u refused to die!\n", cpu);
684 break;
685 }
686 msleep(1);
687 }
688 cpu_callin_map[cpu] = 0;
689 cpu_dead[cpu] = 0;
690}
691
692#endif
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
deleted file mode 100644
index edb9fcc647..0000000000
--- a/arch/ppc/platforms/pmac_time.c
+++ /dev/null
@@ -1,291 +0,0 @@
1/*
2 * Support for periodic interrupts (100 per second) and for getting
3 * the current time from the RTC on Power Macintoshes.
4 *
5 * We use the decrementer register for our periodic interrupts.
6 *
7 * Paul Mackerras August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10#include <linux/config.h>
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/string.h>
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/time.h>
19#include <linux/adb.h>
20#include <linux/cuda.h>
21#include <linux/pmu.h>
22#include <linux/hardirq.h>
23
24#include <asm/sections.h>
25#include <asm/prom.h>
26#include <asm/system.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/machdep.h>
30#include <asm/time.h>
31#include <asm/nvram.h>
32
33/* Apparently the RTC stores seconds since 1 Jan 1904 */
34#define RTC_OFFSET 2082844800
35
36/*
37 * Calibrate the decrementer frequency with the VIA timer 1.
38 */
39#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
40
41/* VIA registers */
42#define RS 0x200 /* skip between registers */
43#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
44#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
45#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
46#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
47#define ACR (11*RS) /* Auxiliary control register */
48#define IFR (13*RS) /* Interrupt flag register */
49
50/* Bits in ACR */
51#define T1MODE 0xc0 /* Timer 1 mode */
52#define T1MODE_CONT 0x40 /* continuous interrupts */
53
54/* Bits in IFR and IER */
55#define T1_INT 0x40 /* Timer 1 interrupt */
56
57extern struct timezone sys_tz;
58
59long __init
60pmac_time_init(void)
61{
62#ifdef CONFIG_NVRAM
63 s32 delta = 0;
64 int dst;
65
66 delta = ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x9)) << 16;
67 delta |= ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xa)) << 8;
68 delta |= pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xb);
69 if (delta & 0x00800000UL)
70 delta |= 0xFF000000UL;
71 dst = ((pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x8) & 0x80) != 0);
72 printk("GMT Delta read from XPRAM: %d minutes, DST: %s\n", delta/60,
73 dst ? "on" : "off");
74 return delta;
75#else
76 return 0;
77#endif
78}
79
80unsigned long
81pmac_get_rtc_time(void)
82{
83#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
84 struct adb_request req;
85 unsigned long now;
86#endif
87
88 /* Get the time from the RTC */
89 switch (sys_ctrler) {
90#ifdef CONFIG_ADB_CUDA
91 case SYS_CTRLER_CUDA:
92 if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0)
93 return 0;
94 while (!req.complete)
95 cuda_poll();
96 if (req.reply_len != 7)
97 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
98 req.reply_len);
99 now = (req.reply[3] << 24) + (req.reply[4] << 16)
100 + (req.reply[5] << 8) + req.reply[6];
101 return now - RTC_OFFSET;
102#endif /* CONFIG_ADB_CUDA */
103#ifdef CONFIG_ADB_PMU
104 case SYS_CTRLER_PMU:
105 if (pmu_request(&req, NULL, 1, PMU_READ_RTC) < 0)
106 return 0;
107 while (!req.complete)
108 pmu_poll();
109 if (req.reply_len != 4)
110 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
111 req.reply_len);
112 now = (req.reply[0] << 24) + (req.reply[1] << 16)
113 + (req.reply[2] << 8) + req.reply[3];
114 return now - RTC_OFFSET;
115#endif /* CONFIG_ADB_PMU */
116 default: ;
117 }
118 return 0;
119}
120
121int
122pmac_set_rtc_time(unsigned long nowtime)
123{
124#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
125 struct adb_request req;
126#endif
127
128 nowtime += RTC_OFFSET;
129
130 switch (sys_ctrler) {
131#ifdef CONFIG_ADB_CUDA
132 case SYS_CTRLER_CUDA:
133 if (cuda_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
134 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
135 return 0;
136 while (!req.complete)
137 cuda_poll();
138 if ((req.reply_len != 3) && (req.reply_len != 7))
139 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
140 req.reply_len);
141 return 1;
142#endif /* CONFIG_ADB_CUDA */
143#ifdef CONFIG_ADB_PMU
144 case SYS_CTRLER_PMU:
145 if (pmu_request(&req, NULL, 5, PMU_SET_RTC,
146 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
147 return 0;
148 while (!req.complete)
149 pmu_poll();
150 if (req.reply_len != 0)
151 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
152 req.reply_len);
153 return 1;
154#endif /* CONFIG_ADB_PMU */
155 default:
156 return 0;
157 }
158}
159
160/*
161 * Calibrate the decrementer register using VIA timer 1.
162 * This is used both on powermacs and CHRP machines.
163 */
164int __init
165via_calibrate_decr(void)
166{
167 struct device_node *vias;
168 volatile unsigned char __iomem *via;
169 int count = VIA_TIMER_FREQ_6 / 100;
170 unsigned int dstart, dend;
171
172 vias = find_devices("via-cuda");
173 if (vias == 0)
174 vias = find_devices("via-pmu");
175 if (vias == 0)
176 vias = find_devices("via");
177 if (vias == 0 || vias->n_addrs == 0)
178 return 0;
179 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
180
181 /* set timer 1 for continuous interrupts */
182 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
183 /* set the counter to a small value */
184 out_8(&via[T1CH], 2);
185 /* set the latch to `count' */
186 out_8(&via[T1LL], count);
187 out_8(&via[T1LH], count >> 8);
188 /* wait until it hits 0 */
189 while ((in_8(&via[IFR]) & T1_INT) == 0)
190 ;
191 dstart = get_dec();
192 /* clear the interrupt & wait until it hits 0 again */
193 in_8(&via[T1CL]);
194 while ((in_8(&via[IFR]) & T1_INT) == 0)
195 ;
196 dend = get_dec();
197
198 tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
199 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
200
201 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
202 tb_ticks_per_jiffy, dstart - dend);
203
204 iounmap(via);
205
206 return 1;
207}
208
209#ifdef CONFIG_PM
210/*
211 * Reset the time after a sleep.
212 */
213static int
214time_sleep_notify(struct pmu_sleep_notifier *self, int when)
215{
216 static unsigned long time_diff;
217 unsigned long flags;
218 unsigned long seq;
219
220 switch (when) {
221 case PBOOK_SLEEP_NOW:
222 do {
223 seq = read_seqbegin_irqsave(&xtime_lock, flags);
224 time_diff = xtime.tv_sec - pmac_get_rtc_time();
225 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
226 break;
227 case PBOOK_WAKE:
228 write_seqlock_irqsave(&xtime_lock, flags);
229 xtime.tv_sec = pmac_get_rtc_time() + time_diff;
230 xtime.tv_nsec = 0;
231 last_rtc_update = xtime.tv_sec;
232 write_sequnlock_irqrestore(&xtime_lock, flags);
233 break;
234 }
235 return PBOOK_SLEEP_OK;
236}
237
238static struct pmu_sleep_notifier time_sleep_notifier = {
239 time_sleep_notify, SLEEP_LEVEL_MISC,
240};
241#endif /* CONFIG_PM */
242
243/*
244 * Query the OF and get the decr frequency.
245 * This was taken from the pmac time_init() when merging the prep/pmac
246 * time functions.
247 */
248void __init
249pmac_calibrate_decr(void)
250{
251 struct device_node *cpu;
252 unsigned int freq, *fp;
253
254#ifdef CONFIG_PM
255 pmu_register_sleep_notifier(&time_sleep_notifier);
256#endif /* CONFIG_PM */
257
258 /* We assume MacRISC2 machines have correct device-tree
259 * calibration. That's better since the VIA itself seems
260 * to be slightly off. --BenH
261 */
262 if (!machine_is_compatible("MacRISC2") &&
263 !machine_is_compatible("MacRISC3") &&
264 !machine_is_compatible("MacRISC4"))
265 if (via_calibrate_decr())
266 return;
267
268 /* Special case: QuickSilver G4s seem to have a badly calibrated
269 * timebase-frequency in OF, VIA is much better on these. We should
270 * probably implement calibration based on the KL timer on these
271 * machines anyway... -BenH
272 */
273 if (machine_is_compatible("PowerMac3,5"))
274 if (via_calibrate_decr())
275 return;
276 /*
277 * The cpu node should have a timebase-frequency property
278 * to tell us the rate at which the decrementer counts.
279 */
280 cpu = find_type_devices("cpu");
281 if (cpu == 0)
282 panic("can't find cpu node in time_init");
283 fp = (unsigned int *) get_property(cpu, "timebase-frequency", NULL);
284 if (fp == 0)
285 panic("can't get cpu timebase frequency");
286 freq = *fp;
287 printk("time_init: decrementer frequency = %u.%.6u MHz\n",
288 freq/1000000, freq%1000000);
289 tb_ticks_per_jiffy = freq / HZ;
290 tb_to_us = mulhwu_scale_factor(freq, 1000000);
291}
diff --git a/arch/ppc/platforms/pq2ads.c b/arch/ppc/platforms/pq2ads.c
index 6a1475c1e1..71c9fca1fe 100644
--- a/arch/ppc/platforms/pq2ads.c
+++ b/arch/ppc/platforms/pq2ads.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * PQ2ADS platform support 4 * PQ2ADS platform support
5 * 5 *
6 * Author: Kumar Gala <kumar.gala@freescale.com> 6 * Author: Kumar Gala <galak@kernel.crashing.org>
7 * Derived from: est8260_setup.c by Allen Curtis 7 * Derived from: est8260_setup.c by Allen Curtis
8 * 8 *
9 * Copyright 2004 Freescale Semiconductor, Inc. 9 * Copyright 2004 Freescale Semiconductor, Inc.
diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c
index 4415748071..d065358020 100644
--- a/arch/ppc/platforms/prep_setup.c
+++ b/arch/ppc/platforms/prep_setup.c
@@ -72,7 +72,6 @@
72 72
73TODC_ALLOC(); 73TODC_ALLOC();
74 74
75unsigned char ucSystemType;
76unsigned char ucBoardRev; 75unsigned char ucBoardRev;
77unsigned char ucBoardRevMaj, ucBoardRevMin; 76unsigned char ucBoardRevMaj, ucBoardRevMin;
78 77
@@ -954,7 +953,6 @@ prep_calibrate_decr(void)
954static void __init 953static void __init
955prep_init_IRQ(void) 954prep_init_IRQ(void)
956{ 955{
957 int i;
958 unsigned int pci_viddid, pci_did; 956 unsigned int pci_viddid, pci_did;
959 957
960 if (OpenPIC_Addr != NULL) { 958 if (OpenPIC_Addr != NULL) {
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 5b7f2b80e5..159dcd92a6 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -39,8 +39,6 @@ obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
39 ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o 39 ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o
40obj-$(CONFIG_PCI_QSPAN) += qspan_pci.o 40obj-$(CONFIG_PCI_QSPAN) += qspan_pci.o
41obj-$(CONFIG_PPC_OF) += prom_init.o prom.o 41obj-$(CONFIG_PPC_OF) += prom_init.o prom.o
42obj-$(CONFIG_PPC_PMAC) += open_pic.o
43obj-$(CONFIG_POWER4) += open_pic2.o
44obj-$(CONFIG_PPC_CHRP) += open_pic.o 42obj-$(CONFIG_PPC_CHRP) += open_pic.o
45obj-$(CONFIG_PPC_PREP) += open_pic.o todc_time.o 43obj-$(CONFIG_PPC_PREP) += open_pic.o todc_time.o
46obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o 44obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o
@@ -96,7 +94,7 @@ ifeq ($(CONFIG_85xx),y)
96obj-$(CONFIG_PCI) += pci_auto.o 94obj-$(CONFIG_PCI) += pci_auto.o
97endif 95endif
98obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o 96obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
99obj-$(CONFIG_83xx) += ipic.o ppc83xx_setup.o ppc_sys.o \ 97obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
100 mpc83xx_sys.o mpc83xx_devices.o 98 mpc83xx_sys.o mpc83xx_devices.o
101ifeq ($(CONFIG_83xx),y) 99ifeq ($(CONFIG_83xx),y)
102obj-$(CONFIG_PCI) += pci_auto.o 100obj-$(CONFIG_PCI) += pci_auto.o
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
deleted file mode 100644
index 8f01e0f1d8..0000000000
--- a/arch/ppc/syslib/ipic.c
+++ /dev/null
@@ -1,646 +0,0 @@
1/*
2 * include/asm-ppc/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26
27#include "ipic.h"
28
29static struct ipic p_ipic;
30static struct ipic * primary_ipic;
31
32static struct ipic_info ipic_info[] = {
33 [9] = {
34 .pend = IPIC_SIPNR_H,
35 .mask = IPIC_SIMSR_H,
36 .prio = IPIC_SIPRR_D,
37 .force = IPIC_SIFCR_H,
38 .bit = 24,
39 .prio_mask = 0,
40 },
41 [10] = {
42 .pend = IPIC_SIPNR_H,
43 .mask = IPIC_SIMSR_H,
44 .prio = IPIC_SIPRR_D,
45 .force = IPIC_SIFCR_H,
46 .bit = 25,
47 .prio_mask = 1,
48 },
49 [11] = {
50 .pend = IPIC_SIPNR_H,
51 .mask = IPIC_SIMSR_H,
52 .prio = IPIC_SIPRR_D,
53 .force = IPIC_SIFCR_H,
54 .bit = 26,
55 .prio_mask = 2,
56 },
57 [14] = {
58 .pend = IPIC_SIPNR_H,
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 29,
63 .prio_mask = 5,
64 },
65 [15] = {
66 .pend = IPIC_SIPNR_H,
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_D,
69 .force = IPIC_SIFCR_H,
70 .bit = 30,
71 .prio_mask = 6,
72 },
73 [16] = {
74 .pend = IPIC_SIPNR_H,
75 .mask = IPIC_SIMSR_H,
76 .prio = IPIC_SIPRR_D,
77 .force = IPIC_SIFCR_H,
78 .bit = 31,
79 .prio_mask = 7,
80 },
81 [17] = {
82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR,
86 .bit = 1,
87 .prio_mask = 5,
88 },
89 [18] = {
90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR,
94 .bit = 2,
95 .prio_mask = 6,
96 },
97 [19] = {
98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR,
102 .bit = 3,
103 .prio_mask = 7,
104 },
105 [20] = {
106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR,
110 .bit = 4,
111 .prio_mask = 4,
112 },
113 [21] = {
114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR,
118 .bit = 5,
119 .prio_mask = 5,
120 },
121 [22] = {
122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR,
126 .bit = 6,
127 .prio_mask = 6,
128 },
129 [23] = {
130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR,
134 .bit = 7,
135 .prio_mask = 7,
136 },
137 [32] = {
138 .pend = IPIC_SIPNR_H,
139 .mask = IPIC_SIMSR_H,
140 .prio = IPIC_SIPRR_A,
141 .force = IPIC_SIFCR_H,
142 .bit = 0,
143 .prio_mask = 0,
144 },
145 [33] = {
146 .pend = IPIC_SIPNR_H,
147 .mask = IPIC_SIMSR_H,
148 .prio = IPIC_SIPRR_A,
149 .force = IPIC_SIFCR_H,
150 .bit = 1,
151 .prio_mask = 1,
152 },
153 [34] = {
154 .pend = IPIC_SIPNR_H,
155 .mask = IPIC_SIMSR_H,
156 .prio = IPIC_SIPRR_A,
157 .force = IPIC_SIFCR_H,
158 .bit = 2,
159 .prio_mask = 2,
160 },
161 [35] = {
162 .pend = IPIC_SIPNR_H,
163 .mask = IPIC_SIMSR_H,
164 .prio = IPIC_SIPRR_A,
165 .force = IPIC_SIFCR_H,
166 .bit = 3,
167 .prio_mask = 3,
168 },
169 [36] = {
170 .pend = IPIC_SIPNR_H,
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 4,
175 .prio_mask = 4,
176 },
177 [37] = {
178 .pend = IPIC_SIPNR_H,
179 .mask = IPIC_SIMSR_H,
180 .prio = IPIC_SIPRR_A,
181 .force = IPIC_SIFCR_H,
182 .bit = 5,
183 .prio_mask = 5,
184 },
185 [38] = {
186 .pend = IPIC_SIPNR_H,
187 .mask = IPIC_SIMSR_H,
188 .prio = IPIC_SIPRR_A,
189 .force = IPIC_SIFCR_H,
190 .bit = 6,
191 .prio_mask = 6,
192 },
193 [39] = {
194 .pend = IPIC_SIPNR_H,
195 .mask = IPIC_SIMSR_H,
196 .prio = IPIC_SIPRR_A,
197 .force = IPIC_SIFCR_H,
198 .bit = 7,
199 .prio_mask = 7,
200 },
201 [48] = {
202 .pend = IPIC_SEPNR,
203 .mask = IPIC_SEMSR,
204 .prio = IPIC_SMPRR_A,
205 .force = IPIC_SEFCR,
206 .bit = 0,
207 .prio_mask = 4,
208 },
209 [64] = {
210 .pend = IPIC_SIPNR_H,
211 .mask = IPIC_SIMSR_L,
212 .prio = IPIC_SMPRR_A,
213 .force = IPIC_SIFCR_L,
214 .bit = 0,
215 .prio_mask = 0,
216 },
217 [65] = {
218 .pend = IPIC_SIPNR_H,
219 .mask = IPIC_SIMSR_L,
220 .prio = IPIC_SMPRR_A,
221 .force = IPIC_SIFCR_L,
222 .bit = 1,
223 .prio_mask = 1,
224 },
225 [66] = {
226 .pend = IPIC_SIPNR_H,
227 .mask = IPIC_SIMSR_L,
228 .prio = IPIC_SMPRR_A,
229 .force = IPIC_SIFCR_L,
230 .bit = 2,
231 .prio_mask = 2,
232 },
233 [67] = {
234 .pend = IPIC_SIPNR_H,
235 .mask = IPIC_SIMSR_L,
236 .prio = IPIC_SMPRR_A,
237 .force = IPIC_SIFCR_L,
238 .bit = 3,
239 .prio_mask = 3,
240 },
241 [68] = {
242 .pend = IPIC_SIPNR_H,
243 .mask = IPIC_SIMSR_L,
244 .prio = IPIC_SMPRR_B,
245 .force = IPIC_SIFCR_L,
246 .bit = 4,
247 .prio_mask = 0,
248 },
249 [69] = {
250 .pend = IPIC_SIPNR_H,
251 .mask = IPIC_SIMSR_L,
252 .prio = IPIC_SMPRR_B,
253 .force = IPIC_SIFCR_L,
254 .bit = 5,
255 .prio_mask = 1,
256 },
257 [70] = {
258 .pend = IPIC_SIPNR_H,
259 .mask = IPIC_SIMSR_L,
260 .prio = IPIC_SMPRR_B,
261 .force = IPIC_SIFCR_L,
262 .bit = 6,
263 .prio_mask = 2,
264 },
265 [71] = {
266 .pend = IPIC_SIPNR_H,
267 .mask = IPIC_SIMSR_L,
268 .prio = IPIC_SMPRR_B,
269 .force = IPIC_SIFCR_L,
270 .bit = 7,
271 .prio_mask = 3,
272 },
273 [72] = {
274 .pend = IPIC_SIPNR_H,
275 .mask = IPIC_SIMSR_L,
276 .prio = 0,
277 .force = IPIC_SIFCR_L,
278 .bit = 8,
279 },
280 [73] = {
281 .pend = IPIC_SIPNR_H,
282 .mask = IPIC_SIMSR_L,
283 .prio = 0,
284 .force = IPIC_SIFCR_L,
285 .bit = 9,
286 },
287 [74] = {
288 .pend = IPIC_SIPNR_H,
289 .mask = IPIC_SIMSR_L,
290 .prio = 0,
291 .force = IPIC_SIFCR_L,
292 .bit = 10,
293 },
294 [75] = {
295 .pend = IPIC_SIPNR_H,
296 .mask = IPIC_SIMSR_L,
297 .prio = 0,
298 .force = IPIC_SIFCR_L,
299 .bit = 11,
300 },
301 [76] = {
302 .pend = IPIC_SIPNR_H,
303 .mask = IPIC_SIMSR_L,
304 .prio = 0,
305 .force = IPIC_SIFCR_L,
306 .bit = 12,
307 },
308 [77] = {
309 .pend = IPIC_SIPNR_H,
310 .mask = IPIC_SIMSR_L,
311 .prio = 0,
312 .force = IPIC_SIFCR_L,
313 .bit = 13,
314 },
315 [78] = {
316 .pend = IPIC_SIPNR_H,
317 .mask = IPIC_SIMSR_L,
318 .prio = 0,
319 .force = IPIC_SIFCR_L,
320 .bit = 14,
321 },
322 [79] = {
323 .pend = IPIC_SIPNR_H,
324 .mask = IPIC_SIMSR_L,
325 .prio = 0,
326 .force = IPIC_SIFCR_L,
327 .bit = 15,
328 },
329 [80] = {
330 .pend = IPIC_SIPNR_H,
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 16,
335 },
336 [84] = {
337 .pend = IPIC_SIPNR_H,
338 .mask = IPIC_SIMSR_L,
339 .prio = 0,
340 .force = IPIC_SIFCR_L,
341 .bit = 20,
342 },
343 [85] = {
344 .pend = IPIC_SIPNR_H,
345 .mask = IPIC_SIMSR_L,
346 .prio = 0,
347 .force = IPIC_SIFCR_L,
348 .bit = 21,
349 },
350 [90] = {
351 .pend = IPIC_SIPNR_H,
352 .mask = IPIC_SIMSR_L,
353 .prio = 0,
354 .force = IPIC_SIFCR_L,
355 .bit = 26,
356 },
357 [91] = {
358 .pend = IPIC_SIPNR_H,
359 .mask = IPIC_SIMSR_L,
360 .prio = 0,
361 .force = IPIC_SIFCR_L,
362 .bit = 27,
363 },
364};
365
366static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
367{
368 return in_be32(base + (reg >> 2));
369}
370
371static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
372{
373 out_be32(base + (reg >> 2), value);
374}
375
376static inline struct ipic * ipic_from_irq(unsigned int irq)
377{
378 return primary_ipic;
379}
380
381static void ipic_enable_irq(unsigned int irq)
382{
383 struct ipic *ipic = ipic_from_irq(irq);
384 unsigned int src = irq - ipic->irq_offset;
385 u32 temp;
386
387 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp);
390}
391
392static void ipic_disable_irq(unsigned int irq)
393{
394 struct ipic *ipic = ipic_from_irq(irq);
395 unsigned int src = irq - ipic->irq_offset;
396 u32 temp;
397
398 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp);
401}
402
403static void ipic_disable_irq_and_ack(unsigned int irq)
404{
405 struct ipic *ipic = ipic_from_irq(irq);
406 unsigned int src = irq - ipic->irq_offset;
407 u32 temp;
408
409 ipic_disable_irq(irq);
410
411 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp);
414}
415
416static void ipic_end_irq(unsigned int irq)
417{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
419 ipic_enable_irq(irq);
420}
421
422struct hw_interrupt_type ipic = {
423 .typename = " IPIC ",
424 .enable = ipic_enable_irq,
425 .disable = ipic_disable_irq,
426 .ack = ipic_disable_irq_and_ack,
427 .end = ipic_end_irq,
428};
429
430void __init ipic_init(phys_addr_t phys_addr,
431 unsigned int flags,
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{
436 u32 i, temp = 0;
437
438 primary_ipic = &p_ipic;
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440
441 primary_ipic->irq_offset = irq_offset;
442
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
444
445 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */
447 if (flags & IPIC_SPREADMODE_GRP_A)
448 temp |= SICFR_IPSA;
449 if (flags & IPIC_SPREADMODE_GRP_D)
450 temp |= SICFR_IPSD;
451 if (flags & IPIC_SPREADMODE_MIX_A)
452 temp |= SICFR_MPSA;
453 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB;
455
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
457
458 /* handle MCP route */
459 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
463
464 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
466
467 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0;
469 else
470 temp &= ~SEMSR_SIRQ0;
471
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].handler = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478
479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493}
494
495int ipic_set_priority(unsigned int irq, unsigned int priority)
496{
497 struct ipic *ipic = ipic_from_irq(irq);
498 unsigned int src = irq - ipic->irq_offset;
499 u32 temp;
500
501 if (priority > 7)
502 return -EINVAL;
503 if (src > 127)
504 return -EINVAL;
505 if (ipic_info[src].prio == 0)
506 return -EINVAL;
507
508 temp = ipic_read(ipic->regs, ipic_info[src].prio);
509
510 if (priority < 4) {
511 temp &= ~(0x7 << (20 + (3 - priority) * 3));
512 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
513 } else {
514 temp &= ~(0x7 << (4 + (7 - priority) * 3));
515 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
516 }
517
518 ipic_write(ipic->regs, ipic_info[src].prio, temp);
519
520 return 0;
521}
522
523void ipic_set_highest_priority(unsigned int irq)
524{
525 struct ipic *ipic = ipic_from_irq(irq);
526 unsigned int src = irq - ipic->irq_offset;
527 u32 temp;
528
529 temp = ipic_read(ipic->regs, IPIC_SICFR);
530
531 /* clear and set HPI */
532 temp &= 0x7f000000;
533 temp |= (src & 0x7f) << 24;
534
535 ipic_write(ipic->regs, IPIC_SICFR, temp);
536}
537
538void ipic_set_default_priority(void)
539{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571}
572
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
574{
575 struct ipic *ipic = primary_ipic;
576 u32 temp;
577
578 temp = ipic_read(ipic->regs, IPIC_SERMR);
579 temp |= (1 << (31 - mcp_irq));
580 ipic_write(ipic->regs, IPIC_SERMR, temp);
581}
582
583void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
584{
585 struct ipic *ipic = primary_ipic;
586 u32 temp;
587
588 temp = ipic_read(ipic->regs, IPIC_SERMR);
589 temp &= (1 << (31 - mcp_irq));
590 ipic_write(ipic->regs, IPIC_SERMR, temp);
591}
592
593u32 ipic_get_mcp_status(void)
594{
595 return ipic_read(primary_ipic->regs, IPIC_SERMR);
596}
597
598void ipic_clear_mcp_status(u32 mask)
599{
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601}
602
603/* Return an interrupt vector or -1 if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs)
605{
606 int irq;
607
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
609
610 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1;
612
613 return irq;
614}
615
616static struct sysdev_class ipic_sysclass = {
617 set_kset_name("ipic"),
618};
619
620static struct sys_device device_ipic = {
621 .id = 0,
622 .cls = &ipic_sysclass,
623};
624
625static int __init init_ipic_sysfs(void)
626{
627 int rc;
628
629 if (!primary_ipic->regs)
630 return -ENODEV;
631 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
632
633 rc = sysdev_class_register(&ipic_sysclass);
634 if (rc) {
635 printk(KERN_ERR "Failed registering ipic sys class\n");
636 return -ENODEV;
637 }
638 rc = sysdev_register(&device_ipic);
639 if (rc) {
640 printk(KERN_ERR "Failed registering ipic sys device\n");
641 return -ENODEV;
642 }
643 return 0;
644}
645
646subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
deleted file mode 100644
index 2b56a4fcf3..0000000000
--- a/arch/ppc/syslib/ipic.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * arch/ppc/kernel/ipic.h
3 *
4 * IPIC private definitions and structure.
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2005 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __IPIC_H__
16#define __IPIC_H__
17
18#include <asm/ipic.h>
19
20#define MPC83xx_IPIC_SIZE (0x00100)
21
22/* System Global Interrupt Configuration Register */
23#define SICFR_IPSA 0x00010000
24#define SICFR_IPSD 0x00080000
25#define SICFR_MPSA 0x00200000
26#define SICFR_MPSB 0x00400000
27
28/* System External Interrupt Mask Register */
29#define SEMSR_SIRQ0 0x00008000
30
31/* System Error Control Register */
32#define SERCR_MCPR 0x00000001
33
34struct ipic {
35 volatile u32 __iomem *regs;
36 unsigned int irq_offset;
37};
38
39struct ipic_info {
40 u8 pend; /* pending register offset from base */
41 u8 mask; /* mask register offset from base */
42 u8 prio; /* priority register offset from base */
43 u8 force; /* force register offset from base */
44 u8 bit; /* register bit position (as per doc)
45 bit mask = 1 << (31 - bit) */
46 u8 prio_mask; /* priority mask value */
47};
48
49#endif /* __IPIC_H__ */
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
index 1d1c3956c1..1941a8c7ca 100644
--- a/arch/ppc/syslib/m82xx_pci.c
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -248,7 +248,8 @@ pq2ads_setup_pci(struct pci_controller *hose)
248 pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * 248 pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
249 ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); 249 ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
250 freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div)); 250 freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
251 time = (int)666666/freq; 251 time = (int)66666666/freq;
252
252 /* due to PCI Local Bus spec, some devices needs to wait such a long 253 /* due to PCI Local Bus spec, some devices needs to wait such a long
253 time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */ 254 time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
254 printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq, 255 printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 1cc3abe6fa..688616de3c 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -135,6 +135,16 @@ static struct irqaction tbint_irqaction = {
135 .name = "tbint", 135 .name = "tbint",
136}; 136};
137 137
138/* per-board overridable init_internal_rtc() function. */
139void __init __attribute__ ((weak))
140init_internal_rtc(void)
141{
142 /* Disable the RTC one second and alarm interrupts. */
143 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
144 /* Enable the RTC */
145 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
146}
147
138/* The decrementer counts at the system (internal) clock frequency divided by 148/* The decrementer counts at the system (internal) clock frequency divided by
139 * sixteen, or external oscillator divided by four. We force the processor 149 * sixteen, or external oscillator divided by four. We force the processor
140 * to use system clock divided by sixteen. 150 * to use system clock divided by sixteen.
@@ -183,10 +193,7 @@ void __init m8xx_calibrate_decr(void)
183 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY); 193 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
184 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY); 194 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
185 195
186 /* Disable the RTC one second and alarm interrupts. */ 196 init_internal_rtc();
187 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
188 /* Enable the RTC */
189 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
190 197
191 /* Enabling the decrementer also enables the timebase interrupts 198 /* Enabling the decrementer also enables the timebase interrupts
192 * (or from the other point of view, to get decrementer interrupts 199 * (or from the other point of view, to get decrementer interrupts
diff --git a/arch/ppc/syslib/m8xx_wdt.c b/arch/ppc/syslib/m8xx_wdt.c
index a21632d37e..df6c9557b8 100644
--- a/arch/ppc/syslib/m8xx_wdt.c
+++ b/arch/ppc/syslib/m8xx_wdt.c
@@ -19,6 +19,7 @@
19#include <syslib/m8xx_wdt.h> 19#include <syslib/m8xx_wdt.h>
20 20
21static int wdt_timeout; 21static int wdt_timeout;
22int m8xx_has_internal_rtc = 0;
22 23
23static irqreturn_t m8xx_wdt_interrupt(int, void *, struct pt_regs *); 24static irqreturn_t m8xx_wdt_interrupt(int, void *, struct pt_regs *);
24static struct irqaction m8xx_wdt_irqaction = { 25static struct irqaction m8xx_wdt_irqaction = {
@@ -45,35 +46,15 @@ static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs)
45 return IRQ_HANDLED; 46 return IRQ_HANDLED;
46} 47}
47 48
48void __init m8xx_wdt_handler_install(bd_t * binfo) 49#define SYPCR_SWP 0x1
50#define SYPCR_SWE 0x4
51
52
53void __init m8xx_wdt_install_irq(volatile immap_t *imap, bd_t *binfo)
49{ 54{
50 volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
51 u32 pitc; 55 u32 pitc;
52 u32 sypcr;
53 u32 pitrtclk; 56 u32 pitrtclk;
54 57
55 sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
56
57 if (!(sypcr & 0x04)) {
58 printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
59 sypcr);
60 return;
61 }
62
63 m8xx_wdt_reset();
64
65 printk(KERN_NOTICE
66 "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
67 (sypcr >> 16), sypcr & 0x01);
68
69 wdt_timeout = (sypcr >> 16) & 0xFFFF;
70
71 if (!wdt_timeout)
72 wdt_timeout = 0xFFFF;
73
74 if (sypcr & 0x01)
75 wdt_timeout *= 2048;
76
77 /* 58 /*
78 * Fire trigger if half of the wdt ticked down 59 * Fire trigger if half of the wdt ticked down
79 */ 60 */
@@ -98,6 +79,67 @@ void __init m8xx_wdt_handler_install(bd_t * binfo)
98 printk(KERN_NOTICE 79 printk(KERN_NOTICE
99 "m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n", pitc); 80 "m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n", pitc);
100 81
82}
83
84static void m8xx_wdt_timer_func(unsigned long data);
85
86static struct timer_list m8xx_wdt_timer =
87 TIMER_INITIALIZER(m8xx_wdt_timer_func, 0, 0);
88
89void m8xx_wdt_stop_timer(void)
90{
91 del_timer(&m8xx_wdt_timer);
92}
93
94void m8xx_wdt_install_timer(void)
95{
96 m8xx_wdt_timer.expires = jiffies + (HZ/2);
97 add_timer(&m8xx_wdt_timer);
98}
99
100static void m8xx_wdt_timer_func(unsigned long data)
101{
102 m8xx_wdt_reset();
103 m8xx_wdt_install_timer();
104}
105
106void __init m8xx_wdt_handler_install(bd_t * binfo)
107{
108 volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
109 u32 sypcr;
110
111 sypcr = in_be32(&imap->im_siu_conf.sc_sypcr);
112
113 if (!(sypcr & SYPCR_SWE)) {
114 printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
115 sypcr);
116 return;
117 }
118
119 m8xx_wdt_reset();
120
121 printk(KERN_NOTICE
122 "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
123 (sypcr >> 16), sypcr & SYPCR_SWP);
124
125 wdt_timeout = (sypcr >> 16) & 0xFFFF;
126
127 if (!wdt_timeout)
128 wdt_timeout = 0xFFFF;
129
130 if (sypcr & SYPCR_SWP)
131 wdt_timeout *= 2048;
132
133 m8xx_has_internal_rtc = in_be16(&imap->im_sit.sit_rtcsc) & RTCSC_RTE;
134
135 /* if the internal RTC is off use a kernel timer */
136 if (!m8xx_has_internal_rtc) {
137 if (wdt_timeout < (binfo->bi_intfreq/HZ))
138 printk(KERN_ERR "m8xx_wdt: timeout too short for ktimer!\n");
139 m8xx_wdt_install_timer();
140 } else
141 m8xx_wdt_install_irq(imap, binfo);
142
101 wdt_timeout /= binfo->bi_intfreq; 143 wdt_timeout /= binfo->bi_intfreq;
102} 144}
103 145
diff --git a/arch/ppc/syslib/m8xx_wdt.h b/arch/ppc/syslib/m8xx_wdt.h
index 0d81a9f815..e75835f001 100644
--- a/arch/ppc/syslib/m8xx_wdt.h
+++ b/arch/ppc/syslib/m8xx_wdt.h
@@ -9,8 +9,12 @@
9#ifndef _PPC_SYSLIB_M8XX_WDT_H 9#ifndef _PPC_SYSLIB_M8XX_WDT_H
10#define _PPC_SYSLIB_M8XX_WDT_H 10#define _PPC_SYSLIB_M8XX_WDT_H
11 11
12extern int m8xx_has_internal_rtc;
13
12extern void m8xx_wdt_handler_install(bd_t * binfo); 14extern void m8xx_wdt_handler_install(bd_t * binfo);
13extern int m8xx_wdt_get_timeout(void); 15extern int m8xx_wdt_get_timeout(void);
14extern void m8xx_wdt_reset(void); 16extern void m8xx_wdt_reset(void);
17extern void m8xx_wdt_install_timer(void);
18extern void m8xx_wdt_stop_timer(void);
15 19
16#endif /* _PPC_SYSLIB_M8XX_WDT_H */ 20#endif /* _PPC_SYSLIB_M8XX_WDT_H */
diff --git a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c
index 4ac19080eb..313c96ec7e 100644
--- a/arch/ppc/syslib/mpc52xx_pci.c
+++ b/arch/ppc/syslib/mpc52xx_pci.c
@@ -24,6 +24,12 @@
24#include <asm/machdep.h> 24#include <asm/machdep.h>
25 25
26 26
27/* This macro is defined to activate the workaround for the bug
28 435 of the MPC5200 (L25R). With it activated, we don't do any
29 32 bits configuration access during type-1 cycles */
30#define MPC5200_BUG_435_WORKAROUND
31
32
27static int 33static int
28mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 34mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
29 int offset, int len, u32 *val) 35 int offset, int len, u32 *val)
@@ -40,17 +46,39 @@ mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
40 ((bus->number - hose->bus_offset) << 16) | 46 ((bus->number - hose->bus_offset) << 16) |
41 (devfn << 8) | 47 (devfn << 8) |
42 (offset & 0xfc)); 48 (offset & 0xfc));
49 mb();
50
51#ifdef MPC5200_BUG_435_WORKAROUND
52 if (bus->number != hose->bus_offset) {
53 switch (len) {
54 case 1:
55 value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3));
56 break;
57 case 2:
58 value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1));
59 break;
60
61 default:
62 value = in_le16((u16 __iomem *)hose->cfg_data) |
63 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
64 break;
65 }
66 }
67 else
68#endif
69 {
70 value = in_le32(hose->cfg_data);
43 71
44 value = in_le32(hose->cfg_data); 72 if (len != 4) {
45 73 value >>= ((offset & 0x3) << 3);
46 if (len != 4) { 74 value &= 0xffffffff >> (32 - (len << 3));
47 value >>= ((offset & 0x3) << 3); 75 }
48 value &= 0xffffffff >> (32 - (len << 3));
49 } 76 }
50 77
51 *val = value; 78 *val = value;
52 79
53 out_be32(hose->cfg_addr, 0); 80 out_be32(hose->cfg_addr, 0);
81 mb();
54 82
55 return PCIBIOS_SUCCESSFUL; 83 return PCIBIOS_SUCCESSFUL;
56} 84}
@@ -71,21 +99,48 @@ mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
71 ((bus->number - hose->bus_offset) << 16) | 99 ((bus->number - hose->bus_offset) << 16) |
72 (devfn << 8) | 100 (devfn << 8) |
73 (offset & 0xfc)); 101 (offset & 0xfc));
102 mb();
103
104#ifdef MPC5200_BUG_435_WORKAROUND
105 if (bus->number != hose->bus_offset) {
106 switch (len) {
107 case 1:
108 out_8(((u8 __iomem *)hose->cfg_data) +
109 (offset & 3), val);
110 break;
111 case 2:
112 out_le16(((u16 __iomem *)hose->cfg_data) +
113 ((offset>>1) & 1), val);
114 break;
115
116 default:
117 out_le16((u16 __iomem *)hose->cfg_data,
118 (u16)val);
119 out_le16(((u16 __iomem *)hose->cfg_data) + 1,
120 (u16)(val>>16));
121 break;
122 }
123 }
124 else
125#endif
126 {
127 if (len != 4) {
128 value = in_le32(hose->cfg_data);
74 129
75 if (len != 4) { 130 offset = (offset & 0x3) << 3;
76 value = in_le32(hose->cfg_data); 131 mask = (0xffffffff >> (32 - (len << 3)));
132 mask <<= offset;
77 133
78 offset = (offset & 0x3) << 3; 134 value &= ~mask;
79 mask = (0xffffffff >> (32 - (len << 3))); 135 val = value | ((val << offset) & mask);
80 mask <<= offset; 136 }
81 137
82 value &= ~mask; 138 out_le32(hose->cfg_data, val);
83 val = value | ((val << offset) & mask);
84 } 139 }
85 140 mb();
86 out_le32(hose->cfg_data, val);
87 141
88 out_be32(hose->cfg_addr, 0); 142 out_be32(hose->cfg_addr, 0);
143 mb();
89 144
90 return PCIBIOS_SUCCESSFUL; 145 return PCIBIOS_SUCCESSFUL;
91} 146}
@@ -99,9 +154,12 @@ static struct pci_ops mpc52xx_pci_ops = {
99static void __init 154static void __init
100mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs) 155mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
101{ 156{
157 u32 tmp;
102 158
103 /* Setup control regs */ 159 /* Setup control regs */
104 /* Nothing to do afaik */ 160 tmp = in_be32(&pci_regs->scr);
161 tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
162 out_be32(&pci_regs->scr, tmp);
105 163
106 /* Setup windows */ 164 /* Setup windows */
107 out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION( 165 out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
@@ -142,16 +200,15 @@ mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
142 /* Not necessary and can be a bad thing if for example the bootloader 200 /* Not necessary and can be a bad thing if for example the bootloader
143 is displaying a splash screen or ... Just left here for 201 is displaying a splash screen or ... Just left here for
144 documentation purpose if anyone need it */ 202 documentation purpose if anyone need it */
145#if 0
146 u32 tmp;
147 tmp = in_be32(&pci_regs->gscr); 203 tmp = in_be32(&pci_regs->gscr);
204#if 0
148 out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR); 205 out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
149 udelay(50); 206 udelay(50);
150 out_be32(&pci_regs->gscr, tmp);
151#endif 207#endif
208 out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
152} 209}
153 210
154static void __init 211static void
155mpc52xx_pci_fixup_resources(struct pci_dev *dev) 212mpc52xx_pci_fixup_resources(struct pci_dev *dev)
156{ 213{
157 int i; 214 int i;
diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
index bb2374585a..a4a4b02227 100644
--- a/arch/ppc/syslib/mpc52xx_setup.c
+++ b/arch/ppc/syslib/mpc52xx_setup.c
@@ -84,9 +84,11 @@ mpc52xx_set_bat(void)
84void __init 84void __init
85mpc52xx_map_io(void) 85mpc52xx_map_io(void)
86{ 86{
87 /* Here we only map the MBAR */ 87 /* Here we map the MBAR and the whole upper zone. MBAR is only
88 64k but we can't map only 64k with BATs. Map the whole
89 0xf0000000 range is ok and helps eventual lpb devices placed there */
88 io_block_mapping( 90 io_block_mapping(
89 MPC52xx_MBAR_VIRT, MPC52xx_MBAR, MPC52xx_MBAR_SIZE, _PAGE_IO); 91 MPC52xx_MBAR_VIRT, MPC52xx_MBAR, 0x10000000, _PAGE_IO);
90} 92}
91 93
92 94
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
index f43fbf9a93..f9b95de70e 100644
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ b/arch/ppc/syslib/mpc83xx_devices.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC83xx Device descriptions 4 * MPC83xx Device descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
@@ -28,7 +28,6 @@
28 */ 28 */
29 29
30struct gianfar_mdio_data mpc83xx_mdio_pdata = { 30struct gianfar_mdio_data mpc83xx_mdio_pdata = {
31 .paddr = 0x24520,
32}; 31};
33 32
34static struct gianfar_platform_data mpc83xx_tsec1_pdata = { 33static struct gianfar_platform_data mpc83xx_tsec1_pdata = {
@@ -226,7 +225,14 @@ struct platform_device ppc_sys_platform_devices[] = {
226 .name = "fsl-gianfar_mdio", 225 .name = "fsl-gianfar_mdio",
227 .id = 0, 226 .id = 0,
228 .dev.platform_data = &mpc83xx_mdio_pdata, 227 .dev.platform_data = &mpc83xx_mdio_pdata,
229 .num_resources = 0, 228 .num_resources = 1,
229 .resource = (struct resource[]) {
230 {
231 .start = 0x24520,
232 .end = 0x2453f,
233 .flags = IORESOURCE_MEM,
234 },
235 },
230 }, 236 },
231}; 237};
232 238
diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c
index da74344678..82cf3ab77f 100644
--- a/arch/ppc/syslib/mpc83xx_sys.c
+++ b/arch/ppc/syslib/mpc83xx_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC83xx System descriptions 4 * MPC83xx System descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
@@ -69,9 +69,33 @@ struct ppc_sys_spec ppc_sys_specs[] = {
69 }, 69 },
70 }, 70 },
71 { 71 {
72 .ppc_sys_name = "8343E", 72 .ppc_sys_name = "8347E",
73 .mask = 0xFFFF0000, 73 .mask = 0xFFFF0000,
74 .value = 0x80540000, 74 .value = 0x80540000,
75 .num_devices = 9,
76 .device_list = (enum ppc_sys_devices[])
77 {
78 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
79 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
80 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
81 },
82 },
83 {
84 .ppc_sys_name = "8347",
85 .mask = 0xFFFF0000,
86 .value = 0x80550000,
87 .num_devices = 8,
88 .device_list = (enum ppc_sys_devices[])
89 {
90 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
91 MPC83xx_IIC2, MPC83xx_DUART,
92 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
93 },
94 },
95 {
96 .ppc_sys_name = "8343E",
97 .mask = 0xFFFF0000,
98 .value = 0x80560000,
75 .num_devices = 8, 99 .num_devices = 8,
76 .device_list = (enum ppc_sys_devices[]) 100 .device_list = (enum ppc_sys_devices[])
77 { 101 {
@@ -83,7 +107,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
83 { 107 {
84 .ppc_sys_name = "8343", 108 .ppc_sys_name = "8343",
85 .mask = 0xFFFF0000, 109 .mask = 0xFFFF0000,
86 .value = 0x80550000, 110 .value = 0x80570000,
87 .num_devices = 7, 111 .num_devices = 7,
88 .device_list = (enum ppc_sys_devices[]) 112 .device_list = (enum ppc_sys_devices[])
89 { 113 {
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index 2ede677a0a..00e9b6ff2f 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx Device descriptions 4 * MPC85xx Device descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
@@ -26,7 +26,6 @@
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup 26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */ 27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = { 28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29 .paddr = MPC85xx_MIIM_OFFSET,
30}; 29};
31 30
32static struct gianfar_platform_data mpc85xx_tsec1_pdata = { 31static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
@@ -720,7 +719,14 @@ struct platform_device ppc_sys_platform_devices[] = {
720 .name = "fsl-gianfar_mdio", 719 .name = "fsl-gianfar_mdio",
721 .id = 0, 720 .id = 0,
722 .dev.platform_data = &mpc85xx_mdio_pdata, 721 .dev.platform_data = &mpc85xx_mdio_pdata,
723 .num_resources = 0, 722 .num_resources = 1,
723 .resource = (struct resource[]) {
724 {
725 .start = 0x24520,
726 .end = 0x2453f,
727 .flags = IORESOURCE_MEM,
728 },
729 },
724 }, 730 },
725}; 731};
726 732
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index cb68d8c583..397cfbcce5 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx System descriptions 4 * MPC85xx System descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c
index 2b5f0e7016..92dc98b36b 100644
--- a/arch/ppc/syslib/mpc8xx_devices.c
+++ b/arch/ppc/syslib/mpc8xx_devices.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8xx Device descriptions 4 * MPC8xx Device descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug<vbordug@ru.mvista.com> 8 * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug<vbordug@ru.mvista.com>
9 * 9 *
diff --git a/arch/ppc/syslib/mpc8xx_sys.c b/arch/ppc/syslib/mpc8xx_sys.c
index 3cc27d29e3..d3c6175216 100644
--- a/arch/ppc/syslib/mpc8xx_sys.c
+++ b/arch/ppc/syslib/mpc8xx_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC8xx System descriptions 4 * MPC8xx System descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug <vbordug@ru.mvista.com> 8 * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
9 * 9 *
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index 9ccce438bd..ab34b1d607 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -189,6 +189,8 @@ ocp_device_resume(struct device *dev)
189struct bus_type ocp_bus_type = { 189struct bus_type ocp_bus_type = {
190 .name = "ocp", 190 .name = "ocp",
191 .match = ocp_device_match, 191 .match = ocp_device_match,
192 .probe = ocp_driver_probe,
193 .remove = ocp_driver_remove,
192 .suspend = ocp_device_suspend, 194 .suspend = ocp_device_suspend,
193 .resume = ocp_device_resume, 195 .resume = ocp_device_resume,
194}; 196};
@@ -210,8 +212,6 @@ ocp_register_driver(struct ocp_driver *drv)
210 /* initialize common driver fields */ 212 /* initialize common driver fields */
211 drv->driver.name = drv->name; 213 drv->driver.name = drv->name;
212 drv->driver.bus = &ocp_bus_type; 214 drv->driver.bus = &ocp_bus_type;
213 drv->driver.probe = ocp_device_probe;
214 drv->driver.remove = ocp_device_remove;
215 215
216 /* register with core */ 216 /* register with core */
217 return driver_register(&drv->driver); 217 return driver_register(&drv->driver);
diff --git a/arch/ppc/syslib/ppc4xx_dma.c b/arch/ppc/syslib/ppc4xx_dma.c
index f15e64285f..05ccd598dd 100644
--- a/arch/ppc/syslib/ppc4xx_dma.c
+++ b/arch/ppc/syslib/ppc4xx_dma.c
@@ -30,6 +30,7 @@
30 30
31#include <asm/system.h> 31#include <asm/system.h>
32#include <asm/io.h> 32#include <asm/io.h>
33#include <asm/dma.h>
33#include <asm/ppc4xx_dma.h> 34#include <asm/ppc4xx_dma.h>
34 35
35ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS]; 36ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS];
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index 4da168a6ad..1b5fe9e398 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC83XX common board code 4 * MPC83XX common board code
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h
index c766c1a5f7..a122a7322e 100644
--- a/arch/ppc/syslib/ppc83xx_setup.h
+++ b/arch/ppc/syslib/ppc83xx_setup.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC83XX common board definitions 4 * MPC83XX common board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc85xx_common.c b/arch/ppc/syslib/ppc85xx_common.c
index da841dacdc..19ad537225 100644
--- a/arch/ppc/syslib/ppc85xx_common.c
+++ b/arch/ppc/syslib/ppc85xx_common.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx support routines 4 * MPC85xx support routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc85xx_common.h b/arch/ppc/syslib/ppc85xx_common.h
index 2c8f304441..94edf32151 100644
--- a/arch/ppc/syslib/ppc85xx_common.h
+++ b/arch/ppc/syslib/ppc85xx_common.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85xx support routines 4 * MPC85xx support routines
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index de2f905765..1a47ff4b83 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85XX common board code 4 * MPC85XX common board code
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc85xx_setup.h b/arch/ppc/syslib/ppc85xx_setup.h
index 6e6cfe162f..e340b0545f 100644
--- a/arch/ppc/syslib/ppc85xx_setup.h
+++ b/arch/ppc/syslib/ppc85xx_setup.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * MPC85XX common board definitions 4 * MPC85XX common board definitions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2004 Freescale Semiconductor Inc. 8 * Copyright 2004 Freescale Semiconductor Inc.
9 * 9 *
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index 603f011908..c0b93c4191 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * PPC System library functions 4 * PPC System library functions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * Copyright 2005 MontaVista, Inc. by Vitaly Bordug <vbordug@ru.mvista.com> 9 * Copyright 2005 MontaVista, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c
index e960fe9353..6ff3aab82f 100644
--- a/arch/ppc/syslib/pq2_devices.c
+++ b/arch/ppc/syslib/pq2_devices.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * PQ2 Device descriptions 4 * PQ2 Device descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public License 8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any 9 * version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/ppc/syslib/pq2_sys.c b/arch/ppc/syslib/pq2_sys.c
index 7b6c9ebdb9..36d6e21799 100644
--- a/arch/ppc/syslib/pq2_sys.c
+++ b/arch/ppc/syslib/pq2_sys.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * PQ2 System descriptions 4 * PQ2 System descriptions
5 * 5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public License 8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any 9 * version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/ppc/syslib/prom.c b/arch/ppc/syslib/prom.c
index af4deace49..482f837fd3 100644
--- a/arch/ppc/syslib/prom.c
+++ b/arch/ppc/syslib/prom.c
@@ -70,8 +70,6 @@ int use_of_interrupt_tree;
70struct device_node *dflt_interrupt_controller; 70struct device_node *dflt_interrupt_controller;
71int num_interrupt_controllers; 71int num_interrupt_controllers;
72 72
73int pmac_newworld;
74
75extern unsigned int rtas_entry; /* physical pointer */ 73extern unsigned int rtas_entry; /* physical pointer */
76 74
77extern struct device_node *allnodes; 75extern struct device_node *allnodes;
@@ -123,22 +121,13 @@ finish_device_tree(void)
123 unsigned long mem = (unsigned long) klimit; 121 unsigned long mem = (unsigned long) klimit;
124 struct device_node *np; 122 struct device_node *np;
125 123
126 /* All newworld pmac machines and CHRPs now use the interrupt tree */ 124 /* All CHRPs now use the interrupt tree */
127 for (np = allnodes; np != NULL; np = np->allnext) { 125 for (np = allnodes; np != NULL; np = np->allnext) {
128 if (get_property(np, "interrupt-parent", NULL)) { 126 if (get_property(np, "interrupt-parent", NULL)) {
129 use_of_interrupt_tree = 1; 127 use_of_interrupt_tree = 1;
130 break; 128 break;
131 } 129 }
132 } 130 }
133 if (_machine == _MACH_Pmac && use_of_interrupt_tree)
134 pmac_newworld = 1;
135
136#ifdef CONFIG_BOOTX_TEXT
137 if (boot_infos && pmac_newworld) {
138 prom_print("WARNING ! BootX/miBoot booting is not supported on this machine\n");
139 prom_print(" You should use an Open Firmware bootloader\n");
140 }
141#endif /* CONFIG_BOOTX_TEXT */
142 131
143 if (use_of_interrupt_tree) { 132 if (use_of_interrupt_tree) {
144 /* 133 /*
@@ -434,16 +423,10 @@ finish_node_interrupts(struct device_node *np, unsigned long mem_start)
434 * those machines, we want to offset interrupts from the 423 * those machines, we want to offset interrupts from the
435 * second openpic by 128 -- BenH 424 * second openpic by 128 -- BenH
436 */ 425 */
437 if (_machine != _MACH_Pmac && num_interrupt_controllers > 1 426 if (num_interrupt_controllers > 1
438 && ic != NULL 427 && ic != NULL
439 && get_property(ic, "interrupt-parent", NULL) == NULL) 428 && get_property(ic, "interrupt-parent", NULL) == NULL)
440 offset = 16; 429 offset = 16;
441 else if (_machine == _MACH_Pmac && num_interrupt_controllers > 1
442 && ic != NULL && ic->parent != NULL) {
443 char *name = get_property(ic->parent, "name", NULL);
444 if (name && !strcmp(name, "u3"))
445 offset = 128;
446 }
447 430
448 np->intrs[i].line = irq[0] + offset; 431 np->intrs[i].line = irq[0] + offset;
449 if (n > 1) 432 if (n > 1)
diff --git a/arch/ppc/xmon/start.c b/arch/ppc/xmon/start.c
index 98612d4203..4344cbe9b5 100644
--- a/arch/ppc/xmon/start.c
+++ b/arch/ppc/xmon/start.c
@@ -18,7 +18,6 @@
18#include <asm/bootx.h> 18#include <asm/bootx.h>
19#include <asm/machdep.h> 19#include <asm/machdep.h>
20#include <asm/errno.h> 20#include <asm/errno.h>
21#include <asm/pmac_feature.h>
22#include <asm/processor.h> 21#include <asm/processor.h>
23#include <asm/delay.h> 22#include <asm/delay.h>
24#include <asm/btext.h> 23#include <asm/btext.h>
@@ -27,11 +26,9 @@ static volatile unsigned char *sccc, *sccd;
27unsigned int TXRDY, RXRDY, DLAB; 26unsigned int TXRDY, RXRDY, DLAB;
28static int xmon_expect(const char *str, unsigned int timeout); 27static int xmon_expect(const char *str, unsigned int timeout);
29 28
30static int use_serial;
31static int use_screen; 29static int use_screen;
32static int via_modem; 30static int via_modem;
33static int xmon_use_sccb; 31static int xmon_use_sccb;
34static struct device_node *channel_node;
35 32
36#define TB_SPEED 25000000 33#define TB_SPEED 25000000
37 34
@@ -112,94 +109,22 @@ xmon_map_scc(void)
112#ifdef CONFIG_PPC_MULTIPLATFORM 109#ifdef CONFIG_PPC_MULTIPLATFORM
113 volatile unsigned char *base; 110 volatile unsigned char *base;
114 111
115 if (_machine == _MACH_Pmac) { 112#ifdef CONFIG_PPC_CHRP
116 struct device_node *np; 113 base = (volatile unsigned char *) isa_io_base;
117 unsigned long addr; 114 if (_machine == _MACH_chrp)
118#ifdef CONFIG_BOOTX_TEXT 115 base = (volatile unsigned char *)
119 if (!use_screen && !use_serial 116 ioremap(chrp_find_phys_io_base(), 0x1000);
120 && !machine_is_compatible("iMac")) { 117
121 /* see if there is a keyboard in the device tree 118 sccc = base + 0x3fd;
122 with a parent of type "adb" */ 119 sccd = base + 0x3f8;
123 for (np = find_devices("keyboard"); np; np = np->next) 120 if (xmon_use_sccb) {
124 if (np->parent && np->parent->type 121 sccc -= 0x100;
125 && strcmp(np->parent->type, "adb") == 0) 122 sccd -= 0x100;
126 break;
127
128 /* needs to be hacked if xmon_printk is to be used
129 from within find_via_pmu() */
130#ifdef CONFIG_ADB_PMU
131 if (np != NULL && boot_text_mapped && find_via_pmu())
132 use_screen = 1;
133#endif
134#ifdef CONFIG_ADB_CUDA
135 if (np != NULL && boot_text_mapped && find_via_cuda())
136 use_screen = 1;
137#endif
138 }
139 if (!use_screen && (np = find_devices("escc")) != NULL) {
140 /*
141 * look for the device node for the serial port
142 * we're using and see if it says it has a modem
143 */
144 char *name = xmon_use_sccb? "ch-b": "ch-a";
145 char *slots;
146 int l;
147
148 np = np->child;
149 while (np != NULL && strcmp(np->name, name) != 0)
150 np = np->sibling;
151 if (np != NULL) {
152 /* XXX should parse this properly */
153 channel_node = np;
154 slots = get_property(np, "slot-names", &l);
155 if (slots != NULL && l >= 10
156 && strcmp(slots+4, "Modem") == 0)
157 via_modem = 1;
158 }
159 }
160 btext_drawstring("xmon uses ");
161 if (use_screen)
162 btext_drawstring("screen and keyboard\n");
163 else {
164 if (via_modem)
165 btext_drawstring("modem on ");
166 btext_drawstring(xmon_use_sccb? "printer": "modem");
167 btext_drawstring(" port\n");
168 }
169
170#endif /* CONFIG_BOOTX_TEXT */
171
172#ifdef CHRP_ESCC
173 addr = 0xc1013020;
174#else
175 addr = 0xf3013020;
176#endif
177 TXRDY = 4;
178 RXRDY = 1;
179
180 np = find_devices("mac-io");
181 if (np && np->n_addrs)
182 addr = np->addrs[0].address + 0x13020;
183 base = (volatile unsigned char *) ioremap(addr & PAGE_MASK, PAGE_SIZE);
184 sccc = base + (addr & ~PAGE_MASK);
185 sccd = sccc + 0x10;
186
187 } else {
188 base = (volatile unsigned char *) isa_io_base;
189 if (_machine == _MACH_chrp)
190 base = (volatile unsigned char *)
191 ioremap(chrp_find_phys_io_base(), 0x1000);
192
193 sccc = base + 0x3fd;
194 sccd = base + 0x3f8;
195 if (xmon_use_sccb) {
196 sccc -= 0x100;
197 sccd -= 0x100;
198 }
199 TXRDY = 0x20;
200 RXRDY = 1;
201 DLAB = 0x80;
202 } 123 }
124 TXRDY = 0x20;
125 RXRDY = 1;
126 DLAB = 0x80;
127#endif /* CONFIG_PPC_CHRP */
203#elif defined(CONFIG_GEMINI) 128#elif defined(CONFIG_GEMINI)
204 /* should already be mapped by the kernel boot */ 129 /* should already be mapped by the kernel boot */
205 sccc = (volatile unsigned char *) 0xffeffb0d; 130 sccc = (volatile unsigned char *) 0xffeffb0d;
@@ -382,16 +307,6 @@ xmon_read_poll(void)
382 return *sccd; 307 return *sccd;
383} 308}
384 309
385static unsigned char scc_inittab[] = {
386 13, 0, /* set baud rate divisor */
387 12, 1,
388 14, 1, /* baud rate gen enable, src=rtxc */
389 11, 0x50, /* clocks = br gen */
390 5, 0xea, /* tx 8 bits, assert DTR & RTS */
391 4, 0x46, /* x16 clock, 1 stop */
392 3, 0xc1, /* rx enable, 8 bits */
393};
394
395void 310void
396xmon_init_scc(void) 311xmon_init_scc(void)
397{ 312{
@@ -404,43 +319,6 @@ xmon_init_scc(void)
404 sccd[3] = 3; eieio(); /* LCR = 8N1 */ 319 sccd[3] = 3; eieio(); /* LCR = 8N1 */
405 sccd[1] = 0; eieio(); /* IER = 0 */ 320 sccd[1] = 0; eieio(); /* IER = 0 */
406 } 321 }
407 else if ( _machine == _MACH_Pmac )
408 {
409 int i, x;
410
411 if (channel_node != 0)
412 pmac_call_feature(
413 PMAC_FTR_SCC_ENABLE,
414 channel_node,
415 PMAC_SCC_ASYNC | PMAC_SCC_FLAG_XMON, 1);
416 printk(KERN_INFO "Serial port locked ON by debugger !\n");
417 if (via_modem && channel_node != 0) {
418 unsigned int t0;
419
420 pmac_call_feature(
421 PMAC_FTR_MODEM_ENABLE,
422 channel_node, 0, 1);
423 printk(KERN_INFO "Modem powered up by debugger !\n");
424 t0 = readtb();
425 while (readtb() - t0 < 3*TB_SPEED)
426 eieio();
427 }
428 /* use the B channel if requested */
429 if (xmon_use_sccb) {
430 sccc = (volatile unsigned char *)
431 ((unsigned long)sccc & ~0x20);
432 sccd = sccc + 0x10;
433 }
434 for (i = 20000; i != 0; --i) {
435 x = *sccc; eieio();
436 }
437 *sccc = 9; eieio(); /* reset A or B side */
438 *sccc = ((unsigned long)sccc & 0x20)? 0x80: 0x40; eieio();
439 for (i = 0; i < sizeof(scc_inittab); ++i) {
440 *sccc = scc_inittab[i];
441 eieio();
442 }
443 }
444 scc_initialized = 1; 322 scc_initialized = 1;
445 if (via_modem) { 323 if (via_modem) {
446 for (;;) { 324 for (;;) {
@@ -629,19 +507,9 @@ xmon_fgets(char *str, int nb, void *f)
629void 507void
630xmon_enter(void) 508xmon_enter(void)
631{ 509{
632#ifdef CONFIG_ADB_PMU
633 if (_machine == _MACH_Pmac) {
634 pmu_suspend();
635 }
636#endif
637} 510}
638 511
639void 512void
640xmon_leave(void) 513xmon_leave(void)
641{ 514{
642#ifdef CONFIG_ADB_PMU
643 if (_machine == _MACH_Pmac) {
644 pmu_resume();
645 }
646#endif
647} 515}
diff --git a/arch/ppc/xmon/xmon.c b/arch/ppc/xmon/xmon.c
index 2b483b4f16..bdaf6597b4 100644
--- a/arch/ppc/xmon/xmon.c
+++ b/arch/ppc/xmon/xmon.c
@@ -16,9 +16,6 @@
16#include <asm/bootx.h> 16#include <asm/bootx.h>
17#include <asm/machdep.h> 17#include <asm/machdep.h>
18#include <asm/xmon.h> 18#include <asm/xmon.h>
19#ifdef CONFIG_PMAC_BACKLIGHT
20#include <asm/backlight.h>
21#endif
22#include "nonstdio.h" 19#include "nonstdio.h"
23#include "privinst.h" 20#include "privinst.h"
24 21
@@ -99,7 +96,7 @@ static void remove_bpts(void);
99static void insert_bpts(void); 96static void insert_bpts(void);
100static struct bpt *at_breakpoint(unsigned pc); 97static struct bpt *at_breakpoint(unsigned pc);
101static void bpt_cmds(void); 98static void bpt_cmds(void);
102static void cacheflush(void); 99void cacheflush(void);
103#ifdef CONFIG_SMP 100#ifdef CONFIG_SMP
104static void cpu_cmd(void); 101static void cpu_cmd(void);
105#endif /* CONFIG_SMP */ 102#endif /* CONFIG_SMP */
@@ -260,16 +257,6 @@ int xmon(struct pt_regs *excp)
260 */ 257 */
261#endif /* CONFIG_SMP */ 258#endif /* CONFIG_SMP */
262 remove_bpts(); 259 remove_bpts();
263#ifdef CONFIG_PMAC_BACKLIGHT
264 if( setjmp(bus_error_jmp) == 0 ) {
265 debugger_fault_handler = handle_fault;
266 sync();
267 set_backlight_enable(1);
268 set_backlight_level(BACKLIGHT_MAX);
269 sync();
270 }
271 debugger_fault_handler = NULL;
272#endif /* CONFIG_PMAC_BACKLIGHT */
273 cmd = cmds(excp); 260 cmd = cmds(excp);
274 if (cmd == 's') { 261 if (cmd == 's') {
275 xmon_trace[smp_processor_id()] = SSTEP; 262 xmon_trace[smp_processor_id()] = SSTEP;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 19:20:43 -0400