11 files changed, 680 insertions, 2 deletions

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 99c0d32371..0f571d3d2f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)        :=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)       :=-mtune=strongarm1100
 tune-$(CONFIG_CPU_XSCALE)       :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_XSC3)         :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
 tune-$(CONFIG_CPU_V6)           :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
 
 ifeq ($(CONFIG_AEABI),y)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e680c5fd93..c55b739e10 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -239,6 +239,17 @@ config CPU_XSCALE
         select CPU_CACHE_VIVT
         select CPU_TLB_V4WBI
 
+# XScale Core Version 3
+config CPU_XSC3
+        bool
+        depends on ARCH_IXP23XX
+        default y
+        select CPU_32v5
+        select CPU_ABRT_EV5T
+        select CPU_CACHE_VIVT
+        select CPU_TLB_V4WBI
+        select IO_36
+
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor"
@@ -361,11 +372,17 @@ config CPU_TLB_V4WBI
 config CPU_TLB_V6
         bool
 
+#
+# CPU supports 36-bit I/O
+#
+config IO_36
+        bool
+
 comment "Processor Features"
 
 config ARM_THUMB
         bool "Support Thumb user binaries"
-        depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
+        depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
         default y
         help
           Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ffe73ba2bf..07a5385057 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_COPY_V4WB)	+= copypage-v4wb.o
 obj-$(CONFIG_CPU_COPY_V6)       += copypage-v6.o mmu.o
 obj-$(CONFIG_CPU_SA1100)        += copypage-v4mc.o
 obj-$(CONFIG_CPU_XSCALE)        += copypage-xscale.o
+obj-$(CONFIG_CPU_XSC3)          += copypage-xsc3.o
 
 obj-$(CONFIG_CPU_TLB_V3)        += tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
@@ -51,4 +52,5 @@ obj-$(CONFIG_CPU_ARM1026)	+= proc-arm1026.o
 obj-$(CONFIG_CPU_SA110)         += proc-sa110.o
 obj-$(CONFIG_CPU_SA1100)        += proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)        += proc-xscale.o
+obj-$(CONFIG_CPU_XSC3)          += proc-xsc3.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
diff --git a/arch/arm/mm/copypage-xsc3.S b/arch/arm/mm/copypage-xsc3.S
new file mode 100644
index 0000000000..9a2cb4332b
--- /dev/null
+++ b/arch/arm/mm/copypage-xsc3.S
@@ -0,0 +1,97 @@
+/*
+ *  linux/arch/arm/lib/copypage-xsc3.S
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adapted for 3rd gen XScale core, no more mini-dcache
+ * Author: Matt Gilbert (matthew.m.gilbert@intel.com)
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * General note:
+ *  We don't really want write-allocate cache behaviour for these functions
+ *  since that will just eat through 8K of the cache.
+ */
+
+        .text
+        .align  5
+/*
+ * XSC3 optimised copy_user_page
+ *  r0 = destination
+ *  r1 = source
+ *  r2 = virtual user address of ultimate destination page
+ *
+ * The source page may have some clean entries in the cache already, but we
+ * can safely ignore them - break_cow() will flush them out of the cache
+ * if we eventually end up using our copied page.
+ *
+ */
+ENTRY(xsc3_mc_copy_user_page)
+        stmfd   sp!, {r4, r5, lr}
+        mov     lr, #PAGE_SZ/64-1
+
+        pld     [r1, #0]
+        pld     [r1, #32]
+1:      pld     [r1, #64]
+        pld     [r1, #96]
+
+2:      ldrd    r2, [r1], #8
+        mov     ip, r0
+        ldrd    r4, [r1], #8
+        mcr     p15, 0, ip, c7, c6, 1           @ invalidate
+        strd    r2, [r0], #8
+        ldrd    r2, [r1], #8
+        strd    r4, [r0], #8
+        ldrd    r4, [r1], #8
+        strd    r2, [r0], #8
+        strd    r4, [r0], #8
+        ldrd    r2, [r1], #8
+        mov     ip, r0
+        ldrd    r4, [r1], #8
+        mcr     p15, 0, ip, c7, c6, 1           @ invalidate
+        strd    r2, [r0], #8
+        ldrd    r2, [r1], #8
+        subs    lr, lr, #1
+        strd    r4, [r0], #8
+        ldrd    r4, [r1], #8
+        strd    r2, [r0], #8
+        strd    r4, [r0], #8
+        bgt     1b
+        beq     2b
+
+        ldmfd   sp!, {r4, r5, pc}
+
+        .align  5
+/*
+ * XScale optimised clear_user_page
+ *  r0 = destination
+ *  r1 = virtual user address of ultimate destination page
+ */
+ENTRY(xsc3_mc_clear_user_page)
+        mov     r1, #PAGE_SZ/32
+        mov     r2, #0
+        mov     r3, #0
+1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate line
+        strd    r2, [r0], #8
+        strd    r2, [r0], #8
+        strd    r2, [r0], #8
+        strd    r2, [r0], #8
+        subs    r1, r1, #1
+        bne     1b
+        mov     pc, lr
+
+        __INITDATA
+
+        .type   xsc3_mc_user_fns, #object
+ENTRY(xsc3_mc_user_fns)
+        .long   xsc3_mc_clear_user_page
+        .long   xsc3_mc_copy_user_page
+        .size   xsc3_mc_user_fns, . - xsc3_mc_user_fns
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index ef8d30a185..5e5d05bcad 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -557,7 +557,8 @@ void __init create_mapping(struct map_desc *md)
          *      supersections are only allocated for domain 0 regardless
          *      of the actual domain assignments in use.
          */
-        if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) {
+        if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
+                && domain == 0) {
                 /*
                  * Align to supersection boundary if !high pages.
                  * High pages have already been checked for proper
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
new file mode 100644
index 0000000000..f90513e9af
--- /dev/null
+++ b/arch/arm/mm/proc-xsc3.S
@@ -0,0 +1,498 @@
+/*
+ * linux/arch/arm/mm/proc-xsc3.S
+ *
+ * Original Author: Matthew Gilbert
+ * Current Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (C) Intel Corp.
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * MMU functions for the Intel XScale3 Core (XSC3).  The XSC3 core is an
+ * extension to Intel's original XScale core that adds the following
+ * features:
+ *
+ * - ARMv6 Supersections
+ * - Low Locality Reference pages (replaces mini-cache)