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/*
 * Ultra Wide Band
 * UWB Standard definitions
 *
 * Copyright (C) 2005-2006 Intel Corporation
 * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 *
 *
 * All these definitions are based on the ECMA-368 standard.
 *
 * Note all definitions are Little Endian in the wire, and we will
 * convert them to host order before operating on the bitfields (that
 * yes, we use extensively).
 */

#ifndef __LINUX__UWB_SPEC_H__
#define __LINUX__UWB_SPEC_H__

#include <linux/types.h>
#include <linux/bitmap.h>

#define i1480_FW 0x00000303
/* #define i1480_FW 0x00000302 */

/**
 * Number of Medium Access Slots in a superframe.
 *
 * UWB divides time in SuperFrames, each one divided in 256 pieces, or
 * Medium Access Slots. See MBOA MAC[5.4.5] for details. The MAS is the
 * basic bandwidth allocation unit in UWB.
 */
enum { UWB_NUM_MAS = 256 };

/**
 * Number of Zones in superframe.
 *
 * UWB divides the superframe into zones with numbering starting from BPST.
 * See MBOA MAC[16.8.6]
 */
enum { UWB_NUM_ZONES = 16 };

/*
 * Number of MAS in a zone.
 */
#define UWB_MAS_PER_ZONE (UWB_NUM_MAS / UWB_NUM_ZONES)

/*
 * Number of MAS required before a row can be considered available.
 */
#define UWB_USABLE_MAS_PER_ROW (UWB_NUM_ZONES - 1)

/*
 * Number of streams per DRP reservation between a pair of devices.
 *
 * [ECMA-368] section 16.8.6.
 */
enum { UWB_NUM_STREAMS = 8 };

/*
 * mMasLength
 *
 * The length of a MAS in microseconds.
 *
 * [ECMA-368] section 17.16.
 */
enum { UWB_MAS_LENGTH_US = 256 };

/*
 * mBeaconSlotLength
 *
 * The length of the beacon slot in microseconds.
 *
 * [ECMA-368] section 17.16
 */
enum { UWB_BEACON_SLOT_LENGTH_US = 85 };

/*
 * mMaxLostBeacons
 *
 * The number beacons missing in consecutive superframes before a
 * device can be considered as unreachable.
 *
 * [ECMA-368] section 17.16
 */
enum { UWB_MAX_LOST_BEACONS = 3 };

/*
 * mDRPBackOffWinMin
 *
 * The minimum number of superframes to wait before trying to reserve
 * extra MAS.
 *
 * [ECMA-368] section 17.16
 */
enum { UWB_DRP_BACKOFF_WIN_MIN = 2 };

/*
 * mDRPBackOffWinMax
 *
 * The maximum number of superframes to wait before trying to reserve
 * extra MAS.
 *
 * [ECMA-368] section 17.16
 */
enum { UWB_DRP_BACKOFF_WIN_MAX = 16 };

/*
 * Length of a superframe in microseconds.
 */
#define UWB_SUPERFRAME_LENGTH_US (UWB_MAS_LENGTH_US * UWB_NUM_MAS)

/**
 * UWB MAC address
 *
 * It is *imperative* that this struct is exactly 6 packed bytes (as
 * it is also used to define headers sent down and up the wire/radio).
 */
struct uwb_mac_addr {
	u8 data[6];
} __attribute__((packed));


/**
 * UWB device address
 *
 * It is *imperative* that this struct is exactly 6 packed bytes (as
 * it is also used to define headers sent down and up the wire/radio).
 */
struct uwb_dev_addr {
	u8 data[2];
} __attribute__((packed));


/**
 * Types of UWB addresses
 *
 * Order matters (by size).
 */
enum uwb_addr_type {
	UWB_ADDR_DEV = 0,
	UWB_ADDR_MAC = 1,
};


/** Size of a char buffer for printing a MAC/device address */
enum { UWB_ADDR_STRSIZE = 32 };


/** UWB WiMedia protocol IDs. */
enum uwb_prid {
	UWB_PRID_WLP_RESERVED   = 0x0000,
	UWB_PRID_WLP		= 0x0001,
	UWB_PRID_WUSB_BOT	= 0x0010,
	UWB_PRID_WUSB		= 0x0010,
	UWB_PRID_WUSB_TOP	= 0x001F,
};


/** PHY Rate (MBOA MAC[7.8.12, Table 61]) */
enum uwb_phy_rate {
	UWB_PHY_RATE_53 = 0,
	UWB_PHY_RATE_80,
	UWB_PHY_RATE_106,
	UWB_PHY_RATE_160,
	UWB_PHY_RATE_200,
	UWB_PHY_RATE_320,
	UWB_PHY_RATE_400,
	UWB_PHY_RATE_480,
	UWB_PHY_RATE_INVALID
};


/**
 * Different ways to scan (MBOA MAC[6.2.2, Table 8], WUSB[Table 8-78])
 */
enum uwb_scan_type {
	UWB_SCAN_ONLY = 0,
	UWB_SCAN_OUTSIDE_BP,
	UWB_SCAN_WHILE_INACTIVE,
	UWB_SCAN_DISABLED,
	UWB_SCAN_ONLY_STARTTIME,
	UWB_SCAN_TOP
};


/** ACK Policy types (MBOA MAC[7.2.1.3]) */
enum uwb_ack_pol {
	UWB_ACK_NO = 0,
	UWB_ACK_INM = 1,
	UWB_ACK_B = 2,
	UWB_ACK_B_REQ = 3,
};


/** DRP reservation types ([ECMA-368 table 106) */
enum uwb_drp_type {
	UWB_DRP_TYPE_ALIEN_BP = 0,
	UWB_DRP_TYPE_HARD,
	UWB_DRP_TYPE_SOFT,
	UWB_DRP_TYPE_PRIVATE,
	UWB_DRP_TYPE_PCA,
};


/** DRP Reason Codes ([ECMA-368] table 107) */
enum uwb_drp_reason {
	UWB_DRP_REASON_ACCEPTED = 0,
	UWB_DRP_REASON_CONFLICT,
	UWB_DRP_REASON_PENDING,
	UWB_DRP_REASON_DENIED,
	UWB_DRP_REASON_MODIFIED,
};

/** Relinquish Request Reason Codes ([ECMA-368] table 113) */
enum uwb_relinquish_req_reason {
	UWB_RELINQUISH_REQ_REASON_NON_SPECIFIC = 0,
	UWB_RELINQUISH_REQ_REASON_OVER_ALLOCATION,
};

/**
 *  DRP Notification Reason Codes (WHCI 0.95 [3.1.4.9])
 */
enum uwb_drp_notif_reason {
	UWB_DRP_NOTIF_DRP_IE_RCVD = 0,
	UWB_DRP_NOTIF_CONFLICT,
	UWB_DRP_NOTIF_TERMINATE,
};


/** Allocation of MAS slots in a DRP request MBOA MAC[7.8.7] */
struct uwb_drp_alloc {
	__le16 zone_bm;
	__le16 mas_bm;
} __attribute__((packed));


/** General MAC Header format (ECMA-368[16.2]) */
struct uwb_mac_frame_hdr {
	__le16 Frame_Control;
	struct uwb_dev_addr DestAddr;
	struct uwb_dev_addr SrcAddr;
	__le16 Sequence_Control;
	__le16 Access_Information;
} __attribute__((packed));


/**
 * uwb_beacon_frame - a beacon frame including MAC headers
 *
 * [ECMA] section 16.3.
 */
struct uwb_beacon_frame {
	struct uwb_mac_frame_hdr hdr;
	struct uwb_mac_addr Device_Identifier;	/* may be a NULL EUI-48 */
	u8 Beacon_Slot_Number;
	u8 Device_Control;
	u8 IEData[];
} __attribute__((packed));


/** Information Element codes (MBOA MAC[T54]) */
enum uwb_ie {
	UWB_PCA_AVAILABILITY = 2,
	UWB_IE_DRP_AVAILABILITY = 8,
	UWB_IE_DRP = 9,
	UWB_BP_SWITCH_IE = 11,
	UWB_MAC_CAPABILITIES_IE = 12,
	UWB_PHY_CAPABILITIES_IE = 13,
	UWB_APP_SPEC_PROBE_IE = 15,
	UWB_IDENTIFICATION_IE = 19,
	UWB_MASTER_KEY_ID_IE = 20,
	UWB_RELINQUISH_REQUEST_IE = 21,
	UWB_IE_WLP = 250, /* WiMedia Logical Link Control Protocol WLP 0.99 */
	UWB_APP_SPEC_IE = 255,
};


/**
 * Header common to all Information Elements (IEs)
 */
struct uwb_ie_hdr {
	u8 element_id;	/* enum uwb_ie */
	u8 length;
} __attribute__((packed));


/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.6]) */
struct uwb_ie_drp {
	struct uwb_ie_hdr	hdr;
	__le16                  drp_control;
	struct uwb_dev_addr	dev_addr;
	struct uwb_drp_alloc	allocs[];
} __attribute__((packed));

static inline int uwb_ie_drp_type(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 0) & 0x7;
}

static inline int uwb_ie_drp_stream_index(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 3) & 0x7;
}

static inline int uwb_ie_drp_reason_code(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 6) & 0x7;
}

static inline int uwb_ie_drp_status(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 9) & 0x1;
}

static inline int uwb_ie_drp_owner(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 10) & 0x1;
}

static inline int uwb_ie_drp_tiebreaker(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 11) & 0x1;
}

static inline int uwb_ie_drp_unsafe(struct uwb_ie_drp *ie)
{
	return (le16_to_cpu(ie->drp_control) >> 12) & 0x1;
}

static inline void uwb_ie_drp_set_type(struct uwb_ie_drp *ie, enum uwb_drp_type type)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x7 << 0)) | (type << 0);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_stream_index(struct uwb_ie_drp *ie, int stream_index)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x7 << 3)) | (stream_index << 3);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_reason_code(struct uwb_ie_drp *ie,
				       enum uwb_drp_reason reason_code)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (ie->drp_control & ~(0x7 << 6)) | (reason_code << 6);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_status(struct uwb_ie_drp *ie, int status)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x1 << 9)) | (status << 9);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_owner(struct uwb_ie_drp *ie, int owner)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x1 << 10)) | (owner << 10);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_tiebreaker(struct uwb_ie_drp *ie, int tiebreaker)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x1 << 11)) | (tiebreaker << 11);
	ie->drp_control = cpu_to_le16(drp_control);
}

static inline void uwb_ie_drp_set_unsafe(struct uwb_ie_drp *ie, int unsafe)
{
	u16 drp_control = le16_to_cpu(ie->drp_control);
	drp_control = (drp_control & ~(0x1 << 12)) | (unsafe << 12);
	ie->drp_control = cpu_to_le16(drp_control);
}

/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.7]) */
struct uwb_ie_drp_avail {
	struct uwb_ie_hdr	hdr;
	DECLARE_BITMAP(bmp, UWB_NUM_MAS);
} __attribute__((packed));

/* Relinqish Request IE ([ECMA-368] section 16.8.19). */
struct uwb_relinquish_request_ie {
        struct uwb_ie_hdr       hdr;
        __le16                  relinquish_req_control;
        struct uwb_dev_addr     dev_addr;
        struct uwb_drp_alloc    allocs[];
} __attribute__((packed));

static inline int uwb_ie_relinquish_req_reason_code(struct uwb_relinquish_request_ie *ie)
{
	return (le16_to_cpu(ie->relinquish_req_control) >> 0) & 0xf;
}

static inline void uwb_ie_relinquish_req_set_reason_code(struct uwb_relinquish_request_ie *ie,
							 int reason_code)
{
	u16 ctrl = le16_to_cpu(ie->relinquish_req_control);
	ctrl = (ctrl & ~(0xf << 0)) | (reason_code << 0);
	ie->relinquish_req_control = cpu_to_le16(ctrl);
}

/**
 * The Vendor ID is set to an OUI that indicates the vendor of the device.
 * ECMA-368 [16.8.10]
 */
struct uwb_vendor_id {
	u8 data[3];
} __attribute__((packed));

/**
 * The device type ID
 * FIXME: clarify what this means
 * ECMA-368 [16.8.10]
 */
struct uwb_device_type_id {
	u8 data[3];
} __attribute__((packed));


/**
 * UWB device information types
 * ECMA-368 [16.8.10]
 */
enum uwb_dev_info_type {
	UWB_DEV_INFO_VENDOR_ID = 0,
	UWB_DEV_INFO_VENDOR_TYPE,
	UWB_DEV_INFO_NAME,
};

/**
 * UWB device information found in Identification IE
 * ECMA-368 [16.8.10]
 */
struct uwb_dev_info {
	u8 type;	/* enum uwb_dev_info_type */
	u8 length;
	u8 data[];
} __attribute__((packed));

/**
 * UWB Identification IE
 * ECMA-368 [16.8.10]
 */
struct uwb_identification_ie {
	struct uwb_ie_hdr hdr;
	struct uwb_dev_info info[];
} __attribute__((packed));

/*
 * UWB Radio Controller
 *
 * These definitions are common to the Radio Control layers as
 * exported by the WUSB1.0 HWA and WHCI interfaces.
 */

/** Radio Control Command Block (WUSB1.0[Table 8-65] and WHCI 0.95) */
struct uwb_rccb {
	u8 bCommandType;		/* enum hwa_cet */
	__le16 wCommand;		/* Command code */
	u8 bCommandContext;		/* Context ID */
} __attribute__((packed));


/** Radio Control Event Block (WUSB[table 8-66], WHCI 0.95) */
struct uwb_rceb {
	u8 bEventType;			/* enum hwa_cet */
	__le16 wEvent;			/* Event code */
	u8 bEventContext;		/* Context ID */
} __attribute__((packed));


enum {
	UWB_RC_CET_GENERAL = 0,		/* General Command/Event type */
	UWB_RC_CET_EX_TYPE_1 = 1,	/* Extended Type 1 Command/Event type */
};

/* Commands to the radio controller */
enum uwb_rc_cmd {
	UWB_RC_CMD_CHANNEL_CHANGE = 16,
	UWB_RC_CMD_DEV_ADDR_MGMT = 17,	/* Device Address Management */
	UWB_RC_CMD_GET_IE = 18,		/* GET Information Elements */
	UWB_RC_CMD_RESET = 19,
	UWB_RC_CMD_SCAN = 20,		/* Scan management  */
	UWB_RC_CMD_SET_BEACON_FILTER = 21,
	UWB_RC_CMD_SET_DRP_IE = 22,	/* Dynamic Reservation Protocol IEs */
	UWB_RC_CMD_SET_IE = 23,		/* Information Element management */
	UWB_RC_CMD_SET_NOTIFICATION_FILTER = 24,
	UWB_RC_CMD_SET_TX_POWER = 25,
	UWB_RC_CMD_SLEEP = 26,
	UWB_RC_CMD_START_BEACON = 27,
	UWB_RC_CMD_STOP_BEACON = 28,
	UWB_RC_CMD_BP_MERGE = 29,
	UWB_RC_CMD_SEND_COMMAND_FRAME = 30,
	UWB_RC_CMD_SET_ASIE_NOTIF = 31,
};

/* Notifications from the radio controller */
enum uwb_rc_evt {
	UWB_RC_EVT_IE_RCV = 0,
	UWB_RC_EVT_BEACON = 1,
	UWB_RC_EVT_BEACON_SIZE = 2,
	UWB_RC_EVT_BPOIE_CHANGE = 3,
	UWB_RC_EVT_BP_SLOT_CHANGE = 4,
	UWB_RC_EVT_BP_SWITCH_IE_RCV = 5,
	UWB_RC_EVT_DEV_ADDR_CONFLICT = 6,
	UWB_RC_EVT_DRP_AVAIL = 7,
	UWB_RC_EVT_DRP = 8,
	UWB_RC_EVT_BP_SWITCH_STATUS = 9,
	UWB_RC_EVT_CMD_FRAME_RCV = 10,
	UWB_RC_EVT_CHANNEL_CHANGE_IE_RCV = 11,
	/* Events (command responses) use the same code as the command */
	UWB_RC_EVT_UNKNOWN_CMD_RCV = 65535,
};

enum uwb_rc_extended_type_1_cmd {
	UWB_RC_SET_DAA_ENERGY_MASK = 32,
	UWB_RC_SET_NOTIFICATION_FILTER_EX = 33,
};

enum uwb_rc_extended_type_1_evt {
	UWB_RC_DAA_ENERGY_DETECTED = 0,
};

/* Radio Control Result Code. [WHCI] table 3-3. */
enum {
	UWB_RC_RES_SUCCESS = 0,
	UWB_RC_RES_FAIL,
	UWB_RC_RES_FAIL_HARDWARE,
	UWB_RC_RES_FAIL_NO_SLOTS,
	UWB_RC_RES_FAIL_BEACON_TOO_LARGE,
	UWB_RC_RES_FAIL_INVALID_PARAMETER,
	UWB_RC_RES_FAIL_UNSUPPORTED_PWR_LEVEL,
	UWB_RC_RES_FAIL_INVALID_IE_DATA,
	UWB_RC_RES_FAIL_BEACON_SIZE_EXCEEDED,
	UWB_RC_RES_FAIL_CANCELLED,
	UWB_RC_RES_FAIL_INVALID_STATE,
	UWB_RC_RES_FAIL_INVALID_SIZE,
	UWB_RC_RES_FAIL_ACK_NOT_RECEIVED,
	UWB_RC_RES_FAIL_NO_MORE_ASIE_NOTIF,
	UWB_RC_RES_FAIL_TIME_OUT = 255,
};

/* Confirm event. [WHCI] section 3.1.3.1 etc. */
struct uwb_rc_evt_confirm {
	struct uwb_rceb rceb;
	u8 bResultCode;
} __attribute__((packed));

/* Device Address Management event. [WHCI] section 3.1.3.2. */
struct uwb_rc_evt_dev_addr_mgmt {
	struct uwb_rceb rceb;
	u8 baAddr[6];
	u8 bResultCode;
} __attribute__((packed));


/* Get IE Event. [WHCI] section 3.1.3.3. */
struct uwb_rc_evt_get_ie {
	struct uwb_rceb rceb;
	__le16 wIELength;
	u8 IEData[];
} __attribute__((packed));

/* Set DRP IE Event. [WHCI] section 3.1.3.7. */
struct uwb_rc_evt_set_drp_ie {
	struct uwb_rceb rceb;
	__le16 wRemainingSpace;
	u8 bResultCode;
} __attribute__((packed));

/* Set IE Event. [WHCI] section 3.1.3.8. */
struct uwb_rc_evt_set_ie {
	struct uwb_rceb rceb;
	__le16 RemainingSpace;
	u8 bResultCode;
} __attribute__((packed));

/* Scan command. [WHCI] 3.1.3.5. */
struct uwb_rc_cmd_scan {
	struct uwb_rccb rccb;
	u8 bChannelNumber;
	u8 bScanState;
	__le16 wStartTime;
} __attribute__((packed));

/* Set DRP IE command. [WHCI] section 3.1.3.7. */
struct uwb_rc_cmd_set_drp_ie {
	struct uwb_rccb rccb;
	__le16 wIELength;
	struct uwb_ie_drp IEData[];
} __attribute__((packed));

/* Set IE command. [WHCI] section 3.1.3.8. */
struct uwb_rc_cmd_set_ie {
	struct uwb_rccb rccb;
	__le16 wIELength;
	u8 IEData[];
} __attribute__((packed));

/* Set DAA Energy Mask event. [WHCI 0.96] section 3.1.3.17. */
struct uwb_rc_evt_set_daa_energy_mask {
	struct uwb_rceb rceb;
	__le16 wLength;
	u8 result;
} __attribute__((packed));

/* Set Notification Filter Extended event. [WHCI 0.96] section 3.1.3.18. */
struct uwb_rc_evt_set_notification_filter_ex {
	struct uwb_rceb rceb;
	__le16 wLength;
	u8 result;
} __attribute__((packed));

/* IE Received notification. [WHCI] section 3.1.4.1. */
struct uwb_rc_evt_ie_rcv {
	struct uwb_rceb rceb;
	struct uwb_dev_addr SrcAddr;
	__le16 wIELength;
	u8 IEData[];
} __attribute__((packed));

/* Type of the received beacon. [WHCI] section 3.1.4.2. */
enum uwb_rc_beacon_type {
	UWB_RC_BEACON_TYPE_SCAN = 0,
	UWB_RC_BEACON_TYPE_NEIGHBOR,
	UWB_RC_BEACON_TYPE_OL_ALIEN,
	UWB_RC_BEACON_TYPE_NOL_ALIEN,
};

/* Beacon received notification. [WHCI] 3.1.4.2. */
struct uwb_rc_evt_beacon {
	struct uwb_rceb rceb;
	u8	bChannelNumber;
	u8	bBeaconType;
	__le16	wBPSTOffset;
	u8	bLQI;
	u8	bRSSI;
	__le16	wBeaconInfoLength;
	u8	BeaconInfo[];
} __attribute__((packed));


/* Beacon Size Change notification. [WHCI] section 3.1.4.3 */
struct uwb_rc_evt_beacon_size {
	struct uwb_rceb rceb;
	__le16 wNewBeaconSize;
} __attribute__((packed));


/* BPOIE Change notification. [WHCI] section 3.1.4.4. */
struct uwb_rc_evt_bpoie_change {
	struct uwb_rceb rceb;
	__le16 wBPOIELength;
	u8 BPOIE[];
} __attribute__((packed));


/* Beacon Slot Change notification. [WHCI] section 3.1.4.5. */
struct uwb_rc_evt_bp_slot_change {
	struct uwb_rceb rceb;
	u8 slot_info;
} __attribute__((packed));

static inline int uwb_rc_evt_bp_slot_change_slot_num(
	const struct uwb_rc_evt_bp_slot_change *evt)
{
	return evt->slot_info & 0x7f;
}

static inline int uwb_rc_evt_bp_slot_change_no_slot(
	const struct uwb_rc_evt_bp_slot_change *evt)
{
	return (evt->slot_info & 0x80) >> 7;
}

/* BP Switch IE Received notification. [WHCI] section 3.1.4.6. */
struct uwb_rc_evt_bp_switch_ie_rcv {
	struct uwb_rceb rceb;
	struct uwb_dev_addr wSrcAddr;
	__le16 wIELength;
	u8 IEData[];
} __attribute__((packed));

/* DevAddr Conflict notification. [WHCI] section 3.1.4.7. */
struct uwb_rc_evt_dev_addr_conflict {
	struct uwb_rceb rceb;
} __attribute__((packed));

/* DRP notification. [WHCI] section 3.1.4.9. */
struct uwb_rc_evt_drp {
	struct uwb_rceb           rceb;
	struct uwb_dev_addr       src_addr;
	u8                        reason;
	u8                        beacon_slot_number;
	__le16                    ie_length;
	u8                        ie_data[];
} __attribute__((packed));

static inline enum uwb_drp_notif_reason uwb_rc_evt_drp_reason(struct uwb_rc_evt_drp *evt)
{
	return evt->reason & 0x0f;
}


/* DRP Availability Change notification. [WHCI] section 3.1.4.8. */
struct uwb_rc_evt_drp_avail {
	struct uwb_rceb rceb;
	DECLARE_BITMAP(bmp, UWB_NUM_MAS);
} __attribute__((packed));

/* BP switch status notification. [WHCI] section 3.1.4.10. */
struct uwb_rc_evt_bp_switch_status {
	struct uwb_rceb rceb;
	u8 status;
	u8 slot_offset;
	__le16 bpst_offset;
	u8 move_countdown;
} __attribute__((packed));

/* Command Frame Received notification. [WHCI] section 3.1.4.11. */
struct uwb_rc_evt_cmd_frame_rcv {
	struct uwb_rceb rceb;
	__le16 receive_time;
	struct uwb_dev_addr wSrcAddr;
	struct uwb_dev_addr wDstAddr;
	__le16 control;
	__le16 reserved;
	__le16 dataLength;
	u8 data[];
} __attribute__((packed));

/* Channel Change IE Received notification. [WHCI] section 3.1.4.12. */
struct uwb_rc_evt_channel_change_ie_rcv {
	struct uwb_rceb rceb;
	struct uwb_dev_addr wSrcAddr;
	__le16 wIELength;
	u8 IEData[];
} __attribute__((packed));

/* DAA Energy Detected notification. [WHCI 0.96] section 3.1.4.14. */
struct uwb_rc_evt_daa_energy_detected {
	struct uwb_rceb rceb;
	__le16 wLength;
	u8 bandID;
	u8 reserved;
	u8 toneBmp[16];
} __attribute__((packed));


/**
 * Radio Control Interface Class Descriptor
 *
 *  WUSB 1.0 [8.6.1.2]
 */
struct uwb_rc_control_intf_class_desc {
	u8 bLength;
	u8 bDescriptorType;
	__le16 bcdRCIVersion;
} __attribute__((packed));

#endif /* #ifndef __LINUX__UWB_SPEC_H__ */
ramfc_size; uint32_t ramro_offset; uint32_t ramro_size; /* base physical adresses */ uint64_t fb_phys; uint64_t fb_available_size; uint64_t fb_mappable_pages; uint64_t fb_aper_free; struct { enum { NOUVEAU_GART_NONE = 0, NOUVEAU_GART_AGP, NOUVEAU_GART_SGDMA } type; uint64_t aper_base; uint64_t aper_size; uint64_t aper_free; struct nouveau_gpuobj *sg_ctxdma; struct page *sg_dummy_page; dma_addr_t sg_dummy_bus; /* nottm hack */ struct drm_ttm_backend *sg_be; unsigned long sg_handle; } gart_info; /* G8x/G9x virtual address space */ uint64_t vm_gart_base; uint64_t vm_gart_size; uint64_t vm_vram_base; uint64_t vm_vram_size; uint64_t vm_end; struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; int vm_vram_pt_nr; /* the mtrr covering the FB */ int fb_mtrr; struct mem_block *ramin_heap; /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ uint32_t ctx_table_size; struct nouveau_gpuobj_ref *ctx_table; struct list_head gpuobj_list; struct nvbios VBIOS; struct nouveau_bios_info *vbios; struct nv04_mode_state mode_reg; struct nv04_mode_state saved_reg; uint32_t saved_vga_font[4][16384]; uint32_t crtc_owner; uint32_t dac_users[4]; struct nouveau_suspend_resume { uint32_t fifo_mode; uint32_t graph_ctx_control; uint32_t graph_state; uint32_t *ramin_copy; uint64_t ramin_size; } susres; struct backlight_device *backlight; bool acpi_dsm; struct nouveau_channel *evo; struct { struct dentry *channel_root; } debugfs; }; static inline struct drm_nouveau_private * nouveau_bdev(struct ttm_bo_device *bd) { return container_of(bd, struct drm_nouveau_private, ttm.bdev); } static inline int nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) { struct nouveau_bo *prev; if (!pnvbo) return -EINVAL; prev = *pnvbo; *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; if (prev) { struct ttm_buffer_object *bo = &prev->bo; ttm_bo_unref(&bo); } return 0; } #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ struct drm_nouveau_private *nv = dev->dev_private; \ if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ NV_ERROR(dev, "called without init\n"); \ return -EINVAL; \ } \ } while (0) #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ struct drm_nouveau_private *nv = dev->dev_private; \ if (!nouveau_channel_owner(dev, (cl), (id))) { \ NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ DRM_CURRENTPID, (id)); \ return -EPERM; \ } \ (ch) = nv->fifos[(id)]; \ } while (0) /* nouveau_drv.c */ extern int nouveau_noagp; extern int nouveau_duallink; extern int nouveau_uscript_lvds; extern int nouveau_uscript_tmds; extern int nouveau_vram_pushbuf; extern int nouveau_vram_notify; extern int nouveau_fbpercrtc; extern char *nouveau_tv_norm; extern int nouveau_reg_debug; extern char *nouveau_vbios; /* nouveau_state.c */ extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); extern int nouveau_load(struct drm_device *, unsigned long flags); extern int nouveau_firstopen(struct drm_device *); extern void nouveau_lastclose(struct drm_device *); extern int nouveau_unload(struct drm_device *); extern int nouveau_ioctl_getparam(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_setparam(struct drm_device *, void *data, struct drm_file *); extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, uint32_t reg, uint32_t mask, uint32_t val); extern bool nouveau_wait_for_idle(struct drm_device *); extern int nouveau_card_init(struct drm_device *); extern int nouveau_ioctl_card_init(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_suspend(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_resume(struct drm_device *, void *data, struct drm_file *); /* nouveau_mem.c */ extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, uint64_t size); extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, uint64_t size, int align2, struct drm_file *, int tail); extern void nouveau_mem_takedown(struct mem_block **heap); extern void nouveau_mem_free_block(struct mem_block *); extern uint64_t nouveau_mem_fb_amount(struct drm_device *); extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); extern int nouveau_mem_init(struct drm_device *); extern int nouveau_mem_init_agp(struct drm_device *); extern void nouveau_mem_close(struct drm_device *); extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, uint32_t size, uint32_t flags, uint64_t phys); extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, uint32_t size); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(struct nouveau_channel *); extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, int cout, uint32_t *offset); extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, struct drm_file *); /* nouveau_channel.c */ extern struct drm_ioctl_desc nouveau_ioctls[]; extern int nouveau_max_ioctl; extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, int channel); extern int nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan, struct drm_file *file_priv, uint32_t fb_ctxdma, uint32_t tt_ctxdma); extern void nouveau_channel_free(struct nouveau_channel *); extern int nouveau_channel_idle(struct nouveau_channel *chan); /* nouveau_object.c */ extern int nouveau_gpuobj_early_init(struct drm_device *); extern int nouveau_gpuobj_init(struct drm_device *); extern void nouveau_gpuobj_takedown(struct drm_device *); extern void nouveau_gpuobj_late_takedown(struct drm_device *); extern int nouveau_gpuobj_suspend(struct drm_device *dev); extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); extern void nouveau_gpuobj_resume(struct drm_device *dev); extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, uint32_t vram_h, uint32_t tt_h); extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, uint32_t size, int align, uint32_t flags, struct nouveau_gpuobj **); extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, uint32_t handle, struct nouveau_gpuobj *, struct nouveau_gpuobj_ref **); extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **); extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, struct nouveau_gpuobj_ref **ref_ret); extern int nouveau_gpuobj_new_ref(struct drm_device *, struct nouveau_channel *alloc_chan, struct nouveau_channel *ref_chan, uint32_t handle, uint32_t size, int align, uint32_t flags, struct nouveau_gpuobj_ref **); extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t p_offset, uint32_t b_offset, uint32_t size, uint32_t flags, struct nouveau_gpuobj **, struct nouveau_gpuobj_ref**); extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, uint64_t offset, uint64_t size, int access, int target, struct nouveau_gpuobj **); extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, uint64_t offset, uint64_t size, int access, struct nouveau_gpuobj **, uint32_t *o_ret); extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, struct nouveau_gpuobj **); extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, struct drm_file *); /* nouveau_irq.c */ extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); extern void nouveau_irq_preinstall(struct drm_device *); extern int nouveau_irq_postinstall(struct drm_device *); extern void nouveau_irq_uninstall(struct drm_device *); /* nouveau_sgdma.c */ extern int nouveau_sgdma_init(struct drm_device *); extern void nouveau_sgdma_takedown(struct drm_device *); extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, uint32_t *page); extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); /* nouveau_debugfs.c */ #if defined(CONFIG_DRM_NOUVEAU_DEBUG) extern int nouveau_debugfs_init(struct drm_minor *); extern void nouveau_debugfs_takedown(struct drm_minor *); extern int nouveau_debugfs_channel_init(struct nouveau_channel *); extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); #else static inline int nouveau_debugfs_init(struct drm_minor *minor) { return 0; } static inline void nouveau_debugfs_takedown(struct drm_minor *minor) { } static inline int nouveau_debugfs_channel_init(struct nouveau_channel *chan) { return 0; } static inline void nouveau_debugfs_channel_fini(struct nouveau_channel *chan) { } #endif /* nouveau_dma.c */ extern int nouveau_dma_init(struct nouveau_channel *); extern int nouveau_dma_wait(struct nouveau_channel *, int size); /* nouveau_acpi.c */ #ifdef CONFIG_ACPI extern int nouveau_hybrid_setup(struct drm_device *dev); extern bool nouveau_dsm_probe(struct drm_device *dev); #else static inline int nouveau_hybrid_setup(struct drm_device *dev) { return 0; } static inline bool nouveau_dsm_probe(struct drm_device *dev) { return false; } #endif /* nouveau_backlight.c */ #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT extern int nouveau_backlight_init(struct drm_device *); extern void nouveau_backlight_exit(struct drm_device *); #else static inline int nouveau_backlight_init(struct drm_device *dev) { return 0; } static inline void nouveau_backlight_exit(struct drm_device *dev) { } #endif /* nouveau_bios.c */ extern int nouveau_bios_init(struct drm_device *); extern void nouveau_bios_takedown(struct drm_device *dev); extern int nouveau_run_vbios_init(struct drm_device *); extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, struct dcb_entry *); extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, enum dcb_gpio_tag); extern struct dcb_connector_table_entry * nouveau_bios_connector_entry(struct drm_device *, int index); extern int get_pll_limits(struct drm_device *, uint32_t limit_match, struct pll_lims *); extern int nouveau_bios_run_display_table(struct drm_device *, struct dcb_entry *, uint32_t script, int pxclk); extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, int *length); extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, bool *dl, bool *if_is_24bit); extern int run_tmds_table(struct drm_device *, struct dcb_entry *, int head, int pxclk); extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, enum LVDS_script, int pxclk); /* nouveau_ttm.c */ int nouveau_ttm_global_init(struct drm_nouveau_private *); void nouveau_ttm_global_release(struct drm_nouveau_private *); int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); /* nouveau_dp.c */ int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, uint8_t *data, int data_nr); bool nouveau_dp_detect(struct drm_encoder *); bool nouveau_dp_link_train(struct drm_encoder *); /* nv04_fb.c */ extern int nv04_fb_init(struct drm_device *); extern void nv04_fb_takedown(struct drm_device *); /* nv10_fb.c */ extern int nv10_fb_init(struct drm_device *); extern void nv10_fb_takedown(struct drm_device *); /* nv40_fb.c */ extern int nv40_fb_init(struct drm_device *); extern void nv40_fb_takedown(struct drm_device *); /* nv04_fifo.c */ extern int nv04_fifo_init(struct drm_device *); extern void nv04_fifo_disable(struct drm_device *); extern void nv04_fifo_enable(struct drm_device *); extern bool nv04_fifo_reassign(struct drm_device *, bool); extern int nv04_fifo_channel_id(struct drm_device *); extern int nv04_fifo_create_context(struct nouveau_channel *); extern void nv04_fifo_destroy_context(struct nouveau_channel *); extern int nv04_fifo_load_context(struct nouveau_channel *); extern int nv04_fifo_unload_context(struct drm_device *); /* nv10_fifo.c */ extern int nv10_fifo_init(struct drm_device *); extern int nv10_fifo_channel_id(struct drm_device *); extern int nv10_fifo_create_context(struct nouveau_channel *); extern void nv10_fifo_destroy_context(struct nouveau_channel *); extern int nv10_fifo_load_context(struct nouveau_channel *); extern int nv10_fifo_unload_context(struct drm_device *); /* nv40_fifo.c */ extern int nv40_fifo_init(struct drm_device *); extern int nv40_fifo_create_context(struct nouveau_channel *); extern void nv40_fifo_destroy_context(struct nouveau_channel *); extern int nv40_fifo_load_context(struct nouveau_channel *); extern int nv40_fifo_unload_context(struct drm_device *); /* nv50_fifo.c */ extern int nv50_fifo_init(struct drm_device *); extern void nv50_fifo_takedown(struct drm_device *); extern int nv50_fifo_channel_id(struct drm_device *); extern int nv50_fifo_create_context(struct nouveau_channel *); extern void nv50_fifo_destroy_context(struct nouveau_channel *); extern int nv50_fifo_load_context(struct nouveau_channel *); extern int nv50_fifo_unload_context(struct drm_device *); /* nv04_graph.c */ extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; extern int nv04_graph_init(struct drm_device *); extern void nv04_graph_takedown(struct drm_device *); extern void nv04_graph_fifo_access(struct drm_device *, bool); extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); extern int nv04_graph_create_context(struct nouveau_channel *); extern void nv04_graph_destroy_context(struct nouveau_channel *); extern int nv04_graph_load_context(struct nouveau_channel *); extern int nv04_graph_unload_context(struct drm_device *); extern void nv04_graph_context_switch(struct drm_device *); /* nv10_graph.c */ extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; extern int nv10_graph_init(struct drm_device *); extern void nv10_graph_takedown(struct drm_device *); extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); extern int nv10_graph_create_context(struct nouveau_channel *); extern void nv10_graph_destroy_context(struct nouveau_channel *); extern int nv10_graph_load_context(struct nouveau_channel *); extern int nv10_graph_unload_context(struct drm_device *); extern void nv10_graph_context_switch(struct drm_device *); /* nv20_graph.c */ extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; extern int nv20_graph_create_context(struct nouveau_channel *); extern void nv20_graph_destroy_context(struct nouveau_channel *); extern int nv20_graph_load_context(struct nouveau_channel *); extern int nv20_graph_unload_context(struct drm_device *); extern int nv20_graph_init(struct drm_device *); extern void nv20_graph_takedown(struct drm_device *); extern int nv30_graph_init(struct drm_device *); /* nv40_graph.c */ extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; extern int nv40_graph_init(struct drm_device *); extern void nv40_graph_takedown(struct drm_device *); extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); extern int nv40_graph_create_context(struct nouveau_channel *); extern void nv40_graph_destroy_context(struct nouveau_channel *); extern int nv40_graph_load_context(struct nouveau_channel *); extern int nv40_graph_unload_context(struct drm_device *); extern int nv40_grctx_init(struct drm_device *); extern void nv40_grctx_fini(struct drm_device *); extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *); /* nv50_graph.c */ extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; extern int nv50_graph_init(struct drm_device *); extern void nv50_graph_takedown(struct drm_device *); extern void nv50_graph_fifo_access(struct drm_device *, bool); extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); extern int nv50_graph_create_context(struct nouveau_channel *); extern void nv50_graph_destroy_context(struct nouveau_channel *); extern int nv50_graph_load_context(struct nouveau_channel *); extern int nv50_graph_unload_context(struct drm_device *); extern void nv50_graph_context_switch(struct drm_device *); /* nv04_instmem.c */ extern int nv04_instmem_init(struct drm_device *); extern void nv04_instmem_takedown(struct drm_device *); extern int nv04_instmem_suspend(struct drm_device *); extern void nv04_instmem_resume(struct drm_device *); extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, uint32_t *size); extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); extern void nv04_instmem_prepare_access(struct drm_device *, bool write); extern void nv04_instmem_finish_access(struct drm_device *); /* nv50_instmem.c */ extern int nv50_instmem_init(struct drm_device *); extern void nv50_instmem_takedown(struct drm_device *); extern int nv50_instmem_suspend(struct drm_device *); extern void nv50_instmem_resume(struct drm_device *); extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, uint32_t *size); extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); extern void nv50_instmem_prepare_access(struct drm_device *, bool write); extern void nv50_instmem_finish_access(struct drm_device *); /* nv04_mc.c */ extern int nv04_mc_init(struct drm_device *); extern void nv04_mc_takedown(struct drm_device *); /* nv40_mc.c */ extern int nv40_mc_init(struct drm_device *); extern void nv40_mc_takedown(struct drm_device *); /* nv50_mc.c */ extern int nv50_mc_init(struct drm_device *); extern void nv50_mc_takedown(struct drm_device *); /* nv04_timer.c */ extern int nv04_timer_init(struct drm_device *); extern uint64_t nv04_timer_read(struct drm_device *); extern void nv04_timer_takedown(struct drm_device *); extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg); /* nv04_dac.c */ extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector); extern int nv04_dac_output_offset(struct drm_encoder *encoder); extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); /* nv04_dfp.c */ extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry); extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, int head, bool dl); extern void nv04_dfp_disable(struct drm_device *dev, int head); extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); /* nv04_tv.c */ extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); /* nv17_tv.c */ extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector, uint32_t pin_mask); /* nv04_display.c */ extern int nv04_display_create(struct drm_device *); extern void nv04_display_destroy(struct drm_device *); extern void nv04_display_restore(struct drm_device *); /* nv04_crtc.c */ extern int nv04_crtc_create(struct drm_device *, int index); /* nouveau_bo.c */ extern struct ttm_bo_driver nouveau_bo_driver; extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, int size, int align, uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, bool no_vm, bool mappable, struct nouveau_bo **); extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); extern int nouveau_bo_unpin(struct nouveau_bo *); extern int nouveau_bo_map(struct nouveau_bo *); extern void nouveau_bo_unmap(struct nouveau_bo *); extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); /* nouveau_fence.c */ struct nouveau_fence; extern int nouveau_fence_init(struct nouveau_channel *); extern void nouveau_fence_fini(struct nouveau_channel *); extern void nouveau_fence_update(struct nouveau_channel *); extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, bool emit); extern int nouveau_fence_emit(struct nouveau_fence *); struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); extern bool nouveau_fence_signalled(void *obj, void *arg); extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); extern int nouveau_fence_flush(void *obj, void *arg); extern void nouveau_fence_unref(void **obj); extern void *nouveau_fence_ref(void *obj); extern void nouveau_fence_handler(struct drm_device *dev, int channel); /* nouveau_gem.c */ extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, int size, int align, uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, bool no_vm, bool mappable, struct nouveau_bo **); extern int nouveau_gem_object_new(struct drm_gem_object *); extern void nouveau_gem_object_del(struct drm_gem_object *); extern int nouveau_gem_ioctl_new(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_pin(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_tile(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_info(struct drm_device *, void *, struct drm_file *); /* nv17_gpio.c */ int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); #ifndef ioread32_native #ifdef __BIG_ENDIAN #define ioread16_native ioread16be #define iowrite16_native iowrite16be #define ioread32_native ioread32be #define iowrite32_native iowrite32be #else /* def __BIG_ENDIAN */ #define ioread16_native ioread16 #define iowrite16_native iowrite16 #define ioread32_native ioread32 #define iowrite32_native iowrite32 #endif /* def __BIG_ENDIAN else */ #endif /* !ioread32_native */ /* channel control reg access */ static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) { return ioread32_native(chan->user + reg); } static inline void nvchan_wr32(struct nouveau_channel *chan, unsigned reg, u32 val) { iowrite32_native(val, chan->user + reg); } /* register access */ static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) { struct drm_nouveau_private *dev_priv = dev->dev_private; return ioread32_native(dev_priv->mmio + reg); } static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) { struct drm_nouveau_private *dev_priv = dev->dev_private; iowrite32_native(val, dev_priv->mmio + reg); } static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) { struct drm_nouveau_private *dev_priv = dev->dev_private; return ioread8(dev_priv->mmio + reg); } static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) { struct drm_nouveau_private *dev_priv = dev->dev_private; iowrite8(val, dev_priv->mmio + reg); } #define nv_wait(reg, mask, val) \ nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) /* PRAMIN access */ static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) { struct drm_nouveau_private *dev_priv = dev->dev_private; return ioread32_native(dev_priv->ramin + offset); } static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) { struct drm_nouveau_private *dev_priv = dev->dev_private; iowrite32_native(val, dev_priv->ramin + offset); } /* object access */ static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, unsigned index) { return nv_ri32(dev, obj->im_pramin->start + index * 4); } static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, unsigned index, u32 val) { nv_wi32(dev, obj->im_pramin->start + index * 4, val); } /* * Logging * Argument d is (struct drm_device *). */ #define NV_PRINTK(level, d, fmt, arg...) \ printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ pci_name(d->pdev), ##arg) #ifndef NV_DEBUG_NOTRACE #define NV_DEBUG(d, fmt, arg...) do { \ if (drm_debug) { \ NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ __LINE__, ##arg); \ } \ } while (0) #else #define NV_DEBUG(d, fmt, arg...) do { \ if (drm_debug) \ NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ } while (0) #endif #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) /* nouveau_reg_debug bitmask */ enum { NOUVEAU_REG_DEBUG_MC = 0x1, NOUVEAU_REG_DEBUG_VIDEO = 0x2, NOUVEAU_REG_DEBUG_FB = 0x4, NOUVEAU_REG_DEBUG_EXTDEV = 0x8, NOUVEAU_REG_DEBUG_CRTC = 0x10, NOUVEAU_REG_DEBUG_RAMDAC = 0x20, NOUVEAU_REG_DEBUG_VGACRTC = 0x40, NOUVEAU_REG_DEBUG_RMVIO = 0x80, NOUVEAU_REG_DEBUG_VGAATTR = 0x100, NOUVEAU_REG_DEBUG_EVO = 0x200, }; #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ } while (0) static inline bool nv_two_heads(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; const int impl = dev->pci_device & 0x0ff0; if (dev_priv->card_type >= NV_10 && impl != 0x0100 && impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) return true; return false; } static inline bool nv_gf4_disp_arch(struct drm_device *dev) { return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; } static inline bool nv_two_reg_pll(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; const int impl = dev->pci_device & 0x0ff0; if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) return true; return false; } #define NV50_NVSW 0x0000506e #define NV50_NVSW_DMA_SEMAPHORE 0x00000060 #define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 #define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 #define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c #define NV50_NVSW_DMA_VBLSEM 0x0000018c #define NV50_NVSW_VBLSEM_OFFSET 0x00000400 #define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 #define NV50_NVSW_VBLSEM_RELEASE 0x00000408 #endif /* __NOUVEAU_DRV_H__ */