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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
version . */
#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define MEMARB_INTR_VECT 0x31
#define GEN_IO_INTR_VECT 0x32
#define GIO_INTR_VECT GEN_IO_INTR_VECT
#define IOP0_INTR_VECT 0x33
#define IOP1_INTR_VECT 0x34
#define IOP2_INTR_VECT 0x35
#define IOP3_INTR_VECT 0x36
#define DMA0_INTR_VECT 0x37
#define DMA1_INTR_VECT 0x38
#define DMA2_INTR_VECT 0x39
#define DMA3_INTR_VECT 0x3a
#define DMA4_INTR_VECT 0x3b
#define DMA5_INTR_VECT 0x3c
#define DMA6_INTR_VECT 0x3d
#define DMA7_INTR_VECT 0x3e
#define DMA8_INTR_VECT 0x3f
#define DMA9_INTR_VECT 0x40
#define ATA_INTR_VECT 0x41
#define SSER0_INTR_VECT 0x42
#define SSER1_INTR_VECT 0x43
#define SER0_INTR_VECT 0x44
#define SER1_INTR_VECT 0x45
#define SER2_INTR_VECT 0x46
#define SER3_INTR_VECT 0x47
#define P21_INTR_VECT 0x48
#define ETH0_INTR_VECT 0x49
#define ETH1_INTR_VECT 0x4a
#define TIMER_INTR_VECT 0x4b
#define TIMER0_INTR_VECT TIMER_INTR_VECT
#define BIF_ARB_INTR_VECT 0x4c
#define BIF_DMA_INTR_VECT 0x4d
#define EXT_INTR_VECT 0x4e
#define IPI_INTR_VECT 0x4f
#define NBR_INTR_VECT 0x50
#endif
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