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generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 14:35:55 -0400
rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); rt73usb_register_write(rt2x00dev, PHY_CSR3, reg); /* * Wait until the BBP becomes ready. */ reg = rt73usb_bbp_check(rt2x00dev); if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); *value = 0xff; return; } *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); } static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u32 value) { u32 reg; unsigned int i; if (!word) return; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg); if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY)) goto rf_write; udelay(REGISTER_BUSY_DELAY); } ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n"); return; rf_write: reg = 0; rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value); /* * RF5225 and RF2527 contain 21 bits per RF register value, * all others contain 20 bits. */ rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) || rt2x00_rf(&rt2x00dev->chip, RF2527))); rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); rt73usb_register_write(rt2x00dev, PHY_CSR4, reg); rt2x00_rf_write(rt2x00dev, word, value); } #ifdef CONFIG_RT2X00_LIB_DEBUGFS #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev, const unsigned int word, u32 *data) { rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data); } static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev, const unsigned int word, u32 data) { rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data); } static const struct rt2x00debug rt73usb_rt2x00debug = { .owner = THIS_MODULE, .csr = { .read = rt73usb_read_csr, .write = rt73usb_write_csr, .word_size = sizeof(u32), .word_count = CSR_REG_SIZE / sizeof(u32), }, .eeprom = { .read = rt2x00_eeprom_read, .write = rt2x00_eeprom_write, .word_size = sizeof(u16), .word_count = EEPROM_SIZE / sizeof(u16), }, .bbp = { .read = rt73usb_bbp_read, .write = rt73usb_bbp_write, .word_size = sizeof(u8), .word_count = BBP_SIZE / sizeof(u8), }, .rf = { .read = rt2x00_rf_read, .write = rt73usb_rf_write, .word_size = sizeof(u32), .word_count = RF_SIZE / sizeof(u32), }, }; #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ /* * Configuration handlers. */ static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac) { u32 tmp; tmp = le32_to_cpu(mac[1]); rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); mac[1] = cpu_to_le32(tmp); rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac, (2 * sizeof(__le32))); } static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid) { u32 tmp; tmp = le32_to_cpu(bssid[1]); rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3); bssid[1] = cpu_to_le32(tmp); rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid, (2 * sizeof(__le32))); } static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type, const int tsf_sync) { u32 reg; /* * Clear current synchronisation setup. * For the Beacon base registers we only need to clear * the first byte since that byte contains the VALID and OWNER * bits which (when set to 0) will invalidate the entire beacon. */ rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); /* * Enable synchronisation. */ rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync); rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); } static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev, const int short_preamble, const int ack_timeout, const int ack_consume_time) { u32 reg; /* * When in atomic context, reschedule and let rt2x00lib * call this function again. */ if (in_atomic()) { queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work); return; } rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout); rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, !!short_preamble); rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); } static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev, const int basic_rate_mask) { rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask); } static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, struct rf_channel *rf, const int txpower) { u8 r3; u8 r94; u8 smart; rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || rt2x00_rf(&rt2x00dev->chip, RF2527)); rt73usb_bbp_read(rt2x00dev, 3, &r3); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); rt73usb_bbp_write(rt2x00dev, 3, r3); r94 = 6; if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) r94 += txpower - MAX_TXPOWER; else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) r94 += txpower; rt73usb_bbp_write(rt2x00dev, 94, r94); rt73usb_rf_write(rt2x00dev, 1, rf->rf1); rt73usb_rf_write(rt2x00dev, 2, rf->rf2); rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); rt73usb_rf_write(rt2x00dev, 4, rf->rf4); rt73usb_rf_write(rt2x00dev, 1, rf->rf1); rt73usb_rf_write(rt2x00dev, 2, rf->rf2); rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); rt73usb_rf_write(rt2x00dev, 4, rf->rf4); rt73usb_rf_write(rt2x00dev, 1, rf->rf1); rt73usb_rf_write(rt2x00dev, 2, rf->rf2); rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); rt73usb_rf_write(rt2x00dev, 4, rf->rf4); udelay(10); } static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, const int txpower) { struct rf_channel rf; rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); rt73usb_config_channel(rt2x00dev, &rf, txpower); } static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) { u8 r3; u8 r4; u8 r77; u8 temp; rt73usb_bbp_read(rt2x00dev, 3, &r3); rt73usb_bbp_read(rt2x00dev, 4, &r4); rt73usb_bbp_read(rt2x00dev, 77, &r77); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); /* * Configure the RX antenna. */ switch (ant->rx) { case ANTENNA_HW_DIVERSITY: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags) && (rt2x00dev->curr_hwmode != HWMODE_A); rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); break; case ANTENNA_A: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); if (rt2x00dev->curr_hwmode == HWMODE_A) rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); else rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); break; case ANTENNA_SW_DIVERSITY: /* * NOTE: We should never come here because rt2x00lib is * supposed to catch this and send us the correct antenna * explicitely. However we are nog going to bug about this. * Instead, just default to antenna B. */ case ANTENNA_B: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); if (rt2x00dev->curr_hwmode == HWMODE_A) rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); else rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); break; } rt73usb_bbp_write(rt2x00dev, 77, r77); rt73usb_bbp_write(rt2x00dev, 3, r3); rt73usb_bbp_write(rt2x00dev, 4, r4); } static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) { u8 r3; u8 r4; u8 r77; rt73usb_bbp_read(rt2x00dev, 3, &r3); rt73usb_bbp_read(rt2x00dev, 4, &r4); rt73usb_bbp_read(rt2x00dev, 77, &r77); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); /* * Configure the RX antenna. */ switch (ant->rx) { case ANTENNA_HW_DIVERSITY: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); break; case ANTENNA_A: rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); break; case ANTENNA_SW_DIVERSITY: /* * NOTE: We should never come here because rt2x00lib is * supposed to catch this and send us the correct antenna * explicitely. However we are nog going to bug about this. * Instead, just default to antenna B. */ case ANTENNA_B: rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); break; } rt73usb_bbp_write(rt2x00dev, 77, r77); rt73usb_bbp_write(rt2x00dev, 3, r3); rt73usb_bbp_write(rt2x00dev, 4, r4); } struct antenna_sel { u8 word; /* * value[0] -> non-LNA * value[1] -> LNA */ u8 value[2]; }; static const struct antenna_sel antenna_sel_a[] = { { 96, { 0x58, 0x78 } }, { 104, { 0x38, 0x48 } }, { 75, { 0xfe, 0x80 } }, { 86, { 0xfe, 0x80 } }, { 88, { 0xfe, 0x80 } }, { 35, { 0x60, 0x60 } }, { 97, { 0x58, 0x58 } }, { 98, { 0x58, 0x58 } }, }; static const struct antenna_sel antenna_sel_bg[] = { { 96, { 0x48, 0x68 } }, { 104, { 0x2c, 0x3c } }, { 75, { 0xfe, 0x80 } }, { 86, { 0xfe, 0x80 } }, { 88, { 0xfe, 0x80 } }, { 35, { 0x50, 0x50 } }, { 97, { 0x48, 0x48 } }, { 98, { 0x48, 0x48 } }, }; static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) { const struct antenna_sel *sel; unsigned int lna; unsigned int i; u32 reg; if (rt2x00dev->curr_hwmode == HWMODE_A) { sel = antenna_sel_a; lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); } else { sel = antenna_sel_bg; lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); } for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg); rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, (rt2x00dev->curr_hwmode == HWMODE_B || rt2x00dev->curr_hwmode == HWMODE_G)); rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, (rt2x00dev->curr_hwmode == HWMODE_A)); rt73usb_register_write(rt2x00dev, PHY_CSR0, reg); if (rt2x00_rf(&rt2x00dev->chip, RF5226) || rt2x00_rf(&rt2x00dev->chip, RF5225)) rt73usb_config_antenna_5x(rt2x00dev, ant); else if (rt2x00_rf(&rt2x00dev->chip, RF2528) || rt2x00_rf(&rt2x00dev->chip, RF2527)) rt73usb_config_antenna_2x(rt2x00dev, ant); } static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_conf *libconf) { u32 reg; rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time); rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg); rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs); rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs); rt73usb_register_write(rt2x00dev, MAC_CSR8, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, libconf->conf->beacon_int * 16); rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); } static void rt73usb_config(struct rt2x00_dev *rt2x00dev, const unsigned int flags, struct rt2x00lib_conf *libconf) { if (flags & CONFIG_UPDATE_PHYMODE) rt73usb_config_phymode(rt2x00dev, libconf->basic_rates); if (flags & CONFIG_UPDATE_CHANNEL) rt73usb_config_channel(rt2x00dev, &libconf->rf, libconf->conf->power_level); if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL)) rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); if (flags & CONFIG_UPDATE_ANTENNA) rt73usb_config_antenna(rt2x00dev, &libconf->ant); if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) rt73usb_config_duration(rt2x00dev, libconf); } /* * LED functions. */ static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev) { u32 reg; rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg); rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70); rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30); rt73usb_register_write(rt2x00dev, MAC_CSR14, reg); rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1); rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)); rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, (rt2x00dev->rx_status.phymode != MODE_IEEE80211A)); rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000, rt2x00dev->led_reg, REGISTER_TIMEOUT); } static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev) { rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0); rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0); rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0); rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000, rt2x00dev->led_reg, REGISTER_TIMEOUT); } static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi) { u32 led; if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH) return; /* * Led handling requires a positive value for the rssi, * to do that correctly we need to add the correction. */ rssi += rt2x00dev->rssi_offset; if (rssi <= 30) led = 0; else if (rssi <= 39) led = 1; else if (rssi <= 49) led = 2; else if (rssi <= 53) led = 3; else if (rssi <= 63) led = 4; else led = 5; rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led, rt2x00dev->led_reg, REGISTER_TIMEOUT); } /* * Link tuning */ static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) { u32 reg; /* * Update FCS error count from register. */ rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); /* * Update False CCA count from register. */ rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); } static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev) { rt73usb_bbp_write(rt2x00dev, 17, 0x20); rt2x00dev->link.vgc_level = 0x20; } static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev) { int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); u8 r17; u8 up_bound; u8 low_bound; /* * Update Led strength */ rt73usb_activity_led(rt2x00dev, rssi); rt73usb_bbp_read(rt2x00dev, 17, &r17); /* * Determine r17 bounds. */ if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) { low_bound = 0x28; up_bound = 0x48; if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { low_bound += 0x10; up_bound += 0x10; } } else { if (rssi > -82) { low_bound = 0x1c; up_bound = 0x40; } else if (rssi > -84) { low_bound = 0x1c; up_bound = 0x20; } else { low_bound = 0x1c; up_bound = 0x1c; } if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { low_bound += 0x14; up_bound += 0x10; } } /* * Special big-R17 for very short distance */ if (rssi > -35) { if (r17 != 0x60) rt73usb_bbp_write(rt2x00dev, 17, 0x60); return; } /* * Special big-R17 for short distance */ if (rssi >= -58) { if (r17 != up_bound) rt73usb_bbp_write(rt2x00dev, 17, up_bound); return; } /* * Special big-R17 for middle-short distance */ if (rssi >= -66) { low_bound += 0x10; if (r17 != low_bound) rt73usb_bbp_write(rt2x00dev, 17, low_bound); return; } /* * Special mid-R17 for middle distance */ if (rssi >= -74) { if (r17 != (low_bound + 0x10)) rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08); return; } /* * Special case: Change up_bound based on the rssi. * Lower up_bound when rssi is weaker then -74 dBm. */ up_bound -= 2 * (-74 - rssi); if (low_bound > up_bound) up_bound = low_bound; if (r17 > up_bound) { rt73usb_bbp_write(rt2x00dev, 17, up_bound); return; } /* * r17 does not yet exceed upper limit, continue and base * the r17 tuning on the false CCA count. */ if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) { r17 += 4; if (r17 > up_bound) r17 = up_bound; rt73usb_bbp_write(rt2x00dev, 17, r17); } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) { r17 -= 4; if (r17 < low_bound) r17 = low_bound; rt73usb_bbp_write(rt2x00dev, 17, r17); } } /* * Firmware name function. */ static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) { return FIRMWARE_RT2571; } /* * Initialization functions. */ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data, const size_t len) { unsigned int i; int status; u32 reg; char *ptr = data; char *cache; int buflen; int timeout; /* * Wait for stable hardware. */ for (i = 0; i < 100; i++) { rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); if (reg) break; msleep(1); } if (!reg) { ERROR(rt2x00dev, "Unstable hardware.\n"); return -EBUSY; } /* * Write firmware to device. * We setup a seperate cache for this action, * since we are going to write larger chunks of data * then normally used cache size. */ cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL); if (!cache) { ERROR(rt2x00dev, "Failed to allocate firmware cache.\n"); return -ENOMEM; } for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) { buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE); timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32)); memcpy(cache, ptr, buflen); rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE, USB_VENDOR_REQUEST_OUT, FIRMWARE_IMAGE_BASE + i, 0x0000, cache, buflen, timeout); ptr += buflen; } kfree(cache); /* * Send firmware request to device to load firmware, * we need to specify a long timeout time. */ status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0000, USB_MODE_FIRMWARE, REGISTER_TIMEOUT_FIRMWARE); if (status < 0) { ERROR(rt2x00dev, "Failed to write Firmware to device.\n"); return status; } rt73usb_disable_led(rt2x00dev); return 0; } static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) { u32 reg; rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg); rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg); /* * CCK TXD BBP registers */ rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg); /* * OFDM TXD BBP registers */ rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg); rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg); rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg); rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg); rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg); rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); rt73usb_register_write(rt2x00dev, MAC_CSR6, reg); rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) return -EBUSY; rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); /* * Invalidate all Shared Keys (SEC_CSR0), * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) */ rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); reg = 0x000023b0; if (rt2x00_rf(&rt2x00dev->chip, RF5225) || rt2x00_rf(&rt2x00dev->chip, RF2527)) rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); rt73usb_register_write(rt2x00dev, PHY_CSR1, reg); rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg); rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0); rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0); rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg); rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192); rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48); rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); /* * We must clear the error counters. * These registers are cleared on read, * so we may pass a useless variable to store the value. */ rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); rt73usb_register_read(rt2x00dev, STA_CSR2, &reg); /* * Reset MAC and BBP registers. */ rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); return 0; } static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) { unsigned int i; u16 eeprom; u8 reg_id; u8 value; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt73usb_bbp_read(rt2x00dev, 0, &value); if ((value != 0xff) && (value != 0x00)) goto continue_csr_init; NOTICE(rt2x00dev, "Waiting for BBP register.\n"); udelay(REGISTER_BUSY_DELAY); } ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); return -EACCES; continue_csr_init: rt73usb_bbp_write(rt2x00dev, 3, 0x80); rt73usb_bbp_write(rt2x00dev, 15, 0x30); rt73usb_bbp_write(rt2x00dev, 21, 0xc8); rt73usb_bbp_write(rt2x00dev, 22, 0x38); rt73usb_bbp_write(rt2x00dev, 23, 0x06); rt73usb_bbp_write(rt2x00dev, 24, 0xfe); rt73usb_bbp_write(rt2x00dev, 25, 0x0a); rt73usb_bbp_write(rt2x00dev, 26, 0x0d); rt73usb_bbp_write(rt2x00dev, 32, 0x0b); rt73usb_bbp_write(rt2x00dev, 34, 0x12); rt73usb_bbp_write(rt2x00dev, 37, 0x07); rt73usb_bbp_write(rt2x00dev, 39, 0xf8); rt73usb_bbp_write(rt2x00dev, 41, 0x60); rt73usb_bbp_write(rt2x00dev, 53, 0x10); rt73usb_bbp_write(rt2x00dev, 54, 0x18); rt73usb_bbp_write(rt2x00dev, 60, 0x10); rt73usb_bbp_write(rt2x00dev, 61, 0x04); rt73usb_bbp_write(rt2x00dev, 62, 0x04); rt73usb_bbp_write(rt2x00dev, 75, 0xfe); rt73usb_bbp_write(rt2x00dev, 86, 0xfe); rt73usb_bbp_write(rt2x00dev, 88, 0xfe); rt73usb_bbp_write(rt2x00dev, 90, 0x0f); rt73usb_bbp_write(rt2x00dev, 99, 0x00); rt73usb_bbp_write(rt2x00dev, 102, 0x16); rt73usb_bbp_write(rt2x00dev, 107, 0x04); DEBUG(rt2x00dev, "Start initialization from EEPROM...\n"); for (i = 0; i < EEPROM_BBP_SIZE; i++) { rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); if (eeprom != 0xffff && eeprom != 0x0000) { reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n", reg_id, value); rt73usb_bbp_write(rt2x00dev, reg_id, value); } } DEBUG(rt2x00dev, "...End initialization from EEPROM.\n"); return 0; } /* * Device state switch handlers. */ static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state) { u32 reg; rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, state == STATE_RADIO_RX_OFF); rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); } static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) { /* * Initialize all registers. */ if (rt73usb_init_registers(rt2x00dev) || rt73usb_init_bbp(rt2x00dev)) { ERROR(rt2x00dev, "Register initialization failed.\n"); return -EIO; } rt2x00usb_enable_radio(rt2x00dev); /* * Enable LED */ rt73usb_enable_led(rt2x00dev); return 0; } static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) { /* * Disable LED */ rt73usb_disable_led(rt2x00dev); rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); /* * Disable synchronisation. */ rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); rt2x00usb_disable_radio(rt2x00dev); } static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) { u32 reg; unsigned int i; char put_to_sleep; char current_state; put_to_sleep = (state != STATE_AWAKE); rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); rt73usb_register_write(rt2x00dev, MAC_CSR12, reg); /* * Device is not guaranteed to be in the requested state yet. * We must wait until the register indicates that the * device has entered the correct state. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); current_state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); if (current_state == !put_to_sleep) return 0; msleep(10); } NOTICE(rt2x00dev, "Device failed to enter state %d, " "current device state %d.\n", !put_to_sleep, current_state); return -EBUSY; } static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,