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config SUPERH
	def_bool y
	select EMBEDDED
	select HAVE_CLK
	select HAVE_IDE if HAS_IOPORT
	select HAVE_MEMBLOCK
	select HAVE_OPROFILE
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_ARCH_TRACEHOOK
	select HAVE_DMA_API_DEBUG
	select HAVE_DMA_ATTRS
	select HAVE_IRQ_WORK
	select HAVE_PERF_EVENTS
	select PERF_USE_VMALLOC
	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_BZIP2
	select HAVE_KERNEL_LZMA
	select HAVE_KERNEL_LZO
	select HAVE_SYSCALL_TRACEPOINTS
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_GENERIC_HARDIRQS
	select HAVE_SPARSE_IRQ
	select RTC_LIB
	select GENERIC_ATOMIC64
	select GENERIC_HARDIRQS_NO_DEPRECATED
	help
	  The SuperH is a RISC processor targeted for use in embedded systems
	  and consumer electronics; it was also used in the Sega Dreamcast
	  gaming console.  The SuperH port has a home page at
	  <http://www.linux-sh.org/>.

config SUPERH32
	def_bool ARCH = "sh"
	select HAVE_KPROBES
	select HAVE_KRETPROBES
	select HAVE_IOREMAP_PROT if MMU && !X2TLB
	select HAVE_FUNCTION_TRACER
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_DYNAMIC_FTRACE
	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
	select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_ARCH_KGDB
	select HAVE_HW_BREAKPOINT
	select HAVE_MIXED_BREAKPOINTS_REGS
	select PERF_EVENTS
	select ARCH_HIBERNATION_POSSIBLE if MMU
	select SPARSE_IRQ

config SUPERH64
	def_bool ARCH = "sh64"

config ARCH_DEFCONFIG
	string
	default "arch/sh/configs/shx3_defconfig" if SUPERH32
	default "arch/sh/configs/cayman_defconfig" if SUPERH64

config RWSEM_GENERIC_SPINLOCK
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	bool

config GENERIC_BUG
	def_bool y
	depends on BUG && SUPERH32

config GENERIC_CSUM
	def_bool y
	depends on SUPERH64

config GENERIC_FIND_NEXT_BIT
	def_bool y

config GENERIC_HWEIGHT
	def_bool y

config IRQ_PER_CPU
	def_bool y

config GENERIC_GPIO
	def_bool n

config GENERIC_CALIBRATE_DELAY
	bool

config GENERIC_IOMAP
	bool

config GENERIC_CLOCKEVENTS
	def_bool y

config GENERIC_CLOCKEVENTS_BROADCAST
	bool

config GENERIC_CMOS_UPDATE
	def_bool y
	depends on SH_SH03 || SH_DREAMCAST

config GENERIC_LOCKBREAK
	def_bool y
	depends on SMP && PREEMPT

config SYS_SUPPORTS_PM
	bool
	depends on !SMP

config ARCH_SUSPEND_POSSIBLE
	def_bool n

config ARCH_HIBERNATION_POSSIBLE
	def_bool n

config SYS_SUPPORTS_APM_EMULATION
	bool
	select ARCH_SUSPEND_POSSIBLE

config SYS_SUPPORTS_HUGETLBFS
	bool

config SYS_SUPPORTS_SMP
	bool

config SYS_SUPPORTS_NUMA
	bool

config SYS_SUPPORTS_PCI
	bool

config SYS_SUPPORTS_CMT
	bool

config SYS_SUPPORTS_MTU2
	bool

config SYS_SUPPORTS_TMU
	bool

config STACKTRACE_SUPPORT
	def_bool y

config LOCKDEP_SUPPORT
	def_bool y

config HAVE_LATENCYTOP_SUPPORT
	def_bool y

config ARCH_HAS_ILOG2_U32
	def_bool n

config ARCH_HAS_ILOG2_U64
	def_bool n

config ARCH_NO_VIRT_TO_BUS
	def_bool y

config ARCH_HAS_DEFAULT_IDLE
	def_bool y

config ARCH_HAS_CPU_IDLE_WAIT
	def_bool y

config NO_IOPORT
	bool

config IO_TRAPPED
	bool

config DMA_COHERENT
	bool

config DMA_NONCOHERENT
	def_bool !DMA_COHERENT

config NEED_DMA_MAP_STATE
	def_bool DMA_NONCOHERENT

config NEED_SG_DMA_LENGTH
	def_bool y

source "init/Kconfig"

source "kernel/Kconfig.freezer"

menu "System type"

#
# Processor families
#
config CPU_SH2
	bool

config CPU_SH2A
	bool
	select CPU_SH2

config CPU_SH3
	bool
	select CPU_HAS_INTEVT
	select CPU_HAS_SR_RB
	select SYS_SUPPORTS_TMU

config CPU_SH4
	bool
	select CPU_HAS_INTEVT
	select CPU_HAS_SR_RB
	select CPU_HAS_FPU if !CPU_SH4AL_DSP
	select SYS_SUPPORTS_TMU
	select SYS_SUPPORTS_HUGETLBFS if MMU

config CPU_SH4A
	bool
	select CPU_SH4

config CPU_SH4AL_DSP
	bool
	select CPU_SH4A
	select CPU_HAS_DSP

config CPU_SH5
	bool
	select CPU_HAS_FPU
	select SYS_SUPPORTS_TMU
	select SYS_SUPPORTS_HUGETLBFS if MMU

config CPU_SHX2
	bool

config CPU_SHX3
	bool
	select DMA_COHERENT
	select SYS_SUPPORTS_SMP
	select SYS_SUPPORTS_NUMA

config ARCH_SHMOBILE
	bool
	select ARCH_SUSPEND_POSSIBLE
	select PM
	select PM_RUNTIME

config CPU_HAS_PMU
       depends on CPU_SH4 || CPU_SH4A
       default y
       bool

if SUPERH32

choice
	prompt "Processor sub-type selection"

#
# Processor subtypes
#

# SH-2 Processor Support

config CPU_SUBTYPE_SH7619
	bool "Support SH7619 processor"
	select CPU_SH2
	select SYS_SUPPORTS_CMT

# SH-2A Processor Support

config CPU_SUBTYPE_SH7201
	bool "Support SH7201 processor"
	select CPU_SH2A
	select CPU_HAS_FPU
	select SYS_SUPPORTS_MTU2
 
config CPU_SUBTYPE_SH7203
	bool "Support SH7203 processor"
	select CPU_SH2A
	select CPU_HAS_FPU
	select SYS_SUPPORTS_CMT
	select SYS_SUPPORTS_MTU2

config CPU_SUBTYPE_SH7206
	bool "Support SH7206 processor"
	select CPU_SH2A
	select SYS_SUPPORTS_CMT
	select SYS_SUPPORTS_MTU2

config CPU_SUBTYPE_SH7263
	bool "Support SH7263 processor"
	select CPU_SH2A
	select CPU_HAS_FPU
	select SYS_SUPPORTS_CMT
	select SYS_SUPPORTS_MTU2

config CPU_SUBTYPE_MXG
	bool "Support MX-G processor"
	select CPU_SH2A
	select SYS_SUPPORTS_MTU2
	help
	  Select MX-G if running on an R8A03022BG part.

# SH-3 Processor Support

config CPU_SUBTYPE_SH7705
	bool "Support SH7705 processor"
	select CPU_SH3

config CPU_SUBTYPE_SH7706
	bool "Support SH7706 processor"
	select CPU_SH3
	help
	  Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.

config CPU_SUBTYPE_SH7707
	bool "Support SH7707 processor"
	select CPU_SH3
	help
	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.

config CPU_SUBTYPE_SH7708
	bool "Support SH7708 processor"
	select CPU_SH3
	help
	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
	  if you have a 100 Mhz SH-3 HD6417708R CPU.

config CPU_SUBTYPE_SH7709
	bool "Support SH7709 processor"
	select CPU_SH3
	help
	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.

config CPU_SUBTYPE_SH7710
	bool "Support SH7710 processor"
	select CPU_SH3
	select CPU_HAS_DSP
	help
	  Select SH7710 if you have a SH3-DSP SH7710 CPU.

config CPU_SUBTYPE_SH7712
	bool "Support SH7712 processor"
	select CPU_SH3
	select CPU_HAS_DSP
	help
	  Select SH7712 if you have a SH3-DSP SH7712 CPU.

config CPU_SUBTYPE_SH7720
	bool "Support SH7720 processor"
	select CPU_SH3
	select CPU_HAS_DSP
	select SYS_SUPPORTS_CMT
	help
	  Select SH7720 if you have a SH3-DSP SH7720 CPU.

config CPU_SUBTYPE_SH7721
	bool "Support SH7721 processor"
	select CPU_SH3
	select CPU_HAS_DSP
	select SYS_SUPPORTS_CMT
	help
	  Select SH7721 if you have a SH3-DSP SH7721 CPU.

# SH-4 Processor Support

config CPU_SUBTYPE_SH7750
	bool "Support SH7750 processor"
	select CPU_SH4
	help
	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.

config CPU_SUBTYPE_SH7091
	bool "Support SH7091 processor"
	select CPU_SH4
	help
	  Select SH7091 if you have an SH-4 based Sega device (such as
	  the Dreamcast, Naomi, and Naomi 2).

config CPU_SUBTYPE_SH7750R
	bool "Support SH7750R processor"
	select CPU_SH4

config CPU_SUBTYPE_SH7750S
	bool "Support SH7750S processor"
	select CPU_SH4

config CPU_SUBTYPE_SH7751
	bool "Support SH7751 processor"
	select CPU_SH4
	help
	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
	  or if you have a HD6417751R CPU.

config CPU_SUBTYPE_SH7751R
	bool "Support SH7751R processor"
	select CPU_SH4

config CPU_SUBTYPE_SH7760
	bool "Support SH7760 processor"
	select CPU_SH4

config CPU_SUBTYPE_SH4_202
	bool "Support SH4-202 processor"
	select CPU_SH4

# SH-4A Processor Support

config CPU_SUBTYPE_SH7723
	bool "Support SH7723 processor"
	select CPU_SH4A
	select CPU_SHX2
	select ARCH_SHMOBILE
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_CMT
	help
	  Select SH7723 if you have an SH-MobileR2 CPU.

config CPU_SUBTYPE_SH7724
	bool "Support SH7724 processor"
	select CPU_SH4A
	select CPU_SHX2
	select ARCH_SHMOBILE
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_CMT
	help
	  Select SH7724 if you have an SH-MobileR2R CPU.

config CPU_SUBTYPE_SH7757
	bool "Support SH7757 processor"
	select CPU_SH4A
	select CPU_SHX2
	help
	  Select SH7757 if you have a SH4A SH7757 CPU.

config CPU_SUBTYPE_SH7763
	bool "Support SH7763 processor"
	select CPU_SH4A
	help
	  Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.

config CPU_SUBTYPE_SH7770
	bool "Support SH7770 processor"
	select CPU_SH4A

config CPU_SUBTYPE_SH7780
	bool "Support SH7780 processor"
	select CPU_SH4A

config CPU_SUBTYPE_SH7785
	bool "Support SH7785 processor"
	select CPU_SH4A
	select CPU_SHX2
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_NUMA

config CPU_SUBTYPE_SH7786
	bool "Support SH7786 processor"
	select CPU_SH4A
	select CPU_SHX3
	select CPU_HAS_PTEAEX
	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

config CPU_SUBTYPE_SHX3
	bool "Support SH-X3 processor"
	select CPU_SH4A
	select CPU_SHX3
	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
	select ARCH_REQUIRE_GPIOLIB

# SH4AL-DSP Processor Support

config CPU_SUBTYPE_SH7343
	bool "Support SH7343 processor"
	select CPU_SH4AL_DSP
	select ARCH_SHMOBILE
	select SYS_SUPPORTS_CMT

config CPU_SUBTYPE_SH7722
	bool "Support SH7722 processor"
	select CPU_SH4AL_DSP
	select CPU_SHX2
	select ARCH_SHMOBILE
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_NUMA
	select SYS_SUPPORTS_CMT

config CPU_SUBTYPE_SH7366
	bool "Support SH7366 processor"
	select CPU_SH4AL_DSP
	select CPU_SHX2
	select ARCH_SHMOBILE
	select ARCH_SPARSEMEM_ENABLE
	select SYS_SUPPORTS_NUMA
	select SYS_SUPPORTS_CMT

endchoice

endif

if SUPERH64

choice
	prompt "Processor sub-type selection"

# SH-5 Processor Support

config CPU_SUBTYPE_SH5_101
	bool "Support SH5-101 processor"
	select CPU_SH5

config CPU_SUBTYPE_SH5_103
	bool "Support SH5-103 processor"
	select CPU_SH5

endchoice

endif

source "arch/sh/mm/Kconfig"
 
source "arch/sh/Kconfig.cpu"

source "arch/sh/boards/Kconfig"

menu "Timer and clock configuration"

config SH_TIMER_TMU
	bool "TMU timer driver"
	depends on SYS_SUPPORTS_TMU
	default y
	help
	  This enables the build of the TMU timer driver.

config SH_TIMER_CMT
	bool "CMT timer driver"
	depends on SYS_SUPPORTS_CMT
	default y
	help
	  This enables build of the CMT timer driver.

config SH_TIMER_MTU2
	bool "MTU2 timer driver"
	depends on SYS_SUPPORTS_MTU2
	default y
	help
	  This enables build of the MTU2 timer driver.

config SH_PCLK_FREQ
	int "Peripheral clock frequency (in Hz)"
	depends on SH_CLK_CPG_LEGACY
	default "31250000" if CPU_SUBTYPE_SH7619
	default "33333333" if CPU_SUBTYPE_SH7770 || \
			      CPU_SUBTYPE_SH7760 || \
			      CPU_SUBTYPE_SH7705 || \
			      CPU_SUBTYPE_SH7203 || \
			      CPU_SUBTYPE_SH7206 || \
			      CPU_SUBTYPE_SH7263 || \
			      CPU_SUBTYPE_MXG
	default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
	default "66000000" if CPU_SUBTYPE_SH4_202
	default "50000000"
	help
	  This option is used to specify the peripheral clock frequency.
	  This is necessary for determining the reference clock value on
	  platforms lacking an RTC.

config SH_CLK_CPG
	def_bool y

config SH_CLK_CPG_LEGACY
	depends on SH_CLK_CPG
	def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
		      !CPU_SHX3 && !CPU_SUBTYPE_SH7757

config SH_CLK_MD
	int "CPU Mode Pin Setting"
	depends on CPU_SH2
	default 6 if CPU_SUBTYPE_SH7206
	default 5 if CPU_SUBTYPE_SH7619
	default 0
	help
	  MD2 - MD0 pin setting.

source "kernel/time/Kconfig"

endmenu

menu "CPU Frequency scaling"

source "drivers/cpufreq/Kconfig"

config SH_CPU_FREQ
	tristate "SuperH CPU Frequency driver"
	depends on CPU_FREQ
	select CPU_FREQ_TABLE
	help
	  This adds the cpufreq driver for SuperH. Any CPU that supports
	  clock rate rounding through the clock framework can use this
	  driver. While it will make the kernel slightly larger, this is
	  harmless for CPUs that don't support rate rounding. The driver
	  will also generate a notice in the boot log before disabling
	  itself if the CPU in question is not capable of rate rounding.

	  For details, take a look at <file:Documentation/cpu-freq>.

	  If unsure, say N.

endmenu

source "arch/sh/drivers/Kconfig"

endmenu

menu "Kernel features"

source kernel/Kconfig.hz

config KEXEC
	bool "kexec system call (EXPERIMENTAL)"
	depends on SUPERH32 && EXPERIMENTAL && MMU
	help
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
	  but it is independent of the system firmware.  And like a reboot
	  you can start any kernel with it, not just Linux.

	  The name comes from the similarity to the exec system call.

	  It is an ongoing process to be certain the hardware in a machine
	  is properly shutdown, so do not be surprised if this code does not
	  initially work for you.  It may help to enable device hotplugging
	  support.  As of this writing the exact hardware interface is
	  strongly in flux, so no good recommendation can be made.

config CRASH_DUMP
	bool "kernel crash dumps (EXPERIMENTAL)"
	depends on SUPERH32 && EXPERIMENTAL && BROKEN_ON_SMP
	help
	  Generate crash dump after being started by kexec.
	  This should be normally only set in special crash dump kernels
	  which are loaded in the main kernel with kexec-tools into
	  a specially reserved region and then later executed after
	  a crash by kdump/kexec. The crash dump kernel must be compiled
	  to a memory address not used by the main kernel using
	  MEMORY_START.

	  For more details see Documentation/kdump/kdump.txt

config KEXEC_JUMP
	bool "kexec jump (EXPERIMENTAL)"
	depends on SUPERH32 && KEXEC && HIBERNATION && EXPERIMENTAL
	help
	  Jump between original kernel and kexeced kernel and invoke
	  code via KEXEC

config SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
	depends on PROC_FS
	help
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl, it cannot be disabled and the task is only
	  allowed to execute a few safe syscalls defined by each seccomp
	  mode.

	  If unsure, say N.

config SMP
	bool "Symmetric multi-processing support"
	depends on SYS_SUPPORTS_SMP
	select USE_GENERIC_SMP_HELPERS
	---help---
	  This enables support for systems with more than one CPU. If you have
	  a system with only one CPU, like most personal computers, say N. If
	  you have a system with more than one CPU, say Y.

	  If you say N here, the kernel will run on single and multiprocessor
	  machines, but will use only one CPU of a multiprocessor machine. If
	  you say Y here, the kernel will run on many, but not all,
	  singleprocessor machines. On a singleprocessor machine, the kernel
	  will run faster if you say N here.

	  People using multiprocessor machines who say Y here should also say
	  Y to "Enhanced Real Time Clock Support", below.

	  See also <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO
	  available at <http://www.tldp.org/docs.html#howto>.

	  If you don't know what to do here, say N.

config NR_CPUS
	int "Maximum number of CPUs (2-32)"
	range 2 32
	depends on SMP
	default "4" if CPU_SUBTYPE_SHX3
	default "2"
	help
	  This allows you to specify the maximum number of CPUs which this
	  kernel will support.  The maximum supported value is 32 and the
	  minimum value which makes sense is 2.

	  This is purely to save memory - each supported CPU adds
	  approximately eight kilobytes to the kernel image.

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
	depends on SMP && HOTPLUG && EXPERIMENTAL
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

source "kernel/Kconfig.preempt"

config GUSA
	def_bool y
	depends on !SMP && SUPERH32
	help
	  This enables support for gUSA (general UserSpace Atomicity).
	  This is the default implementation for both UP and non-ll/sc
	  CPUs, and is used by the libc, amongst others.

	  For additional information, design information can be found 
	  in <http://lc.linux.or.jp/lc2002/papers/niibe0919p.pdf>.

	  This should only be disabled for special cases where alternate
	  atomicity implementations exist.

config GUSA_RB
	bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
	depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A)
	help
	  Enabling this option will allow the kernel to implement some
	  atomic operations using a software implementation of load-locked/
	  store-conditional (LLSC). On machines which do not have hardware
	  LLSC, this should be more efficient than the other alternative of
	  disabling interrupts around the atomic sequence.

config HW_PERF_EVENTS
	bool "Enable hardware performance counter support for perf events"
	depends on PERF_EVENTS && CPU_HAS_PMU
	default y
	help
	  Enable hardware performance counter support for perf events. If
	  disabled, perf events will use software events only.

source "drivers/sh/Kconfig"

endmenu

menu "Boot options"

config ZERO_PAGE_OFFSET
	hex
	default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
				SH_7751_SOLUTION_ENGINE
	default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
	default "0x00002000" if PAGE_SIZE_8KB
	default "0x00001000"
	help
	  This sets the default offset of zero page.

config BOOT_LINK_OFFSET
	hex
	default "0x00210000" if SH_SHMIN
	default "0x00400000" if SH_CAYMAN
	default "0x00810000" if SH_7780_SOLUTION_ENGINE
	default "0x009e0000" if SH_TITAN
	default "0x01800000" if SH_SDK7780
	default "0x02000000" if SH_EDOSK7760
	default "0x00800000"
	help
	  This option allows you to set the link address offset of the zImage.
	  This can be useful if you are on a board which has a small amount of
	  memory.

config ENTRY_OFFSET
	hex
	default "0x00001000" if PAGE_SIZE_4KB
	default "0x00002000" if PAGE_SIZE_8KB
	default "0x00004000" if PAGE_SIZE_16KB
	default "0x00010000" if PAGE_SIZE_64KB
	default "0x00000000"

config ROMIMAGE_MMCIF
	bool "Include MMCIF loader in romImage (EXPERIMENTAL)"
	depends on CPU_SUBTYPE_SH7724 && EXPERIMENTAL
	help
	  Say Y here to include experimental MMCIF loading code in
	  romImage. With this enabled it is possible to write the romImage
	  kernel image to an MMC card and boot the kernel straight from
	  the reset vector. At reset the processor Mask ROM will load the
	  first part of the romImage which in turn loads the rest the kernel
	  image to RAM using the MMCIF hardware block.

choice
	prompt "Kernel command line"
	optional
	default CMDLINE_OVERWRITE
	help
	  Setting this option allows the kernel command line arguments
	  to be set.

config CMDLINE_OVERWRITE
	bool "Overwrite bootloader kernel arguments"
	help
	  Given string will overwrite any arguments passed in by
	  a bootloader.

config CMDLINE_EXTEND
	bool "Extend bootloader kernel arguments"
	help
	  Given string will be concatenated with arguments passed in
	  by a bootloader.

endchoice

config CMDLINE
	string "Kernel command line arguments string"
	depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
	default "console=ttySC1,115200"

endmenu

menu "Bus options"

config SUPERHYWAY
	tristate "SuperHyway Bus support"
	depends on CPU_SUBTYPE_SH4_202

config MAPLE
	bool "Maple Bus support"
	depends on SH_DREAMCAST
	help
	 The Maple Bus is SEGA's serial communication bus for peripherals
	 on the Dreamcast. Without this bus support you won't be able to
	 get your Dreamcast keyboard etc to work, so most users
	 probably want to say 'Y' here, unless you are only using the
	 Dreamcast with a serial line terminal or a remote network
	 connection.

config PCI
	bool "PCI support"
	depends on SYS_SUPPORTS_PCI
	select PCI_DOMAINS
	help
	  Find out whether you have a PCI motherboard. PCI is the name of a
	  bus system, i.e. the way the CPU talks to the other stuff inside
	  your box. If you have PCI, say Y, otherwise N.

config PCI_DOMAINS
	bool

source "drivers/pci/pcie/Kconfig"

source "drivers/pci/Kconfig"

source "drivers/pcmcia/Kconfig"

source "drivers/pci/hotplug/Kconfig"

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

menu "Power management options (EXPERIMENTAL)"
depends on EXPERIMENTAL

source "kernel/power/Kconfig"

source "drivers/cpuidle/Kconfig"

endmenu

source "net/Kconfig"

source "drivers/Kconfig"

source "fs/Kconfig"

source "arch/sh/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"

menuconfig VIRTUALIZATION
	bool "Virtualization"
	default n
	---help---
	  Say Y here to get to see options for using your Linux host to run other
	  operating systems inside virtual machines (guests).
	  This option alone does not add any kernel code.

	  If you say N, all options in this submenu will be skipped and disabled.

if VIRTUALIZATION

source drivers/virtio/Kconfig

endif # VIRTUALIZATION

source "lib/Kconfig"
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/*
 *          mxser.c  -- MOXA Smartio/Industio family multiport serial driver.
 *
 *      Copyright (C) 1999-2006  Moxa Technologies (support@moxa.com).
 *	Copyright (C) 2006-2008  Jiri Slaby <jirislaby@gmail.com>
 *
 *      This code is loosely based on the 1.8 moxa driver which is based on
 *	Linux serial driver, written by Linus Torvalds, Theodore T'so and
 *	others.
 *
 *      This program is free software; you can redistribute it and/or modify
 *      it under the terms of the GNU General Public License as published by
 *      the Free Software Foundation; either version 2 of the License, or
 *      (at your option) any later version.
 *
 *	Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
 *	<alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
 *	www.moxa.com.
 *	- Fixed x86_64 cleanness
 */

#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/serial_reg.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/slab.h>

#include <asm/system.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

#include "mxser.h"

#define	MXSER_VERSION	"2.0.5"		/* 1.14 */
#define	MXSERMAJOR	 174

#define MXSER_BOARDS		4	/* Max. boards */
#define MXSER_PORTS_PER_BOARD	8	/* Max. ports per board */
#define MXSER_PORTS		(MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
#define MXSER_ISR_PASS_LIMIT	100

/*CheckIsMoxaMust return value*/
#define MOXA_OTHER_UART		0x00
#define MOXA_MUST_MU150_HWID	0x01
#define MOXA_MUST_MU860_HWID	0x02

#define WAKEUP_CHARS		256

#define UART_MCR_AFE		0x20
#define UART_LSR_SPECIAL	0x1E

#define PCI_DEVICE_ID_POS104UL	0x1044
#define PCI_DEVICE_ID_CB108	0x1080
#define PCI_DEVICE_ID_CP102UF	0x1023
#define PCI_DEVICE_ID_CP112UL	0x1120
#define PCI_DEVICE_ID_CB114	0x1142
#define PCI_DEVICE_ID_CP114UL	0x1143
#define PCI_DEVICE_ID_CB134I	0x1341
#define PCI_DEVICE_ID_CP138U	0x1380


#define C168_ASIC_ID    1
#define C104_ASIC_ID    2
#define C102_ASIC_ID	0xB
#define CI132_ASIC_ID	4
#define CI134_ASIC_ID	3
#define CI104J_ASIC_ID  5

#define MXSER_HIGHBAUD	1
#define MXSER_HAS2	2

/* This is only for PCI */
static const struct {
	int type;
	int tx_fifo;
	int rx_fifo;
	int xmit_fifo_size;
	int rx_high_water;
	int rx_trigger;
	int rx_low_water;
	long max_baud;
} Gpci_uart_info[] = {
	{MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
	{MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
	{MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
};
#define UART_INFO_NUM	ARRAY_SIZE(Gpci_uart_info)

struct mxser_cardinfo {
	char *name;
	unsigned int nports;
	unsigned int flags;
};

static const struct mxser_cardinfo mxser_cards[] = {
/* 0*/	{ "C168 series",	8, },
	{ "C104 series",	4, },
	{ "CI-104J series",	4, },
	{ "C168H/PCI series",	8, },
	{ "C104H/PCI series",	4, },
/* 5*/	{ "C102 series",	4, MXSER_HAS2 },	/* C102-ISA */
	{ "CI-132 series",	4, MXSER_HAS2 },
	{ "CI-134 series",	4, },
	{ "CP-132 series",	2, },
	{ "CP-114 series",	4, },
/*10*/	{ "CT-114 series",	4, },
	{ "CP-102 series",	2, MXSER_HIGHBAUD },
	{ "CP-104U series",	4, },
	{ "CP-168U series",	8, },
	{ "CP-132U series",	2, },
/*15*/	{ "CP-134U series",	4, },
	{ "CP-104JU series",	4, },
	{ "Moxa UC7000 Serial",	8, },		/* RC7000 */
	{ "CP-118U series",	8, },
	{ "CP-102UL series",	2, },
/*20*/	{ "CP-102U series",	2, },
	{ "CP-118EL series",	8, },
	{ "CP-168EL series",	8, },
	{ "CP-104EL series",	4, },
	{ "CB-108 series",	8, },
/*25*/	{ "CB-114 series",	4, },
	{ "CB-134I series",	4, },
	{ "CP-138U series",	8, },
	{ "POS-104UL series",	4, },
	{ "CP-114UL series",	4, },
/*30*/	{ "CP-102UF series",	2, },
	{ "CP-112UL series",	2, },
};

/* driver_data correspond to the lines in the structure above
   see also ISA probe function before you change something */
static struct pci_device_id mxser_pcibrds[] = {
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168),	.driver_data = 3 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104),	.driver_data = 4 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132),	.driver_data = 8 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114),	.driver_data = 9 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114),	.driver_data = 10 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102),	.driver_data = 11 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U),	.driver_data = 12 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U),	.driver_data = 13 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U),	.driver_data = 14 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U),	.driver_data = 15 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000),	.driver_data = 17 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U),	.driver_data = 18 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U),	.driver_data = 20 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108),	.driver_data = 24 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114),	.driver_data = 25 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I),	.driver_data = 26 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U),	.driver_data = 27 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL),	.driver_data = 28 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL),	.driver_data = 29 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF),	.driver_data = 30 },
	{ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL),	.driver_data = 31 },
	{ }
};
MODULE_DEVICE_TABLE(pci, mxser_pcibrds);

static unsigned long ioaddr[MXSER_BOARDS];
static int ttymajor = MXSERMAJOR;

/* Variables for insmod */

MODULE_AUTHOR("Casper Yang");
MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
module_param_array(ioaddr, ulong, NULL, 0);
MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
module_param(ttymajor, int, 0);
MODULE_LICENSE("GPL");

struct mxser_log {
	int tick;
	unsigned long rxcnt[MXSER_PORTS];
	unsigned long txcnt[MXSER_PORTS];
};

struct mxser_mon {
	unsigned long rxcnt;
	unsigned long txcnt;
	unsigned long up_rxcnt;
	unsigned long up_txcnt;
	int modem_status;
	unsigned char hold_reason;
};

struct mxser_mon_ext {
	unsigned long rx_cnt[32];
	unsigned long tx_cnt[32];
	unsigned long up_rxcnt[32];
	unsigned long up_txcnt[32];
	int modem_status[32];

	long baudrate[32];
	int databits[32];
	int stopbits[32];
	int parity[32];
	int flowctrl[32];
	int fifo[32];
	int iftype[32];
};

struct mxser_board;

struct mxser_port {
	struct tty_port port;
	struct mxser_board *board;

	unsigned long ioaddr;
	unsigned long opmode_ioaddr;
	int max_baud;

	int rx_high_water;
	int rx_trigger;		/* Rx fifo trigger level */
	int rx_low_water;
	int baud_base;		/* max. speed */
	int type;		/* UART type */

	int x_char;		/* xon/xoff character */
	int IER;		/* Interrupt Enable Register */
	int MCR;		/* Modem control register */

	unsigned char stop_rx;
	unsigned char ldisc_stop_rx;

	int custom_divisor;
	unsigned char err_shadow;

	struct async_icount icount; /* kernel counters for 4 input interrupts */
	int timeout;

	int read_status_mask;
	int ignore_status_mask;
	int xmit_fifo_size;
	int xmit_head;
	int xmit_tail;
	int xmit_cnt;

	struct ktermios normal_termios;

	struct mxser_mon mon_data;

	spinlock_t slock;
};

struct mxser_board {
	unsigned int idx;
	int irq;
	const struct mxser_cardinfo *info;
	unsigned long vector;
	unsigned long vector_mask;

	int chip_flag;
	int uart_type;

	struct mxser_port ports[MXSER_PORTS_PER_BOARD];
};

struct mxser_mstatus {
	tcflag_t cflag;
	int cts;
	int dsr;
	int ri;
	int dcd;
};

static struct mxser_board mxser_boards[MXSER_BOARDS];
static struct tty_driver *mxvar_sdriver;
static struct mxser_log mxvar_log;
static int mxser_set_baud_method[MXSER_PORTS + 1];

static void mxser_enable_must_enchance_mode(unsigned long baseio)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr |= MOXA_MUST_EFR_EFRB_ENABLE;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_disable_must_enchance_mode(unsigned long baseio)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_BANK_MASK;
	efr |= MOXA_MUST_EFR_BANK0;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(value, baseio + MOXA_MUST_XON1_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_BANK_MASK;
	efr |= MOXA_MUST_EFR_BANK0;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_set_must_fifo_value(struct mxser_port *info)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(info->ioaddr + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);

	efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_BANK_MASK;
	efr |= MOXA_MUST_EFR_BANK1;

	outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
	outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
	outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
	outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
	outb(oldlcr, info->ioaddr + UART_LCR);
}

static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_BANK_MASK;
	efr |= MOXA_MUST_EFR_BANK2;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_BANK_MASK;
	efr |= MOXA_MUST_EFR_BANK2;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	*pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_SF_MASK;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
	efr |= MOXA_MUST_EFR_SF_TX1;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
{
	u8 oldlcr;
	u8 efr;

	oldlcr = inb(baseio + UART_LCR);
	outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);

	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;

	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
	outb(oldlcr, baseio + UART_LCR);
}

static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
{
	u8 oldlcr;