arch/arm/plat-s5p/irq-eint.c


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/* linux/arch/arm/plat-s5p/irq-eint.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * S5P - IRQ EINT support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/gpio.h>

#include <asm/hardware/vic.h>

#include <plat/regs-irqtype.h>

#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/pm.h>

#include <plat/gpio-cfg.h>
#include <mach/regs-gpio.h>

static inline void s5p_irq_eint_mask(unsigned int irq)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
	mask |= eint_irq_to_bit(irq);
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
}

static void s5p_irq_eint_unmask(unsigned int irq)
{
	u32 mask;

	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
	mask &= ~(eint_irq_to_bit(irq));
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
}

static inline void s5p_irq_eint_ack(unsigned int irq)
{
	__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
}

static void s5p_irq_eint_maskack(unsigned int irq)
{
	/* compiler should in-line these */
	s5p_irq_eint_mask(irq);
	s5p_irq_eint_ack(irq);
}

static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
{
	int offs = EINT_OFFSET(irq);
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		newvalue = S5P_EXTINT_RISEEDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S5P_EXTINT_FALLEDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S5P_EXTINT_BOTHEDGE;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S5P_EXTINT_LOWLEV;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S5P_EXTINT_HILEV;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -EINVAL;
	}

	shift = (offs & 0x7) * 4;
	mask = 0x7 << shift;

	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));

	if ((0 <= offs) && (offs < 8))
		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);

	else if ((8 <= offs) && (offs < 16))
		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);

	else if ((16 <= offs) && (offs < 24))
		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);

	else if ((24 <= offs) && (offs < 32))
		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);

	else
		printk(KERN_ERR "No such irq number %d", offs);

	return 0;
}

static struct irq_chip s5p_irq_eint = {
	.name		= "s5p-eint",
	.mask		= s5p_irq_eint_mask,
	.unmask		= s5p_irq_eint_unmask,
	.mask_ack	= s5p_irq_eint_maskack,
	.ack		= s5p_irq_eint_ack,
	.set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.set_wake	= s3c_irqext_wake,
#endif
};

/* s5p_irq_demux_eint
 *
 * This function demuxes the IRQ from the group0 external interrupts,
 * from EINTs 16 to 31. It is designed to be inlined into the specific
 * handler s5p_irq_demux_eintX_Y.
 *
 * Each EINT pend/mask registers handle eight of them.
 */
static inline void s5p_irq_demux_eint(unsigned int start)
{
	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
	unsigned int irq;

	status &= ~mask;
	status &= 0xff;

	while (status) {
		irq = fls(status) - 1;
		generic_handle_irq(irq + start);
		status &= ~(1 << irq);
	}
}

static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
	s5p_irq_demux_eint(IRQ_EINT(16));
	s5p_irq_demux_eint(IRQ_EINT(24));
}

static inline void s5p_irq_vic_eint_mask(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);

	s5p_irq_eint_mask(irq);
	writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR);
}

static void s5p_irq_vic_eint_unmask(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);

	s5p_irq_eint_unmask(irq);
	writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE);
}

static inline void s5p_irq_vic_eint_ack(unsigned int irq)
{
	__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
}

static void s5p_irq_vic_eint_maskack(unsigned int irq)
{
	s5p_irq_vic_eint_mask(irq);
	s5p_irq_vic_eint_ack(irq);
}

static struct irq_chip s5p_irq_vic_eint = {
	.name		= "s5p_vic_eint",
	.mask		= s5p_irq_vic_eint_mask,
	.unmask		= s5p_irq_vic_eint_unmask,
	.mask_ack	= s5p_irq_vic_eint_maskack,
	.ack		= s5p_irq_vic_eint_ack,
	.set_type	= s5p_irq_eint_set_type,
#ifdef CONFIG_PM
	.set_wake	= s3c_irqext_wake,
#endif
};

int __init s5p_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
		set_irq_chip(irq, &s5p_irq_vic_eint);

	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
		set_irq_chip(irq, &s5p_irq_eint);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
	return 0;
}

arch_initcall(s5p_init_irq_eint);
/*
 * rocket_int.h --- internal header file for rocket.c
 *
 * Written by Theodore Ts'o, Copyright 1997.
 * Copyright 1997 Comtrol Corporation.  
 * 
 */

/*
 * Definition of the types in rcktpt_type
 */
#define ROCKET_TYPE_NORMAL	0
#define ROCKET_TYPE_MODEM	1
#define ROCKET_TYPE_MODEMII	2
#define ROCKET_TYPE_MODEMIII	3
#define ROCKET_TYPE_PC104       4

#include <asm/io.h>
#include <asm/byteorder.h>

typedef unsigned char Byte_t;
typedef unsigned int ByteIO_t;

typedef unsigned int Word_t;
typedef unsigned int WordIO_t;

typedef unsigned long DWord_t;
typedef unsigned int DWordIO_t;

/*
 * Note!  Normally the Linux I/O macros already take care of
 * byte-swapping the I/O instructions.  However, all accesses using
 * sOutDW aren't really 32-bit accesses, but should be handled in byte
 * order.  Hence the use of the cpu_to_le32() macro to byte-swap
 * things to no-op the byte swapping done by the big-endian outl()
 * instruction.
 */

#ifdef ROCKET_DEBUG_IO
static inline void sOutB(unsigned short port, unsigned char value)
{
#ifdef ROCKET_DEBUG_IO
	printk("sOutB(%x, %x)...", port, value);
#endif
	outb_p(value, port);
}

static inline void sOutW(unsigned short port, unsigned short value)
{
#ifdef ROCKET_DEBUG_IO
	printk("sOutW(%x, %x)...", port, value);
#endif
	outw_p(value, port);
}

static inline void sOutDW(unsigned short port, unsigned long value)
{
#ifdef ROCKET_DEBUG_IO
	printk("sOutDW(%x, %lx)...", port, value);
#endif
	outl_p(cpu_to_le32(value), port);
}

static inline unsigned char sInB(unsigned short port)
{
	return inb_p(port);
}

static inline unsigned short sInW(unsigned short port)
{
	return inw_p(port);
}

#else				/* !ROCKET_DEBUG_IO */
#define sOutB(a, b) outb_p(b, a)
#define sOutW(a, b) outw_p(b, a)
#define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
#define sInB(a) (inb_p(a))
#define sInW(a) (inw_p(a))
#endif				/* ROCKET_DEBUG_IO */

/* This is used to move arrays of bytes so byte swapping isn't appropriate. */
#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
#define sInStrW(port, addr, count) if (count) insw(port, addr, count)

#define CTL_SIZE 8
#define AIOP_CTL_SIZE 4
#define CHAN_AIOP_SIZE 8
#define MAX_PORTS_PER_AIOP 8
#define MAX_AIOPS_PER_BOARD 4
#define MAX_PORTS_PER_BOARD 32

/* Bus type ID */
#define	isISA	0
#define	isPCI	1
#define	isMC	2

/* Controller ID numbers */
#define CTLID_NULL  -1		/* no controller exists */
#define CTLID_0001  0x0001	/* controller release 1 */

/* AIOP ID numbers, identifies AIOP type implementing channel */
#define AIOPID_NULL -1		/* no AIOP or channel exists */
#define AIOPID_0001 0x0001	/* AIOP release 1 */

#define NULLDEV -1		/* identifies non-existant device */
#define NULLCTL -1		/* identifies non-existant controller */
#define NULLCTLPTR (CONTROLLER_T *)0	/* identifies non-existant controller */
#define NULLAIOP -1		/* identifies non-existant AIOP */
#define NULLCHAN -1		/* identifies non-existant channel */

/************************************************************************
 Global Register Offsets - Direct Access - Fixed values
************************************************************************/

#define _CMD_REG   0x38		/* Command Register            8    Write */
#define _INT_CHAN  0x39		/* Interrupt Channel Register  8    Read */
#define _INT_MASK  0x3A		/* Interrupt Mask Register     8    Read / Write */
#define _UNUSED    0x3B		/* Unused                      8 */
#define _INDX_ADDR 0x3C		/* Index Register Address      16   Write */
#define _INDX_DATA 0x3E		/* Index Register Data         8/16 Read / Write */

/************************************************************************
 Channel Register Offsets for 1st channel in AIOP - Direct Access
************************************************************************/
#define _TD0       0x00		/* Transmit Data               16   Write */
#define _RD0       0x00		/* Receive Data                16   Read */
#define _CHN_STAT0 0x20		/* Channel Status              8/16 Read / Write */
#define _FIFO_CNT0 0x10		/* Transmit/Receive FIFO Count 16   Read */
#define _INT_ID0   0x30		/* Interrupt Identification    8    Read */

/************************************************************************
 Tx Control Register Offsets - Indexed - External - Fixed
************************************************************************/
#define _TX_ENBLS  0x980	/* Tx Processor Enables Register 8 Read / Write */
#define _TXCMP1    0x988	/* Transmit Compare Value #1     8 Read / Write */
#define _TXCMP2    0x989	/* Transmit Compare Value #2     8 Read / Write */
#define _TXREP1B1  0x98A	/* Tx Replace Value #1 - Byte 1  8 Read / Write */
#define _TXREP1B2  0x98B	/* Tx Replace Value #1 - Byte 2  8 Read / Write */
#define _TXREP2    0x98C	/* Transmit Replace Value #2     8 Read / Write */

/************************************************************************
Memory Controller Register Offsets - Indexed - External - Fixed
************************************************************************/
#define _RX_FIFO    0x000	/* Rx FIFO */
#define _TX_FIFO    0x800	/* Tx FIFO */
#define _RXF_OUTP   0x990	/* Rx FIFO OUT pointer        16 Read / Write */
#define _RXF_INP    0x992	/* Rx FIFO IN pointer         16 Read / Write */
#define _TXF_OUTP   0x994	/* Tx FIFO OUT pointer        8  Read / Write */
#define _TXF_INP    0x995	/* Tx FIFO IN pointer         8  Read / Write */
#define _TXP_CNT    0x996	/* Tx Priority Count          8  Read / Write */
#define _TXP_PNTR   0x997	/* Tx Priority Pointer        8  Read / Write */

#define PRI_PEND    0x80	/* Priority data pending (bit7, Tx pri cnt) */
#define TXFIFO_SIZE 255		/* size of Tx FIFO */
#define RXFIFO_SIZE 1023	/* size of Rx FIFO */

/************************************************************************
Tx Priority Buffer - Indexed - External - Fixed
************************************************************************/
#define _TXP_BUF    0x9C0	/* Tx Priority Buffer  32  Bytes   Read / Write */
#define TXP_SIZE    0x20	/* 32 bytes */

/************************************************************************
Channel Register Offsets - Indexed - Internal - Fixed
************************************************************************/

#define _TX_CTRL    0xFF0	/* Transmit Control               16  Write */
#define _RX_CTRL    0xFF2	/* Receive Control                 8  Write */
#define _BAUD       0xFF4	/* Baud Rate                      16  Write */
#define _CLK_PRE    0xFF6	/* Clock Prescaler                 8  Write */

#define STMBREAK   0x08		/* BREAK */
#define STMFRAME   0x04		/* framing error */
#define STMRCVROVR 0x02		/* receiver over run error */
#define STMPARITY  0x01		/* parity error */
#define STMERROR   (STMBREAK | STMFRAME | STMPARITY)
#define STMBREAKH   0x800	/* BREAK */
#define STMFRAMEH   0x400	/* framing error */
#define STMRCVROVRH 0x200	/* receiver over run error */
#define STMPARITYH  0x100	/* parity error */
#define STMERRORH   (STMBREAKH | STMFRAMEH | STMPARITYH)

#define CTS_ACT   0x20		/* CTS input asserted */
#define DSR_ACT   0x10		/* DSR input asserted */
#define CD_ACT    0x08		/* CD input asserted */
#define TXFIFOMT  0x04		/* Tx FIFO is empty */
#define TXSHRMT   0x02		/* Tx shift register is empty */
#define RDA       0x01		/* Rx data available */
#define DRAINED (TXFIFOMT | TXSHRMT)	/* indicates Tx is drained */

#define STATMODE  0x8000	/* status mode enable bit */
#define RXFOVERFL 0x2000	/* receive FIFO overflow */
#define RX2MATCH  0x1000	/* receive compare byte 2 match */
#define RX1MATCH  0x0800	/* receive compare byte 1 match */
#define RXBREAK   0x0400	/* received BREAK */
#define RXFRAME   0x0200	/* received framing error */
#define RXPARITY  0x0100	/* received parity error */
#define STATERROR (RXBREAK | RXFRAME | RXPARITY)

#define CTSFC_EN  0x80		/* CTS flow control enable bit */
#define RTSTOG_EN 0x40		/* RTS toggle enable bit */
#define TXINT_EN  0x10		/* transmit interrupt enable */
#define STOP2     0x08		/* enable 2 stop bits (0 = 1 stop) */
#define PARITY_EN 0x04		/* enable parity (0 = no parity) */
#define EVEN_PAR  0x02		/* even parity (0 = odd parity) */
#define DATA8BIT  0x01		/* 8 bit data (0 = 7 bit data) */

#define SETBREAK  0x10		/* send break condition (must clear) */
#define LOCALLOOP 0x08		/* local loopback set for test */
#define SET_DTR   0x04		/* assert DTR */
#define SET_RTS   0x02		/* assert RTS */
#define TX_ENABLE 0x01		/* enable transmitter */

#define RTSFC_EN  0x40		/* RTS flow control enable */
#define RXPROC_EN 0x20		/* receive processor enable */
#define TRIG_NO   0x00		/* Rx FIFO trigger level 0 (no trigger) */
#define TRIG_1    0x08		/* trigger level 1 char */
#define TRIG_1_2  0x10		/* trigger level 1/2 */
#define TRIG_7_8  0x18		/* trigger level 7/8 */
#define TRIG_MASK 0x18		/* trigger level mask */
#define SRCINT_EN 0x04		/* special Rx condition interrupt enable */
#define RXINT_EN  0x02		/* Rx interrupt enable */
#define MCINT_EN  0x01		/* modem change interrupt enable */

#define RXF_TRIG  0x20		/* Rx FIFO trigger level interrupt */
#define TXFIFO_MT 0x10		/* Tx FIFO empty interrupt */
#define SRC_INT   0x08		/* special receive condition interrupt */
#define DELTA_CD  0x04		/* CD change interrupt */
#define DELTA_CTS 0x02		/* CTS change interrupt */
#define DELTA_DSR 0x01		/* DSR change interrupt */

#define REP1W2_EN 0x10		/* replace byte 1 with 2 bytes enable */
#define IGN2_EN   0x08		/* ignore byte 2 enable */
#define IGN1_EN   0x04		/* ignore byte 1 enable */
#define COMP2_EN  0x02		/* compare byte 2 enable */
#define COMP1_EN  0x01		/* compare byte 1 enable */

#define RESET_ALL 0x80		/* reset AIOP (all channels) */
#define TXOVERIDE 0x40		/* Transmit software off override */
#define RESETUART 0x20		/* reset channel's UART */
#define RESTXFCNT 0x10		/* reset channel's Tx FIFO count register */
#define RESRXFCNT 0x08		/* reset channel's Rx FIFO count register */

#define INTSTAT0  0x01		/* AIOP 0 interrupt status */
#define INTSTAT1  0x02		/* AIOP 1 interrupt status */
#define INTSTAT2  0x04		/* AIOP 2 interrupt status */
#define INTSTAT3  0x08		/* AIOP 3 interrupt status */

#define INTR_EN   0x08		/* allow interrupts to host */
#define INT_STROB 0x04		/* strobe and clear interrupt line (EOI) */

/**************************************************************************
 MUDBAC remapped for PCI
**************************************************************************/

#define _CFG_INT_PCI  0x40
#define _PCI_INT_FUNC 0x3A

#define PCI_STROB 0x2000	/* bit 13 of int aiop register */
#define INTR_EN_PCI   0x0010	/* allow interrupts to host */

/*
 * Definitions for Universal PCI board registers
 */
#define _PCI_9030_INT_CTRL	0x4c          /* Offsets from BAR1 */
#define _PCI_9030_GPIO_CTRL	0x54
#define PCI_INT_CTRL_AIOP	0x0001
#define PCI_GPIO_CTRL_8PORT	0x4000
#define _PCI_9030_RING_IND	0xc0          /* Offsets from BAR1 */

#define CHAN3_EN  0x08		/* enable AIOP 3 */
#define CHAN2_EN  0x04		/* enable AIOP 2 */
#define CHAN1_EN  0x02		/* enable AIOP 1 */
#define CHAN0_EN  0x01		/* enable AIOP 0 */
#define FREQ_DIS  0x00
#define FREQ_274HZ 0x60
#define FREQ_137HZ 0x50
#define FREQ_69HZ  0x40
#define FREQ_34HZ  0x30
#define FREQ_17HZ  0x20
#define FREQ_9HZ   0x10
#define PERIODIC_ONLY 0x80	/* only PERIODIC interrupt */

#define CHANINT_EN 0x0100	/* flags to enable/disable channel ints */

#define RDATASIZE 72
#define RREGDATASIZE 52

/*
 * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
 */
#define AIOP_INTR_BIT_0		0x0001
#define AIOP_INTR_BIT_1		0x0002
#define AIOP_INTR_BIT_2		0x0004
#define AIOP_INTR_BIT_3		0x0008

#define AIOP_INTR_BITS ( \
	AIOP_INTR_BIT_0 \
	| AIOP_INTR_BIT_1 \
	| AIOP_INTR_BIT_2 \
	| AIOP_INTR_BIT_3)

#define UPCI_AIOP_INTR_BIT_0	0x0004
#define UPCI_AIOP_INTR_BIT_1	0x0020
#define UPCI_AIOP_INTR_BIT_2	0x0100
#define UPCI_AIOP_INTR_BIT_3	0x0800

#define UPCI_AIOP_INTR_BITS ( \
	UPCI_AIOP_INTR_BIT_0 \
	| UPCI_AIOP_INTR_BIT_1 \
	| UPCI_AIOP_INTR_BIT_2 \
	| UPCI_AIOP_INTR_BIT_3)

/* Controller level information structure */
typedef struct {
	int CtlID;
	int CtlNum;
	int BusType;
	int boardType;
	int isUPCI;
	WordIO_t PCIIO;
	WordIO_t PCIIO2;
	ByteIO_t MBaseIO;
	ByteIO_t MReg1IO;
	ByteIO_t MReg2IO;
	ByteIO_t MReg3IO;
	Byte_t MReg2;
	Byte_t MReg3;
	int NumAiop;
	int AltChanRingIndicator;
	ByteIO_t UPCIRingInd;
	WordIO_t AiopIO[AIOP_CTL_SIZE];
	ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
	int AiopID[AIOP_CTL_SIZE];
	int AiopNumChan[AIOP_CTL_SIZE];
	Word_t *AiopIntrBits;
} CONTROLLER_T;

typedef CONTROLLER_T CONTROLLER_t;

/* Channel level information structure */
typedef struct {
	CONTROLLER_T *CtlP;
	int AiopNum;
	int ChanID;
	int ChanNum;
	int rtsToggle;

	ByteIO_t Cmd;
	ByteIO_t IntChan;
	ByteIO_t IntMask;
	DWordIO_t IndexAddr;
	WordIO_t IndexData;

	WordIO_t TxRxData;
	WordIO_t ChanStat;
	WordIO_t TxRxCount;
	ByteIO_t IntID;

	Word_t TxFIFO;
	Word_t TxFIFOPtrs;
	Word_t RxFIFO;
	Word_t RxFIFOPtrs;
	Word_t TxPrioCnt;
	Word_t TxPrioPtr;
	Word_t TxPrioBuf;

	Byte_t R[RREGDATASIZE];

	Byte_t BaudDiv[4];
	Byte_t TxControl[4];
	Byte_t RxControl[4];
	Byte_t TxEnables[4];
	Byte_t TxCompare[4];
	Byte_t TxReplace1[4];
	Byte_t TxReplace2[4];
} CHANNEL_T;

typedef CHANNEL_T CHANNEL_t;
typedef CHANNEL_T *CHANPTR_T;

#define InterfaceModeRS232  0x00
#define InterfaceModeRS422  0x08
#define InterfaceModeRS485  0x10
#define InterfaceModeRS232T 0x18

/***************************************************************************
Function: sClrBreak
Purpose:  Stop sending a transmit BREAK signal
Call:     sClrBreak(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrBreak(ChP) \
do { \
   (ChP)->TxControl[3] &= ~SETBREAK; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sClrDTR
Purpose:  Clr the DTR output
Call:     sClrDTR(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrDTR(ChP) \
do { \
   (ChP)->TxControl[3] &= ~SET_DTR; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sClrRTS
Purpose:  Clr the RTS output
Call:     sClrRTS(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrRTS(ChP) \
do { \
   if ((ChP)->rtsToggle) break; \
   (ChP)->TxControl[3] &= ~SET_RTS; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sClrTxXOFF
Purpose:  Clear any existing transmit software flow control off condition
Call:     sClrTxXOFF(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sClrTxXOFF(ChP) \
do { \
   sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
   sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
} while (0)

/***************************************************************************
Function: sCtlNumToCtlPtr
Purpose:  Convert a controller number to controller structure pointer
Call:     sCtlNumToCtlPtr(CtlNum)
          int CtlNum; Controller number
Return:   CONTROLLER_T *: Ptr to controller structure
*/
#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]

/***************************************************************************
Function: sControllerEOI
Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
Call:     sControllerEOI(CtlP)
          CONTROLLER_T *CtlP; Ptr to controller structure
*/
#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)

/***************************************************************************
Function: sPCIControllerEOI
Purpose:  Strobe the PCI End Of Interrupt bit.
          For the UPCI boards, toggle the AIOP interrupt enable bit
	  (this was taken from the Windows driver).
Call:     sPCIControllerEOI(CtlP)
          CONTROLLER_T *CtlP; Ptr to controller structure
*/
#define sPCIControllerEOI(CTLP) \
do { \
    if ((CTLP)->isUPCI) { \
	Word_t w = sInW((CTLP)->PCIIO); \
	sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
	sOutW((CTLP)->PCIIO, w); \
    } \
    else { \
	sOutW((CTLP)->PCIIO, PCI_STROB); \
    } \
} while (0)

/***************************************************************************
Function: sDisAiop
Purpose:  Disable I/O access to an AIOP
Call:     sDisAiop(CltP)
          CONTROLLER_T *CtlP; Ptr to controller structure
          int AiopNum; Number of AIOP on controller
*/
#define sDisAiop(CTLP,AIOPNUM) \
do { \
   (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
   sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
} while (0)

/***************************************************************************
Function: sDisCTSFlowCtl
Purpose:  Disable output flow control using CTS
Call:     sDisCTSFlowCtl(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisCTSFlowCtl(ChP) \
do { \
   (ChP)->TxControl[2] &= ~CTSFC_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sDisIXANY
Purpose:  Disable IXANY Software Flow Control
Call:     sDisIXANY(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisIXANY(ChP) \
do { \
   (ChP)->R[0x0e] = 0x86; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
} while (0)

/***************************************************************************
Function: DisParity
Purpose:  Disable parity
Call:     sDisParity(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: Function sSetParity() can be used in place of functions sEnParity(),
          sDisParity(), sSetOddParity(), and sSetEvenParity().
*/
#define sDisParity(ChP) \
do { \
   (ChP)->TxControl[2] &= ~PARITY_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sDisRTSToggle
Purpose:  Disable RTS toggle
Call:     sDisRTSToggle(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisRTSToggle(ChP) \
do { \
   (ChP)->TxControl[2] &= ~RTSTOG_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
   (ChP)->rtsToggle = 0; \
} while (0)

/***************************************************************************
Function: sDisRxFIFO
Purpose:  Disable Rx FIFO
Call:     sDisRxFIFO(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisRxFIFO(ChP) \
do { \
   (ChP)->R[0x32] = 0x0a; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
} while (0)

/***************************************************************************
Function: sDisRxStatusMode
Purpose:  Disable the Rx status mode
Call:     sDisRxStatusMode(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: This takes the channel out of the receive status mode.  All
          subsequent reads of receive data using sReadRxWord() will return
          two data bytes.
*/
#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)

/***************************************************************************
Function: sDisTransmit
Purpose:  Disable transmit
Call:     sDisTransmit(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
          This disables movement of Tx data from the Tx FIFO into the 1 byte
          Tx buffer.  Therefore there could be up to a 2 byte latency
          between the time sDisTransmit() is called and the transmit buffer
          and transmit shift register going completely empty.
*/
#define sDisTransmit(ChP) \
do { \
   (ChP)->TxControl[3] &= ~TX_ENABLE; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sDisTxSoftFlowCtl
Purpose:  Disable Tx Software Flow Control
Call:     sDisTxSoftFlowCtl(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sDisTxSoftFlowCtl(ChP) \
do { \
   (ChP)->R[0x06] = 0x8a; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
} while (0)

/***************************************************************************
Function: sEnAiop
Purpose:  Enable I/O access to an AIOP
Call:     sEnAiop(CltP)
          CONTROLLER_T *CtlP; Ptr to controller structure
          int AiopNum; Number of AIOP on controller
*/
#define sEnAiop(CTLP,AIOPNUM) \
do { \
   (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
   sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
} while (0)

/***************************************************************************
Function: sEnCTSFlowCtl
Purpose:  Enable output flow control using CTS
Call:     sEnCTSFlowCtl(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnCTSFlowCtl(ChP) \
do { \
   (ChP)->TxControl[2] |= CTSFC_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sEnIXANY
Purpose:  Enable IXANY Software Flow Control
Call:     sEnIXANY(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnIXANY(ChP) \
do { \
   (ChP)->R[0x0e] = 0x21; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
} while (0)

/***************************************************************************
Function: EnParity
Purpose:  Enable parity
Call:     sEnParity(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: Function sSetParity() can be used in place of functions sEnParity(),
          sDisParity(), sSetOddParity(), and sSetEvenParity().

Warnings: Before enabling parity odd or even parity should be chosen using
          functions sSetOddParity() or sSetEvenParity().
*/
#define sEnParity(ChP) \
do { \
   (ChP)->TxControl[2] |= PARITY_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sEnRTSToggle
Purpose:  Enable RTS toggle
Call:     sEnRTSToggle(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: This function will disable RTS flow control and clear the RTS
          line to allow operation of RTS toggle.
*/
#define sEnRTSToggle(ChP) \
do { \
   (ChP)->RxControl[2] &= ~RTSFC_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
   (ChP)->TxControl[2] |= RTSTOG_EN; \
   (ChP)->TxControl[3] &= ~SET_RTS; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
   (ChP)->rtsToggle = 1; \
} while (0)

/***************************************************************************
Function: sEnRxFIFO
Purpose:  Enable Rx FIFO
Call:     sEnRxFIFO(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnRxFIFO(ChP) \
do { \
   (ChP)->R[0x32] = 0x08; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
} while (0)

/***************************************************************************
Function: sEnRxProcessor
Purpose:  Enable the receive processor
Call:     sEnRxProcessor(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: This function is used to start the receive processor.  When
          the channel is in the reset state the receive processor is not
          running.  This is done to prevent the receive processor from
          executing invalid microcode instructions prior to the
          downloading of the microcode.

Warnings: This function must be called after valid microcode has been
          downloaded to the AIOP, and it must not be called before the
          microcode has been downloaded.
*/
#define sEnRxProcessor(ChP) \
do { \
   (ChP)->RxControl[2] |= RXPROC_EN; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
} while (0)

/***************************************************************************
Function: sEnRxStatusMode
Purpose:  Enable the Rx status mode
Call:     sEnRxStatusMode(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Comments: This places the channel in the receive status mode.  All subsequent
          reads of receive data using sReadRxWord() will return a data byte
          in the low word and a status byte in the high word.

*/
#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)

/***************************************************************************
Function: sEnTransmit
Purpose:  Enable transmit
Call:     sEnTransmit(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnTransmit(ChP) \
do { \
   (ChP)->TxControl[3] |= TX_ENABLE; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
} while (0)

/***************************************************************************
Function: sEnTxSoftFlowCtl
Purpose:  Enable Tx Software Flow Control
Call:     sEnTxSoftFlowCtl(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
*/
#define sEnTxSoftFlowCtl(ChP) \
do { \
   (ChP)->R[0x06] = 0xc5; \
   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
} while (0)

/***************************************************************************
Function: sGetAiopIntStatus
Purpose:  Get the AIOP interrupt status
Call:     sGetAiopIntStatus(CtlP,AiopNum)
          CONTROLLER_T *CtlP; Ptr to controller structure
          int AiopNum; AIOP number
Return:   Byte_t: The AIOP interrupt status.  Bits 0 through 7
                         represent channels 0 through 7 respectively.  If a
                         bit is set that channel is interrupting.
*/
#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])

/***************************************************************************
Function: sGetAiopNumChan
Purpose:  Get the number of channels supported by an AIOP
Call:     sGetAiopNumChan(CtlP,AiopNum)
          CONTROLLER_T *CtlP; Ptr to controller structure
          int AiopNum; AIOP number
Return:   int: The number of channels supported by the AIOP
*/
#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]

/***************************************************************************
Function: sGetChanIntID
Purpose:  Get a channel's interrupt identification byte
Call:     sGetChanIntID(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   Byte_t: The channel interrupt ID.  Can be any
             combination of the following flags:
                RXF_TRIG:     Rx FIFO trigger level interrupt
                TXFIFO_MT:    Tx FIFO empty interrupt
                SRC_INT:      Special receive condition interrupt
                DELTA_CD:     CD change interrupt
                DELTA_CTS:    CTS change interrupt
                DELTA_DSR:    DSR change interrupt
*/
#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))

/***************************************************************************
Function: sGetChanNum
Purpose:  Get the number of a channel within an AIOP
Call:     sGetChanNum(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   int: Channel number within AIOP, or NULLCHAN if channel does
               not exist.
*/
#define sGetChanNum(ChP) (ChP)->ChanNum

/***************************************************************************
Function: sGetChanStatus
Purpose:  Get the channel status
Call:     sGetChanStatus(ChP)
          CHANNEL_T *ChP; Ptr to channel structure
Return:   Word_t: The channel status.  Can be any combination of
             the following flags:
                LOW BYTE FLAGS
                CTS_ACT:      CTS input asserted
                DSR_ACT:      DSR input asserted
                CD_ACT:       CD input asserted
                TXFIFOMT:     Tx FIFO is empty
                TXSHRMT:      Tx shift register is empty
                RDA:          Rx data available

                HIGH BYTE FLAGS
                STATMODE:     status mode enable bit
                RXFOVERFL:    receive FIFO overflow
                RX2MATCH:     receive compare byte 2 match
                RX1MATCH:     receive compare byte 1 match
                RXBREAK:      received BREAK
                RXFRAME:      received framing error
                RXPARITY:     received parity error
Warnings: This function will clear the high byte flags in the Channel
          Status Register.
*/
#define sGetChanStatus(ChP) sInW((ChP)->ChanStat)

/***************************************************************************
Function: sGetChanStatusLo
Purpose:  Get the low byte only of the channel status
Call:     sGetChanStatusLo(ChP)
          CHANNEL_T *ChP; Ptr to channel structure