blob: 3bc0a216df97e2f5e602820cbac67cea356cac49 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
|
/* arch/arm/mach-s3c2410/include/mach/dma.h
*
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* DMA Register definitions */
#define S3C2410_DMA_DISRC (0x00)
#define S3C2410_DMA_DISRCC (0x04)
#define S3C2410_DMA_DIDST (0x08)
#define S3C2410_DMA_DIDSTC (0x0C)
#define S3C2410_DMA_DCON (0x10)
#define S3C2410_DMA_DSTAT (0x14)
#define S3C2410_DMA_DCSRC (0x18)
#define S3C2410_DMA_DCDST (0x1C)
#define S3C2410_DMA_DMASKTRIG (0x20)
#define S3C2412_DMA_DMAREQSEL (0x24)
#define S3C2443_DMA_DMAREQSEL (0x24)
#define S3C2410_DISRCC_INC (1<<0)
#define S3C2410_DISRCC_APB (1<<1)
#define S3C2410_DMASKTRIG_STOP (1<<2)
#define S3C2410_DMASKTRIG_ON (1<<1)
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
#define S3C2410_DCON_DEMAND (0<<31)
#define S3C2410_DCON_HANDSHAKE (1<<31)
#define S3C2410_DCON_SYNC_PCLK (0<<30)
#define S3C2410_DCON_SYNC_HCLK (1<<30)
#define S3C2410_DCON_INTREQ (1<<29)
#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
#define S3C2410_DCON_CH0_UART0 (1<<24)
#define S3C2410_DCON_CH0_SDI (2<<24)
#define S3C2410_DCON_CH0_TIMER (3<<24)
#define S3C2410_DCON_CH0_USBEP1 (4<<24)
#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
#define S3C2410_DCON_CH1_UART1 (1<<24)
#define S3C2410_DCON_CH1_I2SSDI (2<<24)
#define S3C2410_DCON_CH1_SPI (3<<24)
#define S3C2410_DCON_CH1_USBEP2 (4<<24)
#define S3C2410_DCON_CH2_I2SSDO (0<<24)
#define S3C2410_DCON_CH2_I2SSDI (1<<24)
#define S3C2410_DCON_CH2_SDI (2<<24)
#define S3C2410_DCON_CH2_TIMER (3<<24)
#define S3C2410_DCON_CH2_USBEP3 (4<<24)
#define S3C2410_DCON_CH3_UART2 (0<<24)
#define S3C2410_DCON_CH3_SDI (1<<24)
#define S3C2410_DCON_CH3_SPI (2<<24)
#define S3C2410_DCON_CH3_TIMER (3<<24)
#define S3C2410_DCON_CH3_USBEP4 (4<<24)
#define S3C2410_DCON_SRCSHIFT (24)
#define S3C2410_DCON_SRCMASK (7<<24)
#define S3C2410_DCON_BYTE (0<<20)
#define S3C2410_DCON_HALFWORD (1<<20)
#define S3C2410_DCON_WORD (2<<20)
#define S3C2410_DCON_AUTORELOAD (0<<22)
#define S3C2410_DCON_NORELOAD (1<<22)
#define S3C2410_DCON_HWTRIG (1<<23)
#ifdef CONFIG_CPU_S3C2440
#define S3C2440_DIDSTC_CHKINT (1<<2)
#define S3C2440_DCON_CH0_I2SSDO (5<<24)
#define S3C2440_DCON_CH0_PCMIN (6<<24)
#define S3C2440_DCON_CH1_PCMOUT (5<<24)
#define S3C2440_DCON_CH1_SDI (6<<24)
#define S3C2440_DCON_CH2_PCMIN (5<<24)
#define S3C2440_DCON_CH2_MICIN (6<<24)
#define S3C2440_DCON_CH3_MICIN (5<<24)
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
#endif
#ifdef CONFIG_CPU_S3C2412
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
#define S3C2412_DMAREQSEL_HW (1)
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
#endif
#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
#define S3C2443_DMAREQSEL_HW (1)
#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
|
