blob: d047dbc28d61ece8e763833ba6e1c76af9bfc2a0 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
/*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
clocks {
/*
* Fixed 30MHz oscillator input to SoC
*/
CLK_SYSIN: CLK_SYSIN {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: arm_periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
CLKS_GMAC0_PHY: clockgenA1@7 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLKS_GMAC0_PHY";
};
CLKS_ETH1_PHY: clockgenA0@7 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLKS_ETH1_PHY";
};
};
};
|
