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/span> #define SONIC_RCR_FAER 0x0004 #define SONIC_RCR_LBK 0x0002 #define SONIC_RCR_PRX 0x0001 #define SONIC_RCR_LB_OFF 0 #define SONIC_RCR_LB_MAC SONIC_RCR_LB0 #define SONIC_RCR_LB_ENDEC SONIC_RCR_LB1 #define SONIC_RCR_LB_TRANS (SONIC_RCR_LB0 | SONIC_RCR_LB1) /* default RCR setup */ #define SONIC_RCR_DEFAULT (SONIC_RCR_BRD) /* * SONIC Transmit Control register bits */ #define SONIC_TCR_PINTR 0x8000 #define SONIC_TCR_POWC 0x4000 #define SONIC_TCR_CRCI 0x2000 #define SONIC_TCR_EXDIS 0x1000 #define SONIC_TCR_EXD 0x0400 #define SONIC_TCR_DEF 0x0200 #define SONIC_TCR_NCRS 0x0100 #define SONIC_TCR_CRLS 0x0080 #define SONIC_TCR_EXC 0x0040 #define SONIC_TCR_PMB 0x0008 #define SONIC_TCR_FU 0x0004 #define SONIC_TCR_BCM 0x0002 #define SONIC_TCR_PTX 0x0001 #define SONIC_TCR_DEFAULT 0x0000 /* * Constants for the SONIC_INTERRUPT_MASK and * SONIC_INTERRUPT_STATUS registers. */ #define SONIC_INT_BR 0x4000 #define SONIC_INT_HBL 0x2000 #define SONIC_INT_LCD 0x1000 #define SONIC_INT_PINT 0x0800 #define SONIC_INT_PKTRX 0x0400 #define SONIC_INT_TXDN 0x0200 #define SONIC_INT_TXER 0x0100 #define SONIC_INT_TC 0x0080 #define SONIC_INT_RDE 0x0040 #define SONIC_INT_RBE 0x0020 #define SONIC_INT_RBAE 0x0010 #define SONIC_INT_CRC 0x0008 #define SONIC_INT_FAE 0x0004 #define SONIC_INT_MP 0x0002 #define SONIC_INT_RFO 0x0001 /* * The interrupts we allow. */ #define SONIC_IMR_DEFAULT ( SONIC_INT_BR | \ SONIC_INT_LCD | \ SONIC_INT_RFO | \ SONIC_INT_PKTRX | \ SONIC_INT_TXDN | \ SONIC_INT_TXER | \ SONIC_INT_RDE | \ SONIC_INT_RBAE | \ SONIC_INT_CRC | \ SONIC_INT_FAE | \ SONIC_INT_MP) #define SONIC_EOL 0x0001 #define CAM_DESCRIPTORS 16 /* Offsets in the various DMA buffers accessed by the SONIC */ #define SONIC_BITMODE16 0 #define SONIC_BITMODE32 1 #define SONIC_BUS_SCALE(bitmode) ((bitmode) ? 4 : 2) /* Note! These are all measured in bus-size units, so use SONIC_BUS_SCALE */ #define SIZEOF_SONIC_RR 4 #define SONIC_RR_BUFADR_L 0 #define SONIC_RR_BUFADR_H 1 #define SONIC_RR_BUFSIZE_L 2 #define SONIC_RR_BUFSIZE_H 3 #define SIZEOF_SONIC_RD 7 #define SONIC_RD_STATUS 0 #define SONIC_RD_PKTLEN 1 #define SONIC_RD_PKTPTR_L 2 #define SONIC_RD_PKTPTR_H 3 #define SONIC_RD_SEQNO 4 #define SONIC_RD_LINK 5 #define SONIC_RD_IN_USE 6 #define SIZEOF_SONIC_TD 8 #define SONIC_TD_STATUS 0 #define SONIC_TD_CONFIG 1 #define SONIC_TD_PKTSIZE 2 #define SONIC_TD_FRAG_COUNT 3 #define SONIC_TD_FRAG_PTR_L 4 #define SONIC_TD_FRAG_PTR_H 5 #define SONIC_TD_FRAG_SIZE 6 #define SONIC_TD_LINK 7 #define SIZEOF_SONIC_CD 4 #define SONIC_CD_ENTRY_POINTER 0 #define SONIC_CD_CAP0 1 #define SONIC_CD_CAP1 2 #define SONIC_CD_CAP2 3 #define SIZEOF_SONIC_CDA ((CAM_DESCRIPTORS * SIZEOF_SONIC_CD) + 1) #define SONIC_CDA_CAM_ENABLE (CAM_DESCRIPTORS * SIZEOF_SONIC_CD) /* * Some tunables for the buffer areas. Power of 2 is required * the current driver uses one receive buffer for each descriptor. * * MSch: use more buffer space for the slow m68k Macs! */ #define SONIC_NUM_RRS 16 /* number of receive resources */ #define SONIC_NUM_RDS SONIC_NUM_RRS /* number of receive descriptors */ #define SONIC_NUM_TDS 16 /* number of transmit descriptors */ #define SONIC_RDS_MASK (SONIC_NUM_RDS-1) #define SONIC_TDS_MASK (SONIC_NUM_TDS-1) #define SONIC_RBSIZE 1520 /* size of one resource buffer */ /* Again, measured in bus size units! */ #define SIZEOF_SONIC_DESC (SIZEOF_SONIC_CDA \ + (SIZEOF_SONIC_TD * SONIC_NUM_TDS) \ + (SIZEOF_SONIC_RD * SONIC_NUM_RDS) \ + (SIZEOF_SONIC_RR * SONIC_NUM_RRS)) /* Information that need to be kept for each board. */ struct sonic_local { /* Bus size. 0 == 16 bits, 1 == 32 bits. */ int dma_bitmode; /* Register offset within the longword (independent of endianness, and varies from one type of Macintosh SONIC to another (Aarrgh)) */ int reg_offset; void *descriptors; /* Crud. These areas have to be within the same 64K. Therefore we allocate a desriptors page, and point these to places within it. */ void *cda; /* CAM descriptor area */ void *tda; /* Transmit descriptor area */ void *rra; /* Receive resource area */ void *rda; /* Receive descriptor area */ struct sk_buff* volatile rx_skb[SONIC_NUM_RRS]; /* packets to be received */ struct sk_buff* volatile tx_skb[SONIC_NUM_TDS]; /* packets to be transmitted */ unsigned int tx_len[SONIC_NUM_TDS]; /* lengths of tx DMA mappings */ /* Logical DMA addresses on MIPS, bus addresses on m68k * (so "laddr" is a bit misleading) */ dma_addr_t descriptors_laddr; u32 cda_laddr; /* logical DMA address of CDA */ u32 tda_laddr; /* logical DMA address of TDA */ u32 rra_laddr; /* logical DMA address of RRA */ u32 rda_laddr; /* logical DMA address of RDA */ dma_addr_t rx_laddr[SONIC_NUM_RRS]; /* logical DMA addresses of rx skbuffs */ dma_addr_t tx_laddr[SONIC_NUM_TDS]; /* logical DMA addresses of tx skbuffs */ unsigned int rra_end; unsigned int cur_rwp; unsigned int cur_rx; unsigned int cur_tx; /* first unacked transmit packet */ unsigned int eol_rx; unsigned int eol_tx; /* last unacked transmit packet */