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n class="hl kwa">break; case NAND_CTL_CLRCLE: MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR); break; case NAND_CTL_SETALE: MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR); break; case NAND_CTL_CLRALE: MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR); break; case NAND_CTL_SETNCE: MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR); break; case NAND_CTL_CLRNCE: MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR); break; } } if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W); } static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { #error Missing headerfiles. No way to fix this. -tglx switch (cmd) { case NAND_CTL_SETCLE: MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR); break; case NAND_CTL_CLRCLE: MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR); break; case NAND_CTL_SETALE: MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR); break; case NAND_CTL_CLRALE: MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR); break; case NAND_CTL_SETNCE: MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR); break; case NAND_CTL_CLRNCE: MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR); break; } } if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W); } #ifdef USE_READY_BUSY_PIN /* * read device ready pin */ static int ppchameleon_device_ready(struct mtd_info *minfo) { if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN) return 1; return 0; } static int ppchameleonevb_device_ready(struct mtd_info *minfo) { if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN) return 1; return 0; } #endif /* * Main initialization routine */ static int __init ppchameleonevb_init(void) { struct nand_chip *this; void __iomem *ppchameleon_fio_base; void __iomem *ppchameleonevb_fio_base; /********************************* * Processor module NAND (if any) * *********************************/ /* Allocate memory for MTD device structure and private data */ ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); if (!ppchameleon_mtd) { printk("Unable to allocate PPChameleon NAND MTD device structure.\n"); return -ENOMEM; } /* map physical address */ ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M); if (!ppchameleon_fio_base) { printk("ioremap PPChameleon NAND flash failed\n"); kfree(ppchameleon_mtd); return -EIO; } /* Get pointer to private data */ this = (struct nand_chip *)(&ppchameleon_mtd[1]); /* Initialize structures */ memset(ppchameleon_mtd, 0, sizeof(struct mtd_info)); memset(this, 0, sizeof(struct nand_chip)); /* Link the private data with the MTD structure */ ppchameleon_mtd->priv = this; ppchameleon_mtd->owner = THIS_MODULE; /* Initialize GPIOs */ /* Pin mapping for NAND chip */ /* CE GPIO_01 CLE GPIO_02 ALE GPIO_03 R/B GPIO_04 */