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/****************************************************************************/ /* * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC * processors. * * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) * (C) Copyright 2000-2001, Lineo (www.lineo.com) */ /****************************************************************************/ #ifndef FEC_H #define FEC_H /****************************************************************************/ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) /* * Just figures, Motorola would have to change the offsets for * registers in the same peripheral device on different models * of the ColdFire! */ typedef struct fec { unsigned long fec_reserved0; unsigned long fec_ievent; /* Interrupt event reg */ unsigned long fec_imask; /* Interrupt mask reg */ unsigned long fec_reserved1; unsigned long fec_r_des_active; /* Receive descriptor reg */ unsigned long fec_x_des_active; /* Transmit descriptor reg */ unsigned long fec_reserved2[3]; unsigned long fec_ecntrl; /* Ethernet control reg */ unsigned long fec_reserved3[6]; unsigned long fec_mii_data; /* MII manage frame reg */ unsigned long fec_mii_speed; /* MII speed control reg */ unsigned long fec_reserved4[7]; unsigned long fec_mib_ctrlstat; /* MIB control/status reg */ unsigned long fec_reserved5[7]; unsigned long fec_r_cntrl; /* Receive control reg */ unsigned long fec_reserved6[15]; unsigned long fec_x_cntrl; /* Transmit Control reg */ unsigned long fec_reserved7[7]; unsigned long fec_addr_low; /* Low 32bits MAC address */ unsigned long fec_addr_high; /* High 16bits MAC address */ unsigned long fec_opd; /* Opcode + Pause duration */ unsigned long fec_reserved8[10]; unsigned long fec_hash_table_high; /* High 32bits hash table */ unsigned long fec_hash_table_low; /* Low 32bits hash table */ unsigned long fec_grp_hash_table_high;/* High 32bits hash table */ unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */ unsigned long fec_reserved9[7]; unsigned long fec_x_wmrk; /* FIFO transmit water mark */ unsigned long fec_reserved10; unsigned long fec_r_bound; /* FIFO receive bound reg */ unsigned long fec_r_fstart; /* FIFO receive start reg */ unsigned long fec_reserved11[11]; unsigned long fec_r_des_start; /* Receive descriptor ring */ unsigned long fec_x_des_start; /* Transmit descriptor ring */ unsigned long fec_r_buff_size; /* Maximum receive buff size */ } fec_t; #else /* * Define device register set address map. */ typedef struct fec { unsigned long fec_ecntrl; /* Ethernet control reg */ unsigned long fec_ievent; /* Interrupt even reg */ unsigned long fec_imask; /* Interrupt mask reg */ unsigned long fec_ivec; /* Interrupt vec status reg */ unsigned long fec_r_des_active; /* Receive descriptor reg */ unsigned long fec_x_des_active; /* Transmit descriptor reg */ unsigned long fec_reserved1[10]; unsigned long fec_mii_data; /* MII manage frame reg */ unsigned long fec_mii_speed; /* MII speed control reg */ unsigned long fec_reserved2[17]; unsigned long fec_r_bound; /* FIFO receive bound reg */ unsigned long fec_r_fstart; /* FIFO receive start reg */ unsigned long fec_reserved3[4]; unsigned long fec_x_wmrk; /* FIFO transmit water mark */ unsigned long fec_reserved4; unsigned long fec_x_fstart; /* FIFO transmit start reg */ unsigned long fec_reserved5[21]; unsigned long fec_r_cntrl; /* Receive control reg */ unsigned long fec_max_frm_len; /* Maximum frame length reg */ unsigned long fec_reserved6[14]; unsigned long fec_x_cntrl; /* Transmit Control reg */ unsigned long fec_reserved7[158]; unsigned long fec_addr_low; /* Low 32bits MAC address */ unsigned long fec_addr_high; /* High 16bits MAC address */ unsigned long fec_grp_hash_table_high;/* High 32bits hash table */


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