litmus-rt.git - The LITMUS^RT kernel.

The LITMUS^RT kernel.

Bjoern Brandenburg

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/* smctr.h: SMC Token Ring driver header for Linux
 *
 * Authors:
 *  - Jay Schulist <jschlst@samba.org>
 */

#ifndef __LINUX_SMCTR_H
#define __LINUX_SMCTR_H

#ifdef __KERNEL__

#define MAX_TX_QUEUE 10

#define SMC_HEADER_SIZE 14

#define SMC_PAGE_OFFSET(X)          (((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask)

#define INIT            0x0D
#define RQ_ATTCH        0x10
#define RQ_STATE        0x0F
#define RQ_ADDR         0x0E
#define CHG_PARM        0x0C
#define RSP             0x00
#define TX_FORWARD      0x09

#define AC_FC_DAT	((3<<13) | 1)
#define      DAT             0x07

#define RPT_NEW_MON     0x25
#define RPT_SUA_CHG     0x26
#define RPT_ACTIVE_ERR  0x28
#define RPT_NN_INCMP    0x27
#define RPT_ERROR       0x29

#define RQ_INIT         0x20
#define RPT_ATTCH       0x24
#define RPT_STATE       0x23
#define RPT_ADDR        0x22

#define POSITIVE_ACK                    0x0001
#define A_FRAME_WAS_FORWARDED           0x8888

#define      GROUP_ADDRESS                   0x2B
#define      PHYSICAL_DROP                   0x0B
#define      AUTHORIZED_ACCESS_PRIORITY      0x07
#define      AUTHORIZED_FUNCTION_CLASS       0x06
#define      FUNCTIONAL_ADDRESS              0x2C
#define      RING_STATION_STATUS             0x29
#define      TRANSMIT_STATUS_CODE            0x2A
#define      IBM_PASS_SOURCE_ADDR    0x01
#define      AC_FC_RPT_TX_FORWARD            ((0<<13) | 0)
#define      AC_FC_RPT_STATE                 ((0<<13) | 0)
#define      AC_FC_RPT_ADDR                  ((0<<13) | 0)
#define      CORRELATOR                      0x09

#define POSITIVE_ACK                    0x0001          /*             */
#define E_MAC_DATA_INCOMPLETE           0x8001          /* not used    */
#define E_VECTOR_LENGTH_ERROR           0x8002          /*             */
#define E_UNRECOGNIZED_VECTOR_ID        0x8003          /*             */
#define E_INAPPROPRIATE_SOURCE_CLASS    0x8004          /*             */
#define E_SUB_VECTOR_LENGTH_ERROR       0x8005          /*             */
#define E_TRANSMIT_FORWARD_INVALID      0x8006          /* def. by IBM */
#define E_MISSING_SUB_VECTOR            0x8007          /*             */
#define E_SUB_VECTOR_UNKNOWN            0x8008          /*             */
#define E_MAC_HEADER_TOO_LONG           0x8009          /*             */
#define E_FUNCTION_DISABLED             0x800A          /* not used    */

#define A_FRAME_WAS_FORWARDED           0x8888          /* used by send_TX_FORWARD */

#define UPSTREAM_NEIGHBOR_ADDRESS       0x02
#define LOCAL_RING_NUMBER               0x03
#define ASSIGN_PHYSICAL_DROP            0x04
#define ERROR_TIMER_VALUE               0x05
#define AUTHORIZED_FUNCTION_CLASS       0x06
#define AUTHORIZED_ACCESS_PRIORITY      0x07
#define CORRELATOR                      0x09
#define PHYSICAL_DROP                   0x0B
#define RESPONSE_CODE                   0x20
#define ADDRESS_MODIFER                 0x21
#define PRODUCT_INSTANCE_ID             0x22
#define RING_STATION_VERSION_NUMBER     0x23
#define WRAP_DATA                       0x26
#define FRAME_FORWARD                   0x27
#define STATION_IDENTIFER               0x28
#define RING_STATION_STATUS             0x29
#define TRANSMIT_STATUS_CODE            0x2A
#define GROUP_ADDRESS                   0x2B
#define FUNCTIONAL_ADDRESS              0x2C

#define F_NO_SUB_VECTORS_FOUND                  0x0000
#define F_UPSTREAM_NEIGHBOR_ADDRESS             0x0001
#define F_LOCAL_RING_NUMBER                     0x0002
#define F_ASSIGN_PHYSICAL_DROP                  0x0004
#define F_ERROR_TIMER_VALUE                     0x0008
#define F_AUTHORIZED_FUNCTION_CLASS             0x0010
#define F_AUTHORIZED_ACCESS_PRIORITY            0x0020
#define F_CORRELATOR                            0x0040
#define F_PHYSICAL_DROP                         0x0080
#define F_RESPONSE_CODE                         0x0100
#define F_PRODUCT_INSTANCE_ID                   0x0200
#define F_RING_STATION_VERSION_NUMBER           0x0400
#define F_STATION_IDENTIFER                     0x0800
#define F_RING_STATION_STATUS                   0x1000
#define F_GROUP_ADDRESS                         0x2000
#define F_FUNCTIONAL_ADDRESS                    0x4000
#define F_FRAME_FORWARD                         0x8000

#define R_INIT                                  0x00
#define R_RQ_ATTCH_STATE_ADDR                   0x00
#define R_CHG_PARM                              0x00
#define R_TX_FORWARD                            F_FRAME_FORWARD


#define      UPSTREAM_NEIGHBOR_ADDRESS       0x02
#define      ADDRESS_MODIFER                 0x21
#define      RING_STATION_VERSION_NUMBER     0x23
#define      PRODUCT_INSTANCE_ID             0x22

#define      RPT_TX_FORWARD  0x2A

#define AC_FC_INIT                      (3<<13) | 0 /*                     */
#define AC_FC_RQ_INIT                   ((3<<13) | 0) /*                     */
#define AC_FC_RQ_ATTCH                  (3<<13) | 0 /* DC = SC of rx frame */
#define AC_FC_RQ_STATE                  (3<<13) | 0 /* DC = SC of rx frame */
#define AC_FC_RQ_ADDR                   (3<<13) | 0 /* DC = SC of rx frame */
#define AC_FC_CHG_PARM                  (3<<13) | 0 /*                     */
#define AC_FC_RSP                       (0<<13) | 0 /* DC = SC of rx frame */
#define AC_FC_RPT_ATTCH                 (0<<13) | 0

#define S_UPSTREAM_NEIGHBOR_ADDRESS               6 + 2
#define S_LOCAL_RING_NUMBER                       2 + 2
#define S_ASSIGN_PHYSICAL_DROP                    4 + 2
#define S_ERROR_TIMER_VALUE                       2 + 2
#define S_AUTHORIZED_FUNCTION_CLASS               2 + 2
#define S_AUTHORIZED_ACCESS_PRIORITY              2 + 2
#define S_CORRELATOR                              2 + 2
#define S_PHYSICAL_DROP                           4 + 2
#define S_RESPONSE_CODE                           4 + 2
#define S_ADDRESS_MODIFER                         2 + 2
#define S_PRODUCT_INSTANCE_ID                    18 + 2
#define S_RING_STATION_VERSION_NUMBER            10 + 2
#define S_STATION_IDENTIFER                       6 + 2
#define S_RING_STATION_STATUS                     6 + 2
#define S_GROUP_ADDRESS                           4 + 2
#define S_FUNCTIONAL_ADDRESS                      4 + 2
#define S_FRAME_FORWARD                         252 + 2
#define S_TRANSMIT_STATUS_CODE                    2 + 2

#define ISB_IMC_RES0                    0x0000  /* */
#define ISB_IMC_MAC_TYPE_3              0x0001  /* MAC_ARC_INDICATE */
#define ISB_IMC_MAC_ERROR_COUNTERS      0x0002  /* */
#define ISB_IMC_RES1                    0x0003  /* */
#define ISB_IMC_MAC_TYPE_2              0x0004  /* QUE_MAC_INDICATE */
#define ISB_IMC_TX_FRAME                0x0005  /* */
#define ISB_IMC_END_OF_TX_QUEUE         0x0006  /* */
#define ISB_IMC_NON_MAC_RX_RESOURCE     0x0007  /* */
#define ISB_IMC_MAC_RX_RESOURCE         0x0008  /* */
#define ISB_IMC_NON_MAC_RX_FRAME        0x0009  /* */
#define ISB_IMC_MAC_RX_FRAME            0x000A  /* */
#define ISB_IMC_TRC_FIFO_STATUS         0x000B  /* */
#define ISB_IMC_COMMAND_STATUS          0x000C  /* */
#define ISB_IMC_MAC_TYPE_1              0x000D  /* Self Removed */
#define ISB_IMC_TRC_INTRNL_TST_STATUS   0x000E  /* */
#define ISB_IMC_RES2                    0x000F  /* */

#define NON_MAC_RX_RESOURCE_BW          0x10    /* shifted right 8 bits */
#define NON_MAC_RX_RESOURCE_FW          0x20    /* shifted right 8 bits */
#define NON_MAC_RX_RESOURCE_BE          0x40    /* shifted right 8 bits */
#define NON_MAC_RX_RESOURCE_FE          0x80    /* shifted right 8 bits */
#define RAW_NON_MAC_RX_RESOURCE_BW      0x1000  /* */
#define RAW_NON_MAC_RX_RESOURCE_FW      0x2000  /* */
#define RAW_NON_MAC_RX_RESOURCE_BE      0x4000  /* */
#define RAW_NON_MAC_RX_RESOURCE_FE      0x8000  /* */

#define MAC_RX_RESOURCE_BW              0x10    /* shifted right 8 bits */
#define MAC_RX_RESOURCE_FW              0x20    /* shifted right 8 bits */
#define MAC_RX_RESOURCE_BE              0x40    /* shifted right 8 bits */
#define MAC_RX_RESOURCE_FE              0x80    /* shifted right 8 bits */
#define RAW_MAC_RX_RESOURCE_BW          0x1000  /* */
#define RAW_MAC_RX_RESOURCE_FW          0x2000  /* */
#define RAW_MAC_RX_RESOURCE_BE          0x4000  /* */
#define RAW_MAC_RX_RESOURCE_FE          0x8000  /* */

#define TRC_FIFO_STATUS_TX_UNDERRUN     0x40    /* shifted right 8 bits */
#define TRC_FIFO_STATUS_RX_OVERRUN      0x80    /* shifted right 8 bits */
#define RAW_TRC_FIFO_STATUS_TX_UNDERRUN 0x4000  /* */
#define RAW_TRC_FIFO_STATUS_RX_OVERRUN  0x8000  /* */

#define       CSR_CLRTINT             0x08

#define MSB(X)                  ((__u8)((__u16) X >> 8))
#define LSB(X)                  ((__u8)((__u16) X &  0xff))

#define AC_FC_LOBE_MEDIA_TEST           ((3<<13) | 0)
#define S_WRAP_DATA                             248 + 2 /* 500 + 2 */
#define      WRAP_DATA                       0x26
#define LOBE_MEDIA_TEST 0x08

/* Destination Class (dc) */

#define DC_MASK         0xF0
#define DC_RS           0x00
#define DC_CRS          0x40
#define DC_RPS          0x50
#define DC_REM          0x60

/* Source Classes (sc) */

#define SC_MASK         0x0F
#define SC_RS           0x00
#define SC_CRS          0x04
#define SC_RPS          0x05
#define SC_REM          0x06

#define PR		0x11
#define PR_PAGE_MASK	0x0C000

#define MICROCHANNEL	0x0008
#define INTERFACE_CHIP	0x0010
#define BOARD_16BIT	0x0040
#define PAGED_RAM	0x0080
#define WD8115TA	(TOKEN_MEDIA | MICROCHANNEL | INTERFACE_CHIP | PAGED_RAM)
#define WD8115T		(TOKEN_MEDIA | INTERFACE_CHIP | BOARD_16BIT | PAGED_RAM)

#define BRD_ID_8316	0x50

#define r587_SER	0x001
#define SER_DIN		0x80
#define SER_DOUT	0x40
#define SER_CLK		0x20
#define SER_ECS		0x10
#define SER_E806	0x08
#define SER_PNP		0x04
#define SER_BIO		0x02
#define SER_16B		0x01

#define r587_IDR	0x004
#define IDR_IRQ_MASK	0x0F0
#define IDR_DCS_MASK	0x007
#define IDR_RWS		0x008


#define r587_BIO	0x003
#define BIO_ENB		0x080
#define BIO_MASK	0x03F

#define r587_PCR	0x005
#define PCR_RAMS	0x040



#define NUM_ADDR_BITS	8

#define ISA_MAX_ADDRESS		0x00ffffff

#define SMCTR_MAX_ADAPTERS	7

#define MC_TABLE_ENTRIES      16

#define MAXFRAGMENTS          32

#define CHIP_REV_MASK         0x3000

#define MAX_TX_QS             8
#define NUM_TX_QS_USED        3

#define MAX_RX_QS             2
#define NUM_RX_QS_USED        2

#define INTEL_DATA_FORMAT	0x4000
#define INTEL_ADDRESS_POINTER_FORMAT	0x8000
#define PAGE_POINTER(X)		((((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask) + tp->ram_access)
#define SWAP_WORDS(X)		(((X & 0xFFFF) << 16) | (X >> 16))

#define INTERFACE_CHIP          0x0010          /* Soft Config Adapter */
#define ADVANCED_FEATURES       0x0020          /* Adv. netw. interface features */
#define BOARD_16BIT             0x0040          /* 16 bit capability */
#define PAGED_RAM               0x0080          /* Adapter has paged RAM */

#define PAGED_ROM               0x0100          /* Adapter has paged ROM */

#define RAM_SIZE_UNKNOWN        0x0000          /* Unknown RAM size */
#define RAM_SIZE_0K             0x0001          /* 0K  RAM */
#define RAM_SIZE_8K             0x0002          /* 8k  RAM */
#define RAM_SIZE_16K            0x0003          /* 16k RAM */
#define RAM_SIZE_32K            0x0004          /* 32k RAM */
#define RAM_SIZE_64K            0x0005          /* 64k RAM */
#define RAM_SIZE_RESERVED_6     0x0006          /* Reserved RAM size */
#define RAM_SIZE_RESERVED_7     0x0007          /* Reserved RAM size */
#define RAM_SIZE_MASK           0x0007          /* Isolates RAM Size */

#define TOKEN_MEDIA           0x0005

#define BID_REG_0       0x00
#define BID_REG_1       0x01
#define BID_REG_2       0x02
#define BID_REG_3       0x03
#define BID_REG_4       0x04
#define BID_REG_5       0x05
#define BID_REG_6       0x06
#define BID_REG_7       0x07
#define BID_LAR_0       0x08
#define BID_LAR_1       0x09
#define BID_LAR_2       0x0A
#define BID_LAR_3       0x0B
#define BID_LAR_4       0x0C
#define BID_LAR_5       0x0D

#define BID_BOARD_ID_BYTE       0x0E
#define BID_CHCKSM_BYTE         0x0F
#define BID_LAR_OFFSET          0x08  

#define BID_MSZ_583_BIT         0x08
#define BID_SIXTEEN_BIT_BIT     0x01

#define BID_BOARD_REV_MASK      0x1E

#define BID_MEDIA_TYPE_BIT      0x01
#define BID_SOFT_CONFIG_BIT     0x20
#define BID_RAM_SIZE_BIT        0x40
#define BID_BUS_TYPE_BIT        0x80

#define BID_CR          0x10

#define BID_TXP         0x04            /* Transmit Packet Command */

#define BID_TCR_DIFF    0x0D    /* Transmit Configuration Register */

#define BID_TCR_VAL     0x18            /* Value to Test 8390 or 690 */
#define BID_PS0         0x00            /* Register Page Select 0 */
#define BID_PS1         0x40            /* Register Page Select 1 */
#define BID_PS2         0x80            /* Register Page Select 2 */
#define BID_PS_MASK     0x3F            /* For Masking Off Page Select Bits */

#define BID_EEPROM_0                    0x08
#define BID_EEPROM_1                    0x09
#define BID_EEPROM_2                    0x0A
#define BID_EEPROM_3                    0x0B
#define BID_EEPROM_4                    0x0C
#define BID_EEPROM_5                    0x0D
#define BID_EEPROM_6                    0x0E
#define BID_EEPROM_7                    0x0F

#define BID_OTHER_BIT                   0x02
#define BID_ICR_MASK                    0x0C
#define BID_EAR_MASK                    0x0F
#define BID_ENGR_PAGE                   0x0A0
#define BID_RLA                         0x10
#define BID_EA6                         0x80
#define BID_RECALL_DONE_MASK            0x10
#define BID_BID_EEPROM_OVERRIDE         0xFFB0
#define BID_EXTRA_EEPROM_OVERRIDE       0xFFD0
#define BID_EEPROM_MEDIA_MASK           0x07
#define BID_STARLAN_TYPE                0x00
#define BID_ETHERNET_TYPE               0x01
#define BID_TP_TYPE                     0x02
#define BID_EW_TYPE                     0x03
#define BID_TOKEN_RING_TYPE             0x04
#define BID_UTP2_TYPE                   0x05
#define BID_EEPROM_IRQ_MASK             0x18
#define BID_PRIMARY_IRQ                 0x00
#define BID_ALTERNATE_IRQ_1             0x08
#define BID_ALTERNATE_IRQ_2             0x10
#define BID_ALTERNATE_IRQ_3             0x18
#define BID_EEPROM_RAM_SIZE_MASK        0xE0
#define BID_EEPROM_RAM_SIZE_RES1        0x00
#define BID_EEPROM_RAM_SIZE_RES2        0x20
#define BID_EEPROM_RAM_SIZE_8K          0x40
#define BID_EEPROM_RAM_SIZE_16K         0x60
#define BID_EEPROM_RAM_SIZE_32K         0x80
#define BID_EEPROM_RAM_SIZE_64K         0xA0
#define BID_EEPROM_RAM_SIZE_RES3        0xC0
#define BID_EEPROM_RAM_SIZE_RES4        0xE0
#define BID_EEPROM_BUS_TYPE_MASK        0x07
#define BID_EEPROM_BUS_TYPE_AT          0x00
#define BID_EEPROM_BUS_TYPE_MCA         0x01
#define BID_EEPROM_BUS_TYPE_EISA        0x02
#define BID_EEPROM_BUS_TYPE_NEC         0x03
#define BID_EEPROM_BUS_SIZE_MASK        0x18
#define BID_EEPROM_BUS_SIZE_8BIT        0x00
#define BID_EEPROM_BUS_SIZE_16BIT       0x08
#define BID_EEPROM_BUS_SIZE_32BIT       0x10
#define BID_EEPROM_BUS_SIZE_64BIT       0x18
#define BID_EEPROM_BUS_MASTER           0x20
#define BID_EEPROM_RAM_PAGING           0x40
#define BID_EEPROM_ROM_PAGING           0x80
#define BID_EEPROM_PAGING_MASK          0xC0
#define BID_EEPROM_LOW_COST             0x08
#define BID_EEPROM_IO_MAPPED            0x10
#define BID_EEPROM_HMI                  0x01
#define BID_EEPROM_AUTO_MEDIA_DETECT    0x01
#define BID_EEPROM_CHIP_REV_MASK        0x0C

#define BID_EEPROM_LAN_ADDR             0x30

#define BID_EEPROM_MEDIA_OPTION         0x54
#define BID_EEPROM_MEDIA_UTP            0x01
#define BID_EEPROM_4MB_RING             0x08
#define BID_EEPROM_16MB_RING            0x10
#define BID_EEPROM_MEDIA_STP            0x40

#define BID_EEPROM_MISC_DATA            0x56
#define BID_EEPROM_EARLY_TOKEN_RELEASE  0x02

#define CNFG_ID_8003E           0x6fc0
#define CNFG_ID_8003S           0x6fc1
#define CNFG_ID_8003W           0x6fc2
#define CNFG_ID_8115TRA         0x6ec6
#define CNFG_ID_8013E           0x61C8
#define CNFG_ID_8013W           0x61C9
#define CNFG_ID_BISTRO03E       0xEFE5
#define CNFG_ID_BISTRO13E       0xEFD5
#define CNFG_ID_BISTRO13W       0xEFD4
#define CNFG_MSR_583    0x0
#define CNFG_ICR_583    0x1
#define CNFG_IAR_583    0x2
#define CNFG_BIO_583    0x3
#define CNFG_EAR_583    0x3
#define CNFG_IRR_583    0x4
#define CNFG_LAAR_584   0x5
#define CNFG_GP2                0x7
#define CNFG_LAAR_MASK          0x1F
#define CNFG_LAAR_ZWS           0x20
#define CNFG_LAAR_L16E          0x40
#define CNFG_ICR_IR2_584        0x04
#define CNFG_ICR_MASK       0x08
#define CNFG_ICR_MSZ        0x08
#define CNFG_ICR_RLA        0x10
#define CNFG_ICR_STO        0x80
#define CNFG_IRR_IRQS           0x60
#define CNFG_IRR_IEN            0x80
#define CNFG_IRR_ZWS            0x01
#define CNFG_GP2_BOOT_NIBBLE    0x0F
#define CNFG_IRR_OUT2       0x04
#define CNFG_IRR_OUT1       0x02

#define CNFG_SIZE_8KB           8
#define CNFG_SIZE_16KB          16
#define CNFG_SIZE_32KB          32
#define CNFG_SIZE_64KB          64
#define CNFG_SIZE_128KB     128
#define CNFG_SIZE_256KB     256
#define ROM_DISABLE             0x0

#define CNFG_SLOT_ENABLE_BIT    0x08

#define CNFG_POS_CONTROL_REG    0x096
#define CNFG_POS_REG0           0x100
#define CNFG_POS_REG1           0x101
#define CNFG_POS_REG2           0x102
#define CNFG_POS_REG3           0x103
#define CNFG_POS_REG4           0x104
#define CNFG_POS_REG5           0x105

#define CNFG_ADAPTER_TYPE_MASK  0x0e

#define SLOT_16BIT              0x0008
#define INTERFACE_5X3_CHIP      0x0000          /* 0000 = 583 or 593 chips */
#define NIC_690_BIT                     0x0010          /* NIC is 690 */
#define ALTERNATE_IRQ_BIT       0x0020          /* Alternate IRQ is used */
#define INTERFACE_584_CHIP      0x0040          /* 0001 = 584 chip */
#define INTERFACE_594_CHIP      0x0080          /* 0010 = 594 chip */
#define INTERFACE_585_CHIP      0x0100          /* 0100 = 585/790 chip */
#define INTERFACE_CHIP_MASK     0x03C0          /* Isolates Intfc Chip Type */

#define BOARD_16BIT             0x0040
#define NODE_ADDR_CKSUM 	0xEE
#define BRD_ID_8115T    	0x04

#define NIC_825_BIT             0x0400          /* TRC 83C825 NIC */
#define NIC_790_BIT             0x0800          /* NIC is 83C790 Ethernet */

#define CHIP_REV_MASK           0x3000

#define HWR_CBUSY			0x02
#define HWR_CA				0x01

#define MAC_QUEUE                       0
#define NON_MAC_QUEUE                   1
#define BUG_QUEUE                       2       /* NO RECEIVE QUEUE, ONLY TX */

#define NUM_MAC_TX_FCBS                 8
#define NUM_MAC_TX_BDBS                 NUM_MAC_TX_FCBS
#define NUM_MAC_RX_FCBS                 7
#define NUM_MAC_RX_BDBS                 8

#define NUM_NON_MAC_TX_FCBS             6
#define NUM_NON_MAC_TX_BDBS             NUM_NON_MAC_TX_FCBS

#define NUM_NON_MAC_RX_BDBS             0       /* CALCULATED DYNAMICALLY */

#define NUM_BUG_TX_FCBS                 8
#define NUM_BUG_TX_BDBS                 NUM_BUG_TX_FCBS

#define MAC_TX_BUFFER_MEMORY            1024
#define NON_MAC_TX_BUFFER_MEMORY        (20 * 1024)
#define BUG_TX_BUFFER_MEMORY            (NUM_BUG_TX_FCBS * 32)

#define RX_BUFFER_MEMORY                0       /* CALCULATED DYNAMICALLY */
#define RX_DATA_BUFFER_SIZE             256
#define RX_BDB_SIZE_SHIFT               3       /* log2(RX_DATA_BUFFER_SIZE)-log2(sizeof(BDBlock)) */
#define RX_BDB_SIZE_MASK                (sizeof(BDBlock) - 1)
#define RX_DATA_BUFFER_SIZE_MASK        (RX_DATA_BUFFER_SIZE-1)

#define NUM_OF_INTERRUPTS               0x20

#define NOT_TRANSMITING                 0
#define TRANSMITING			1

#define TRC_INTERRUPT_ENABLE_MASK       0x7FF6

#define UCODE_VERSION                   0x58

#define UCODE_SIZE_OFFSET               0x0000  /* WORD */
#define UCODE_CHECKSUM_OFFSET           0x0002  /* WORD */
#define UCODE_VERSION_OFFSET            0x0004  /* BYTE */

#define CS_RAM_SIZE                     0X2000
#define CS_RAM_CHECKSUM_OFFSET          0x1FFE  /* WORD 1FFE(MSB)-1FFF(LSB)*/
#define CS_RAM_VERSION_OFFSET           0x1FFC  /* WORD 1FFC(MSB)-1FFD(LSB)*/

#define MISC_DATA_SIZE                  128


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