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generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 01:36:27 -0400
e */ unsigned char p_slice; /* Physical position on node board */ #endif #if 0 unsigned long loops_per_sec; unsigned long ipi_count; unsigned long irq_attempt[NR_IRQS]; unsigned long smp_local_irq_count; unsigned long prof_multiplier; unsigned long prof_counter; #endif /* * Capability and feature descriptor structure for MIPS CPU */ unsigned long options; unsigned long ases; unsigned int processor_id; unsigned int fpu_id; unsigned int cputype; int isa_level; int tlbsize; struct cache_desc icache; /* Primary I-cache */ struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ #if defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered * to be a "CPU" for the purposes of scheduling, but * exception resources, ASID spaces, etc, are common * to all TCs within the same VPE. */ int vpe_id; /* Virtual Processor number */ int tc_id; /* Thread Context number */ #endif /* CONFIG_MIPS_MT */ void *data; /* Additional data */ } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] extern void cpu_probe(void); extern void cpu_report(void); #endif /* __ASM_CPU_INFO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 01:36:27 -0400