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| * mtd: st_spi_fsm: Refactor status register operationsAngus Clark2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the fsm_read_status() and fsm_write_status() code to support 1 or 2 byte operations, with a specified command. This allows us to remove device/register specific code, such as the N25Q fsm_wrvcr() function. The 'QE' configuration code is updated accordingly, with minor tweaks to ensure the register values are only written if actually required. One notable change in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only used for write operations. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Update Macronix 'QE' configurationAngus Clark2014-04-14
| | | | | | | | | | | | | | | | | | Update the configuration of the Macronix 'QE' bit, such that we only set or clear the bit if required. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Update Macronix 32-bit addressing supportAngus Clark2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Macronix 32-bit addressing scheme was originally developed using the MX25L25635E device. As is often the case, it was found that the presence of a "WAIT" instruction was required for the "EN4B/EX4B" FSM Sequence to complete. (It is known that the SPI FSM Controller makes certain undocumented assumptions regarding what constitutes a valid sequence.) However, further testing suggested that a small delay was required after issuing the "EX4B" command; without this delay, data corruptions were observed, consistent with the device not being ready to retrieve data. Although the issue was not fully understood, the workaround of adding a small delay was implemented, while awaiting clarification from Macronix. The same behaviour has now been found with a second Macronix device, the MX25L25655E. However, with this device, it seems that the delay is also required after the 'EN4B' commands. This discovery has prompted us to revisit the issue. Although still not conclusive, further tests have suggested that the issue is down to the SPI FSM Controller, rather than the Macronix devices. Furthermore, an alternative workaround has emerged which is to set the WAIT time to 0x00000001, rather then 0x00000000. (Note, the WAIT instruction is used purely for the purpose of achieving "sequence validity", rather than actually implementing a delay!) The issue is now being investigated by the Design and Validation teams. In the meantime, we implement the alternative workaround, which reduces the effective delay from 1us to 1ns. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Add Macronix MX25L25655E deviceAngus Clark2014-04-14
| | | | | | | | | | | | | | | | Add Macronix MX25L25655E to the list of known devices. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: m25p80: use the SPI nor frameworkBrian Norris2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* | Shiraz has movedViresh Kumar2014-04-18
|/ | | | | | | | | | | | shiraz.hashim@st.com email-id doesn't exist anymore as he has left the company. Replace ST's id with shiraz.linux.kernel@gmail.com. It also updates .mailmap file to fix address for 'git shortlog'. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mtd: devices: elm: update DRIVER_NAME as "omap-elm"Pekon Gupta2014-03-26
| | | | | | | | use "omap-elm" as DRIVER_NAME Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: devices: elm: configure parallel channels based on ecc_stepsPekon Gupta2014-03-26
| | | | | | | | | | | | ELM hardware can process up to maximum of 8 hannels in parallel for ECC error detection. Currently the number of channels getting configured for processing is static determined by macro ERROR_VECTOR_MAX. However, the actual number of channels that need to be processed is the ECC step number. This patch just avoids configuring extra unused channels. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: devices: elm: clean elm_load_syndromePekon Gupta2014-03-26
| | | | | | | | | | This patch refactors elm_load_syndrome() to make it scalable for newer ECC schemes by removing scheme specific macros (like ECC_BYTES*xx), and instead using ECC control information passed during elm_config. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: devices: elm: check for hardware engine's design constraintsPekon Gupta2014-03-26
| | | | | | | | | | | | | | | | ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC errors. This patch adds the following checks for ELM hardware engine: - ELM internal buffers are of 1K, so it cannot process data with ecc-step-size > 1K. - ELM engine can execute upto maximum of 8 threads in parallel, so in *page-mode* (when complete page is processed in single iteration), ELM cannot support ecc-steps > 8. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Succinctly reorganise .remove()Lee Jones2014-03-20
| | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Allow loop to run at least once before giving up CPULee Jones2014-03-20
| | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"Lee Jones2014-03-20
| | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Avoid duplicating MTD core codeLee Jones2014-03-20
| | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Remove useless consts from function argumentsLee Jones2014-03-20
| | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> [Brian: tweaked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitionsLee Jones2014-03-20
| | | | | | | | | | | The old API expected a "partitions" property provided a phandle to a separate partitions node, which itself contained yet more nodes each representing one partition. The new API rids the requirement for the superfluous intermediary partitions node. This patch provides the added information required for automatic parsing by the core. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Move runtime configurable msg sequences into device's structLee Jones2014-03-20
| | | | | | | | | | | | | Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris <computersforpeace@gmail.com> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | This patch allows us to prepare some of the message sequences which will be required to talk to the S25FLxxx family of Serial Flash devices. It also allows us to do some required extra operations after any busy wait failures. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add the ability to write to FSM's status registerLee Jones2014-03-20
| | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add the ability to read the FSM's statusLee Jones2014-03-20
| | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Erase partly or as a whole a Serial Flash deviceLee Jones2014-03-20
| | | | | | | | | | | When an erase is requested by userspace the MTD framework calls back into the driver to conduct the actual command issue. Here we provide the routines which do exactly that. We can choose to either do an entire chip erase or by sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply a busy wait for post-write statusLee Jones2014-03-20
| | | | | | | | | | When we write data to the Serial Flash chip we'll wait a predetermined period of time before giving up. During that period of time we poll the status register until completion. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Write to Flash via the FSM FIFOLee Jones2014-03-20
| | | | | | | | | When we write data to the FIFO the FSM Controller subsequently writes that data out to the Serial Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add the ability to read from a Serial Flash deviceLee Jones2014-03-20
| | | | | | | | | | When a read is issued by userspace the MTD framework calls back into the driver to conduct the actual command issue and data extraction. Here we provide the routines which do exactly that. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Prepare default sequences for read/write/eraseLee Jones2014-03-20
| | | | | | | | | | | Most chips require a predefined set of FSM message sequences for read, write and erase operations. This patch provides a way to set them up, which it will do so if a chip specific initialisation routine isn't been provided. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | | | In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply the N25Qxxx specific read configurationsLee Jones2014-03-20
| | | | | | | | | | The N25Qxxx Serial Flash devices required different sequence configurations depending on whether they're running in 24bit (3Byte) or 32bit (4Byte) mode. We provide those here. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Provide the default read/write configurationsLee Jones2014-03-20
| | | | | | | | | | | | | | Message sequences can vary depending on how many pads (lines) are required to address the chip (mode & dummy), how many data pads (lines) are required to write out to the chip which will determine speed amongst other things which are detailed by the SFDP specification. We are able to use multiple configurations for each chip, but they need to me matched to a device's capabilities. These configurations are listed in preference order - most preferred first. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Update the flash Volatile Configuration RegisterLee Jones2014-03-20
| | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for updating a chip's VCR. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing modeLee Jones2014-03-20
| | | | | | | | | | | | Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add a check to if the chip can handle an SoC resetLee Jones2014-03-20
| | | | | | | | | | | Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Prepare read/write sequences according to configurationLee Jones2014-03-20
| | | | | | | | | | Firstly we search for our preference read/write configuration based on a given chip's capabilities. Then we actually set up the message sequence accordingly. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing modeLee Jones2014-03-20
| | | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Provide the erase one sector sequenceLee Jones2014-03-20
| | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for erasing a single sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Fetch boot-device from mode pinsLee Jones2014-03-20
| | | | | | | | | | | | It's important for us to determine which device was used to boot from in order to make some correct decisions surrounding Power Management. On each of the platforms which support the FSM this is communicated via a set of mode pins held in the system configuration area. This patch determine the boot device and stores the result. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Prepare the read/write FSM message sequence(s)Lee Jones2014-03-20
| | | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare read/write FSM message sequence(s) based on chip capability and configuration. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Use device size to determine address widthLee Jones2014-03-20
| | | | | | | | | | Take some known parameters, namely size and number of sectors and use them to determine weather a device can support 32bit addressing or not. If it can, set the associated flash capability flag for latter use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Search for preferred FSM message sequence configurationsLee Jones2014-03-20
| | | | | | | | | | | Here we provide a means to traverse though all supplied FSM message sequence configurations and pick one based on our chip's capabilities. The first one we match will be the preferred one, as they are presented in order of preference. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Dynamically setup flash device based on JEDEC IDLee Jones2014-03-20
| | | | | | | | | | Using previously added infrastructure we can now extract a device's JEDEC ID, compare it to a list of known and supported devices and make assumptions based on known characteristics of a given chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Provide device look-up tableLee Jones2014-03-20
| | | | | | | | | | | | Supply a lookup table of all the devices we intend to support. This table is used to store device information such as; a human readable device name, their JEDEC ID (plus the extended version), sector size and amount, a bit store of a device's capabilities, its maximum running frequency and possible use of a per-device configuration call-back. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: devices: Provide header for shared OPCODEs and SFDP commandsLee Jones2014-03-20
| | | | | | | | | | | | | JEDEC have helped to standardise a great deal of the commands which can be issued to a Serial Flash devices. Many of the Serial Flash Discoverable Parameters (SFDP) commands are generic across devices. This patch provides a shared point where these commands can be defined. Suggested-by: Mark Brown <broonie@kernel.org> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add support for JEDEC ID extractionLee Jones2014-03-20
| | | | | | | | | | | Once we start supporting devices it will be handy go detect them dynamically. This will be done using the chip's unique JEDEC ID. This patch allows us to extract a device's JEDEC ID using the a predefined FSM register write sequence. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply a method to read from the FSM's FIFOLee Jones2014-03-20
| | | | | | | | | | When invoked the driver will attempt to read any available data from the FSM's data register. Any data collected from this FIFO would have originated from the flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply framework for device requestsLee Jones2014-03-20
| | | | | | | | | | | The FSM hardware works by setting a predetermined sequence of register writes. Rather than open coding them inside each functional block we're going to define them in a series of formatted 'sequence structures'. This patch provides the framework which shall be used for every action. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Initialise and configure the FSM for normal working conditionsLee Jones2014-03-20
| | | | | | | | | | | This patch uses default values to initialise a connected flash chip. This includes; a device soft reset, setting of a safe working frequency, a switch into Fast Sequencing Mode, configuring of timing data and a purge of the FIFO. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Supply all register address and bit logic definesLee Jones2014-03-20
| | | | | | | | | | Here we provide the FSM's register addresses, register bit names/offsets and some commands which will prove useful as we start bulk the FMS's driver out with functionality. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Allocate resources and register with MTD frameworkLee Jones2014-03-20
| | | | | | | | | | This is a new driver. It's used to communicate with a special type of optimised Serial Flash Controller called the FSM. The FSM uses a subset of the SPI protocol to communicate with supported NOR-Flash devices. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: Fix the behavior of OTP write if there is not enough room for dataChristian Riesch2014-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a write to one time programmable memory (OTP) hits the end of this memory area, no more data can be written. The count variable in mtdchar_write() in drivers/mtd/mtdchar.c is not decreased anymore. We are trapped in the loop forever, mtdchar_write() will never return in this case. The desired behavior of a write in such a case is described in [1]: - Try to write as much data as possible, truncate the write to fit into the available memory and return the number of bytes that actually have been written. - If no data could be written at all, return -ENOSPC. This patch fixes the behavior of OTP write if there is not enough space for all data: 1) mtd_write_user_prot_reg() in drivers/mtd/mtdcore.c is modified to return -ENOSPC if no data could be written at all. 2) mtdchar_write() is modified to handle -ENOSPC correctly. Exit if a write returned -ENOSPC and yield the correct return value, either then number of bytes that could be written, or -ENOSPC, if no data could be written at all. Furthermore the patch harmonizes the behavior of the OTP memory write in drivers/mtd/devices/mtd_dataflash.c with the other implementations and the requirements from [1]. Instead of returning -EINVAL if the data does not fit into the OTP memory, we try to write as much data as possible/truncate the write. [1] http://pubs.opengroup.org/onlinepubs/9699919799/functions/write.html Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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