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* Merge branch 'msm-fixes-3.19' of ↵Dave Airlie2014-12-22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~robclark/linux into drm-fixes A few msm fixes for 3.19: * hdmi regulators fix * hdmi fix for spurious HPD interrupts * fix for sync atomic update after async update (which could show up with a setcrtc following a pageflip) * couple little Coccinelle cleanups * 'msm-fixes-3.19' of git://people.freedesktop.org/~robclark/linux: drm/msm/hdmi: rework HDMI IRQ handler drm/msm/hdmi: enable regulators before clocks to avoid warnings drm/msm/mdp5: update irqs on crtc<->encoder link change drm/msm: block incoming update on pending updates drm/msm: Deletion of unnecessary checks before the function call "release_firmware" drm/msm: Deletion of unnecessary checks before two function calls
| * drm/msm/hdmi: rework HDMI IRQ handlerJilai Wang2014-12-18
| | | | | | | | | | | | | | Disable the HPD interrupt when acking it, to avoid spurious interrupt. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org>
| * drm/msm/hdmi: enable regulators before clocks to avoid warningsJilai Wang2014-12-18
| | | | | | | | | | | | | | HPD regulators need to be enabled before clocks, otherwise clock driver will report warning. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org>
| * drm/msm/mdp5: update irqs on crtc<->encoder link changeRob Clark2014-12-18
| | | | | | | | | | | | | | | | | | | | If crtc <-> encoder linkage changes, we could end up with the CRTC listening for the wrong error or vsync irqs. Generally this problem would correct itself relatively quickly, since we update the global irqmask after dispatching irqs, but to be sure let the CRTC trigger update_irq(). Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: block incoming update on pending updatesRob Clark2014-12-18
| | | | | | | | | | | | | | | | | | We can't have multiple updates pending on a given CRTC, and we don't want a sync update to race w/ an async update that preceeded it. So keep track of which CRTCs have updates in flight, and block later updates that would conflict. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: Deletion of unnecessary checks before the function call ↵Markus Elfring2014-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | "release_firmware" The release_firmware() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: Deletion of unnecessary checks before two function callsMarkus Elfring2014-12-17
| | | | | | | | | | | | | | | | | | | | | | The functions framebuffer_release() and vunmap() perform also input parameter validation. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2014-12-15
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "Highlights: - AMD KFD driver merge This is the AMD HSA interface for exposing a lowlevel interface for GPGPU use. They have an open source userspace built on top of this interface, and the code looks as good as it was going to get out of tree. - Initial atomic modesetting work The need for an atomic modesetting interface to allow userspace to try and send a complete set of modesetting state to the driver has arisen, and been suffering from neglect this past year. No more, the start of the common code and changes for msm driver to use it are in this tree. Ongoing work to get the userspace ioctl finished and the code clean will probably wait until next kernel. - DisplayID 1.3 and tiled monitor exposed to userspace. Tiled monitor property is now exposed for userspace to make use of. - Rockchip drm driver merged. - imx gpu driver moved out of staging Other stuff: - core: panel - MIPI DSI + new panels. expose suggested x/y properties for virtual GPUs - i915: Initial Skylake (SKL) support gen3/4 reset work start of dri1/ums removal infoframe tracking fixes for lots of things. - nouveau: tegra k1 voltage support GM204 modesetting support GT21x memory reclocking work - radeon: CI dpm fixes GPUVM improvements Initial DPM fan control - rcar-du: HDMI support added removed some support for old boards slave encoder driver for Analog Devices adv7511 - exynos: Exynos4415 SoC support - msm: a4xx gpu support atomic helper conversion - tegra: iommu support universal plane support ganged-mode DSI support - sti: HDMI i2c improvements - vmwgfx: some late fixes. - qxl: use suggested x/y properties" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (969 commits) drm: sti: fix module compilation issue drm/i915: save/restore GMBUS freq across suspend/resume on gen4 drm: sti: correctly cleanup CRTC and planes drm: sti: add HQVDP plane drm: sti: add cursor plane drm: sti: enable auxiliary CRTC drm: sti: fix delay in VTG programming drm: sti: prepare sti_tvout to support auxiliary crtc drm: sti: use drm_crtc_vblank_{on/off} instead of drm_vblank_{on/off} drm: sti: fix hdmi avi infoframe drm: sti: remove event lock while disabling vblank drm: sti: simplify gdp code drm: sti: clear all mixer control drm: sti: remove gpio for HDMI hot plug detection drm: sti: allow to change hdmi ddc i2c adapter drm/doc: Document drm_add_modes_noedid() usage drm/i915: Remove '& 0xffff' from the mask given to WA_REG() drm/i915: Invert the mask and val arguments in wa_add() and WA_REG() drm: Zero out DRM object memory upon cleanup drm/i915/bdw: Fix the write setting up the WIZ hashing mode ...
| * drm/msm: switch to atomic-helpers iterator macrosRob Clark2014-11-27
| | | | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/plane: Pass old state to ->atomic_update()Thierry Reding2014-11-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In most situations it will be useful to have the old state passed to the ->atomic_update() callback. For example if a plane is being disabled the new state's .crtc field will be NULL, but some drivers may rely on this field to program the CRTCs registers. v2: rename variable to old_plane_state and remove redundant comment as suggested by Daniel Vetter, remove an Exynos hunk that doesn't apply to drm-next and add a hunk for pending MSM mdp5 changes Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/msm/mdp4: fix mixer setup for multi-crtc + planesRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | On mdp4 there is a single global LAYERMIXER_IN_CFG register. The previous logic to share that between multiple crtcs didn't actually handle plane-disable very well. Easier just to look at all of the crtcs each time. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: dpms(OFF) cleanupsRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | | | | | When disabling the interface (INTF), the change doesn't latch until next vblank, so we need to wait for vblank. Also, to be pedantic, in the crtc, set all the mixer stages to unused. It shouldn't really matter, since at this point we have already disabled the INTF and waited for necessary vblank. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: atomicRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | | | Convert mdp5 over to atomic helpers. Extend/wrap drm_plane_state to track plane zpos and to keep track of the needed when applying the atomic update. In mdp5's plane->atomic_check() we also need to check for updates which require SMP reallocation, in order to trigger full modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: atomic fixesRob Clark2014-11-21
| | | | | | | | | | | | Fixes for a couple little issues found in testing. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: remove global mdp5_ctl_mgrRob Clark2014-11-21
| | | | | | | | | | | | | | A bit cleaner.. and won't resulting in an attempt to kfree() a static global in unload path. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: don't use void * for opaque typesRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | For example, use 'struct mdp5_smp *' everywhere instead of 'void *', but only declare it as 'struct mdp5_smp;' in common headers, so the struct body is still private. The accomplishes the desired modularity while still letting the compiler provide some type checking for us. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: add multiple CRTC and overlay supportStephane Viau2014-11-21
| | | | | | | | | | | | | | | | | | MDP5 currently support one single CRTC with its private pipe. This change allows the configuration of multiple CRTCs with the possibility to attach several public planes to these CRTCs. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: set rate before enabling clkRob Clark2014-11-21
| | | | | | | | | | | | | | Set a "safe" rate at first, in order to read out the hw revision. And then after set the optimal value. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: introduce mdp5_cfg moduleStephane Viau2014-11-21
| | | | | | | | | | | | | | | | | | | | The hardware configuration modification from a version to another is quite consequent. Introducing a configuration module (mdp5_cfg) may make things more clear and easier to access when a new hardware version comes up. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: make SMP module dynamically configurableStephane Viau2014-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Shared Memory Pool (SMP) has its own limitation, features and state. Some examples are: - the number of Memory Macro Block (MMB) and their size - the number of lines that can be fetched - the state of MMB currently allocated - the computation of number of blocks required per plane - client IDs ... In order to avoid private data to be overwritten by other modules, let's make these private to the SMP module. Some of these depend on the hardware configuration, let's add them to the mdp5_config struct. In some hw configurations, some MMBs are statically tied to RGB pipes and cannot be re-allocated dynamically. This change introduces the concept of MMB static usage and makes sure that dynamic MMB requests are dimensioned accordingly. A note on passing a pipe pointer, instead of client IDs: Client IDs are SMP-related information. Passing PIPE information to SMP lets SMP module to find out which SMP client(s) are used. This allows the SMP module to access the PIPE pointer, which can be used for FIFO watermark configuration. By the way, even though REG_MDP5_PIPE_REQPRIO_FIFO_WM_* registers are part of the PIPE registers, their functionality is to reflect the behavior of the SMP block. These registers access is now restricted to the SMP module. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/hdmi: remove useless krefRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | | | A left-over from prior to component framework. The original intent was to deal with hdmi getting unloaded before the master component, but that isn't really going to work anyways. These days with the component framework taking care to unload the master component first, we don't have to worry about this. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: get the core clock rate from MDP5 configStephane Viau2014-11-21
| | | | | | | | | | | | | | | | | | | | | | The core clock rate depends on the hw configuration. Once we have read the hardware revision, we can set the core clock to its maximum value. Before then, the clock is set at a rate supported by all MDP5 revisions. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: use irqdomainsRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mdp5, the irqs of hdmi/eDP/dsi0/dsi1 blocks get routed through the mdp block. In order to decouple hdmi/eDP/etc, register an irq domain in mdp5. When hdmi/dsi/etc are used with mdp4, they can directly setup their irqs in their DT nodes as normal. When used with mdp5, instead set the mdp device as the interrupt-parent, as in: mdp: qcom,mdss_mdp@fd900000 { compatible = "qcom,mdss_mdp"; interrupt-controller; #interrupt-cells = <1>; ... }; hdmi: qcom,hdmi_tx@fd922100 { compatible = "qcom,hdmi-tx-8074"; interrupt-parent = <&mdp>; interrupts = <8 0>; /* MDP5_HW_INTR_STATUS.INTR_HDMI */ ... }; There is a slight awkwardness, in that we cannot disable child irqs at the mdp level, they can only be cleared in the child block. So you must not use threaded irq handlers in the child. I'm not sure if there is a better way to deal with that. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: a4xx support for msm-drmAravind Ganesan2014-11-16
| | | | | | | | | | | | | | Added a4xx GPU support. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: Handle register offset differences between a3xx and a4xxAravind Ganesan2014-11-16
| | | | | | | | | | | | | | | | | | | | | | | | Register offsets have changed between a3xx and a4xx GPUs. To be able access these registers in common code, we create a lookup table, and set of read-write APIs to access the register through the lookup table. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> [robclark: remove REG_ADRENO_UNDEFINED, just use zero, and minor tweaks for latest generated headers] Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: small mmap offset cleanupsRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | Use pre-computed iova when unmapping, to reduce the places we assume iova and mmap offset are (at the moment) the same. And get rid of an extra drm_gem_free_mmap_offset() call (since it is already called from drm_gem_object_release()) Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp4: atomicRob Clark2014-11-16
| | | | | | | | | | | | Convert mdp4 display controller backend to atomic helpers. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/hdmi: atomicRob Clark2014-11-16
| | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: atomic core bitsRob Clark2014-11-16
| | | | | | | | | | | | The core parts for async commit. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: bit of fb error checkingRob Clark2014-11-16
| | | | | | | | | | | | | | | | It's a problem that can't happen yet, since we don't support any multi-planar formats yet. But let's avoid nasty surprises when the time comes. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: fb prepare/cleanupRob Clark2014-11-16
| | | | | | | | | | | | | | | | Atomic wants to split the prepare/pin from where we actually program the scanout address (so that any part that can fail is done synchronously). Add some fb/gem apis to make this easier to use from the kms parts. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: remove unused compile-test stubRob Clark2014-11-16
| | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: small fence cleanupRob Clark2014-11-16
| | | | | | | | | | | | | | Give ourselves a way to wait for certain fence #.. makes it easier to wait on a set of bo's, which we'll need for atomic. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: drop attached planes tableRob Clark2014-11-16
| | | | | | | | | | | | | | Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp4: drop attached planes tableRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. TODO move iterator macro somewhere common. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp4: don't care about fb in crtcRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | Since we are configuring things via MDP4_PIPE regs in the plane, it seems like setting the dimensions of the primary plane on the OVLP/DMA regs in crtc is unnecessary. This will make life easier when we want to do a nofb modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: drop private primary ptrRob Clark2014-11-16
| | | | | | | | | | | | Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp4: drop private primary ptrRob Clark2014-11-16
| | | | | | | | | | | | Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: Fix fbdev for 16- and 24-bit modes.Daniel Thompson2014-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently forcing the video mode from the kernel command line (for example video=HDMI-A-1:1280x720-16@60) does not correctly set the number of bits per pixel. This is due to a rather aggressive override in msm_fbdev_create(). This is a particular problem for Android bring up because the software EGL fallbacks don't support 32bpp. Since the overrides are actually the default values anyway then this problem can be trivially fixed by removing the overrides completely. Change was tested by dd'ing a test image to /dev/fb0 with no video= (still 32bpp), video=1920x1080-32@60, video=1920x1080-24@60 and video=1920x1080-16@60 . Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: David Airlie <airlied@linux.ie> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: Allow exported dma-bufs to be mappedDaniel Thompson2014-11-16
| | | | | | | | | | | | | | | | | | | | | | Currently msm does not implement gem_prime_mmap. Without this it is not possible to draw onto a dma-buf from userspace (making its very hard to implement the Android rendering model). Fixing this is just a matter of adding a little boilerplate. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/hdmi: refactor bind/initRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | | | | | | | Split up hdmi_init() into hdmi_init() (done at hdmi sub-device bind/probe time) and hdmi_modeset_init() done from master driver's modeset_init(). Anything that can fail due to dependencies on other drivers which may be missing or not probed yet should go in hdmi_init(), so that devm error/cleanup paths work properly. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: update generated headersRob Clark2014-11-16
| | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/adreno: slight init order cleanupRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | Move anything that can fail after call to base class msm_gpu_init(). This way, if we fail, active_list has already been initialized so we don't trip 'WARN_ON(!list_empty(&gpu->active_list))' in msm_gpu_cleanup(). Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: select REGULATORRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes a potential error, spotted by Felipe with randconfig: ----- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c: In function ‘mdp4_kms_init’: drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:2: error: implicit declaration \ of function ‘devm_regulator_get_exclusive’ [-Werror=implicit-function-declaration] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:16: error: assignment makes \ pointer from integer without a cast [-Werror] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ ----- Also add a brief comment explaining the use of _get_exclusive() Reported-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm: flip-work: change drm_flip_work_init prototypeBoris BREZILLON2014-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we're using lists instead of kfifo to store drm flip-work tasks we do not need the size parameter passed to drm_flip_work_init function anymore. Moreover this function cannot fail anymore, we can thus remove the return code. Modify drm_flip_work_init users to take account of these changes. [airlied: fixed two unused variable warnings] Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | gpu: drm: msm: drop owner assignment from platform_driversWolfram Sang2014-10-20
|/ | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* drm: Pass dma-buf as argument to gem_prime_import_sg_tableMaarten Lankhorst2014-09-30
| | | | | | Allows importing dma_reservation_objects from a dma-buf. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
* drm: Extract <drm/drm_gem.h>Daniel Vetter2014-09-23
| | | | | | | | | | | v2: Don't forget git add, noticed by David. Cc: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Acked-by: David Herrmann <dh.herrmann@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: backmerge tag 'v3.17-rc5' into drm-nextDave Airlie2014-09-15
|\ | | | | | | | | | | | | This is requested to get the fixes for intel and radeon into the same tree for future development work. i915_display.c: fix missing dev_priv conflict.
| * drm/msm: don't crash if no msm.vram paramRob Clark2014-09-11
| | | | | | | | | | | | | | | | If VRAM carveout is used, due to no IOMMU, we should have a default value for msm.vram so that we don't simply crash. Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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