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authorRob Clark <robdclark@gmail.com>2014-11-20 17:05:04 -0500
committerRob Clark <robdclark@gmail.com>2014-11-21 08:59:24 -0500
commitd6ac4a84e7a3713929ec473cb8c10acc1dec41a2 (patch)
tree44628a9fc5fe70e375d84fcc8dd4bf5a92a84005 /drivers/gpu/drm/msm
parented8519636ef6c4b6ffbc4a449ebf39502e80ee74 (diff)
drm/msm/mdp5: dpms(OFF) cleanups
When disabling the interface (INTF), the change doesn't latch until next vblank, so we need to wait for vblank. Also, to be pedantic, in the crtc, set all the mixer stages to unused. It shouldn't really matter, since at this point we have already disabled the INTF and waited for necessary vblank. Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm')
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c2
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c11
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index a6728a80f7e0..0598bdea4ff4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -150,6 +150,8 @@ static void mdp5_crtc_dpms(struct drm_crtc *crtc, int mode)
150 mdp5_enable(mdp5_kms); 150 mdp5_enable(mdp5_kms);
151 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); 151 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
152 } else { 152 } else {
153 /* set STAGE_UNUSED for all layers */
154 mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000);
153 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); 155 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
154 mdp5_disable(mdp5_kms); 156 mdp5_disable(mdp5_kms);
155 } 157 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 25c2fcb39ac3..0254bfdeb92f 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -132,6 +132,17 @@ static void mdp5_encoder_dpms(struct drm_encoder *encoder, int mode)
132 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); 132 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
133 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0); 133 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0);
134 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); 134 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
135
136 /*
137 * Wait for a vsync so we know the ENABLE=0 latched before
138 * the (connector) source of the vsync's gets disabled,
139 * otherwise we end up in a funny state if we re-enable
140 * before the disable latches, which results that some of
141 * the settings changes for the new modeset (like new
142 * scanout buffer) don't latch properly..
143 */
144 mdp_irq_wait(&mdp5_kms->base, intf2vblank(intf));
145
135 bs_set(mdp5_encoder, 0); 146 bs_set(mdp5_encoder, 0);
136 } 147 }
137 148