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path: root/drivers/gpu/drm/msm/mdp
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* drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()Stephane Viau2015-05-21
| | | | | | | | | The index of ->planes[] array (3rd parameter) cannot be equal to MAX_PLANE. This looks like a typo that is now fixed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/msm/mdp5: Fix iteration on INTF config arrayStephane Viau2015-05-14
| | | | | | | | | | | | | | | | | | | | The current iteration in get_dsi_id_from_intf() is wrong: instead of iterating until hw_cfg->intf.count, we need to iterate until MDP5_INTF_NUM_MAX here. Let's take the example of msm8x16: hw_cfg->intf.count = 1 intfs[0] = INTF_Disabled intfs[1] = INTF_DSI If we stop iterating once i reaches hw_cfg->intf.count (== 1), we will miss the test for intfs[1]. Actually, this hw_cfg->intf.count entry is quite confusing and is not (or *should not be*) used anywhere else; let's remove it. Signed-off-by: Stephane Viau <sviau@codeaurora.org>
* drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li2015-04-01
| | | | | | | | | | | | | | This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li2015-04-01
| | | | | | | | | | This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau2015-04-01
| | | | | | | | This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau2015-04-01
| | | | | | | | | | | Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau2015-04-01
| | | | | | | | | | | | | | This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau2015-04-01
| | | | | | | | This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau2015-04-01
| | | | | | | | | | | | | MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau2015-04-01
| | | | | | | | This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Fix PIPE source image size settingsHai Li2015-04-01
| | | | | | | | The width and height in SSPP_SRC_IMG_SIZE register should be the size of the entire source framebuffer, not the fetch size. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li2015-04-01
| | | | | | | | This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add pingpong entry to mdp5 config tableHai Li2015-04-01
| | | | | | | | | Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Make the intf connection in config moduleStephane Viau2015-04-01
| | | | | | | | | | | | Up until now, we assume that eDP is tight to intf_0 and HDMI to intf_3. This information shall actually come from the mdp5_cfg module since it can change from one chip to another. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau2015-04-01
| | | | | | | | | | | Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Remove temp bisectability hack -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update generated header filesStephane Viau2015-04-01
| | | | | | | | | Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: only flush on a CRTC ->atomic_flush()Stephane Viau2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'v4.0-rc3' into drm-nextDave Airlie2015-03-09
|\ | | | | | | | | | | | | | | | | Linux 4.0-rc3 backmerge to fix two i915 conflicts, and get some mainline bug fixes needed for my testing box Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_display.c
| * drm/msm: kexec fixesRob Clark2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | In kexec environment, we are more likely to encounter irq's already enabled from previous environment. At which point we find that writes to disable/clear pending irq's are slightly less than useless without first enabling clocks. TODO: full blown state read-in so kexec'd kernel can inherit the mode already setup. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: fix cursor blendingRob Clark2015-03-04
| | | | | | | | | | | | | | | | Seems like we just want BLEND_EN and not BLEND_TRANSP_EN (setting the latter results in black pixels in the cursor image treated as transparent). Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: fix cursor ROIRob Clark2015-03-04
| | | | | | | | | | | | | | | | If cursor is set near the edge of the screen, it is not valid to use the new cursor width/height as the ROI dimensions. Split out the ROI calc and use it both cursor_set and cursor_move. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: Avoid flushing registers when CRTC is disabledStephane Viau2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a CRTC is disabled, no CTL is allocated to it (CRTC->ctl == NULL); in that case we should not try to FLUSH registers and do nothing instead. This can happen when we try to move a cursor but the CRTC's CTL (CONTROL) has not been allocated yet (inactive CRTC). It can also happens when we .atomic_check()/.atomic_flush() on a disabled CRTC. A CTL needs to be kept as long as the CRTC is alive. Releasing it after the last VBlank is safer than in .atomic_flush(). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm: update generated headers (add 6th lm.base entry)Stephane Viau2015-03-04
| | | | | | | | | | | | | | | | Some target have up to 6 layer mixers (LM). Let the header file access the last LM's base address. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
| * drm/msm/mdp5: fixup "drm/msm: fix fallout of atomic dpms changes"Stephane Viau2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0b776d457b94 ("drm/msm: fix fallout of atomic dpms changes") has a typo in both mdp5_encoder_helper_funcs and mdp5_crtc_helper_funcs definitions: .dpms entry should be replaced by .disable and .enable Also fixed a typo in mdp5_encoder_enable(). Note that these typos are only present for MDP5. MDP4 is fine. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm: Pass in new and old plane state to prepare_fb and cleanup_fbTvrtko Ursulin2015-03-04
|/ | | | | | | | | | | | | | | | | | Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapping to instantiate and which to tear down when transitioning between them. v2: Made passed in states const. (Daniel Vetter) [airlied: add mdp5 and atmel fixups] Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/msm/mdp5: Fix negative SMP block allocationStephane Viau2015-02-01
| | | | | | | | | In case we request a number of SMP blocks which is lower than the already reserved blocks, we should not try to allocate a negative number, but 0 blocks instead. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add hardware cursor supportBeeresh Gopal2015-02-01
| | | | | | | | | | This patch implements the hardware accelarated cursor support for MDP5 platforms. Signed-off-by: Beeresh Gopal <gbeeresh@codeaurora.org> Signed-off-by: Wentao Xu <wentaox@codeaurora.org> Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: fix parameter type for mdp5_ctl_set_intf()Stephane Viau2015-02-01
| | | | | | | | mdp5_ctl_set_intf()'s second argument should be "int", not "enum mdp5_intf". The passed in value is "intf", not "intf_id". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Add the eDP connector in msm drm driver (V2)Hai Li2015-02-01
| | | | | | | | | | | | Modified the hard-coded hdmi connector/encoder implementations in msm drm driver to support both edp and hdmi. V1: Initial change V2: Address Thierry's change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: add YUV format supportBeeresh Gopal2015-02-01
| | | | | | | | | The patch add support for YUV frame format for MDP4 platform. Signed-off-by: Beeresh Gopal <gbeeresh@codeaurora.org> Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: add NV12 support for MDP5Stephane Viau2015-02-01
| | | | | | | This change adds the NV12 format support for public planes. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp: add common YUV information for MDP4/MDP5Stephane Viau2015-02-01
| | | | | | | | | Both MDP4 and MDP5 share some code as far as YUV support is concerned. This change adds this information and will be followed by the actual MDP4 and MDP5 YUV support patches. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-02-01
| | | | | | | | | | Resync from rnndb database, to pull in register defines for: * eDP * HDMI/HDCP * mdp4/mdp5 YUV support * mdp5 hw cursor support Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Do not BUG_ON(!spin_is_locked()) on UPBruno Prémont2015-02-01
| | | | | | | | | | | | | | | On !SMP systems spinlocks do not exist. Thus checking of they are active will always fail. Use assert_spin_locked(lock); instead of BUG_ON(!spin_is_locked(lock)); to not BUG() on all UP systems. Signed-off-by: Bruno Prémont <bonbons@linux-vserver.org> [robclark: drop stray ')'] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix fallout of atomic dpms changesRob Clark2015-02-01
| | | | | | | | | | | | | | | | | | | | | As a result of atomic DPMS support, the various prepare/commit hooks get called in a way that msm dislikes. We were expecting prepare/commit to bracket a modeset, which is no longer the case. This was needed to hold various extra clk's (such as interface clks) on while we are touching registers, and in the case of mdp4 holding vblank enabled. The most straightforward way to deal with this, since we already have our own atomic_commit(), is to just handle prepare/commit internally to the driver (with some additional vfuncs for mdp4 vs mdp5), and switch everything over to instead use the new enable/disable hooks. It doesn't really change too much, despite the code motion. What used to be in the encoder/crtc dpms() fxns is split out into enable/disable. We should be able to drop our own enable-state tracking, as the atomic helpers should do this for us. But keeping that for the short term for extra debugging as atomic stablizes. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Remove CRTC .mode_set and .mode_set_base helpersLaurent Pinchart2015-02-01
| | | | | | | | | Only the legacy helpers use these entry points. Don't populate them with transitional helpers, since that just makes things more confusing. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> [robclark: reword commit msg] Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'topic/atomic-core-2015-01-05' of ↵Dave Airlie2015-01-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next Next batch of atomic work. Most important is the propertification from Rob and the nth iteration of the actual atomic ioctl originally from Ville. Big differences compared to earlier revisions: - Core properties are now fully handled by the core, drivers can only handle driver-specific properties. - Atomic props&ioctl are opt-in per file_priv, userspace needs to explicitly ask for it (like universal plane support). - For now all hidden behind the atomic module option until this has settled a bit. - Atomic modesets are currently not possible since the exact abi for how to handle the mode property is still under discussion. Besides this some cleanup patches from me and the addition of per-object state to global state backpointers to simplify drivers. * tag 'topic/atomic-core-2015-01-05' of git://anongit.freedesktop.org/drm-intel: drm: Ensure universal_planes is set for atomic drm/atomic: Hide drm.ko internal interfaces drm: Atomic modeset ioctl drm/atomic: atomic connector properties drm/atomic: atomic plane properties drm: small property creation cleanup drm/atomic: atomic_check functions drm: add atomic properties drm: refactor getproperties/getconnector drm: tweak getconnector locking drm: add atomic_get_property drm: add atomic_set_property wrappers drm: get rid of direct property value access drm: store property instead of id in obj attachment drm: allow property validation for refcnted props drm/atomic: Introduce state->obj backpointers drm/atomic-helper: Again check modeset *before* plane states drm/atomic-helper: Export both plane and modeset check helpers
| * Merge branch 'topic/core-stuff' into topic/atomic-coreDaniel Vetter2014-12-17
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge my drm-misc branch because of conflicts. Just simple stuff but better to clear this out before I merge the other atomic patches. Conflicts: drivers/gpu/drm/drm_crtc.c drivers/gpu/drm/drm_edid.c Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * | drm/atomic: Introduce state->obj backpointersDaniel Vetter2014-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Useful since this way we can pass around just the state objects and will get ther real object, too. Specifically this allows us to again simplify the parameters for set_crtc_for_plane. v2: msm already has it's own specific plane_reset hook, don't forget that one! v3: Fixup kerneldoc, reported by 0-day builder. Cc: Rob Clark <robdclark@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> (v2) Tested-by: Rob Clark <robdclark@gmail.com> (v2) Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* | | Merge tag 'topic/core-stuff-2014-12-19' of ↵Dave Airlie2015-01-08
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next Misc drm patches with mostly polish patches from Thierry, with a bit of generic mode validation from Ville and a few other oddball things. * tag 'topic/core-stuff-2014-12-19' of git://anongit.freedesktop.org/drm-intel: (25 commits) drm: Include drm_crtc_helper.h in DocBook drm: Make drm_crtc_helper.h standalone includible drm: Move IRQ related fields to proper section drm: Remove stale comment drm: Do basic sanity checks for user modes drm: Perform basic sanity checks on probed modes drm: Reorganize probed mode validation drm/doc: Remove duplicate "by" drm/info: Remove unused code drm/cache: Use wbinvd helpers drm/plane-helper: Test for plane disable earlier drm/doc: Document drm_add_modes_noedid() usage drm: bit of spell-check / editorializing. drm: Prefer sizeof(type) over sizeof type drm: Remove useless else block drm: Remove unneeded braces for single statement blocks drm: Do not assign in if condition drm: Prefer kmalloc_array() over kmalloc() with multiply drm: Prefer kcalloc() over kzalloc() with multiply drm: Miscellaneous checkpatch whitespace cleanups ...
| * | drm/msm: Remove dummy ->load_lut() implementationThierry Reding2014-12-10
| |/ | | | | | | | | | | | | | | | | The ->load_lut() callback is optional, therefore a dummy implementation is not needed. Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/msm/mdp5: update irqs on crtc<->encoder link changeRob Clark2014-12-18
| | | | | | | | | | | | | | | | | | | | If crtc <-> encoder linkage changes, we could end up with the CRTC listening for the wrong error or vsync irqs. Generally this problem would correct itself relatively quickly, since we update the global irqmask after dispatching irqs, but to be sure let the CRTC trigger update_irq(). Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm: block incoming update on pending updatesRob Clark2014-12-18
|/ | | | | | | | | We can't have multiple updates pending on a given CRTC, and we don't want a sync update to race w/ an async update that preceeded it. So keep track of which CRTCs have updates in flight, and block later updates that would conflict. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: switch to atomic-helpers iterator macrosRob Clark2014-11-27
| | | | | Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/plane: Pass old state to ->atomic_update()Thierry Reding2014-11-25
| | | | | | | | | | | | | | | In most situations it will be useful to have the old state passed to the ->atomic_update() callback. For example if a plane is being disabled the new state's .crtc field will be NULL, but some drivers may rely on this field to program the CRTCs registers. v2: rename variable to old_plane_state and remove redundant comment as suggested by Daniel Vetter, remove an Exynos hunk that doesn't apply to drm-next and add a hunk for pending MSM mdp5 changes Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/msm/mdp4: fix mixer setup for multi-crtc + planesRob Clark2014-11-21
| | | | | | | | | On mdp4 there is a single global LAYERMIXER_IN_CFG register. The previous logic to share that between multiple crtcs didn't actually handle plane-disable very well. Easier just to look at all of the crtcs each time. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: dpms(OFF) cleanupsRob Clark2014-11-21
| | | | | | | | | | | When disabling the interface (INTF), the change doesn't latch until next vblank, so we need to wait for vblank. Also, to be pedantic, in the crtc, set all the mixer stages to unused. It shouldn't really matter, since at this point we have already disabled the INTF and waited for necessary vblank. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: atomicRob Clark2014-11-21
| | | | | | | | | | Convert mdp5 over to atomic helpers. Extend/wrap drm_plane_state to track plane zpos and to keep track of the needed when applying the atomic update. In mdp5's plane->atomic_check() we also need to check for updates which require SMP reallocation, in order to trigger full modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
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