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* drm/msm/mdp5: remove global mdp5_ctl_mgrRob Clark2014-11-21
| | | | | | | A bit cleaner.. and won't resulting in an attempt to kfree() a static global in unload path. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: don't use void * for opaque typesRob Clark2014-11-21
| | | | | | | | | For example, use 'struct mdp5_smp *' everywhere instead of 'void *', but only declare it as 'struct mdp5_smp;' in common headers, so the struct body is still private. The accomplishes the desired modularity while still letting the compiler provide some type checking for us. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add multiple CRTC and overlay supportStephane Viau2014-11-21
| | | | | | | | | MDP5 currently support one single CRTC with its private pipe. This change allows the configuration of multiple CRTCs with the possibility to attach several public planes to these CRTCs. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: set rate before enabling clkRob Clark2014-11-21
| | | | | | | Set a "safe" rate at first, in order to read out the hw revision. And then after set the optimal value. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: introduce mdp5_cfg moduleStephane Viau2014-11-21
| | | | | | | | | | The hardware configuration modification from a version to another is quite consequent. Introducing a configuration module (mdp5_cfg) may make things more clear and easier to access when a new hardware version comes up. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: make SMP module dynamically configurableStephane Viau2014-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Shared Memory Pool (SMP) has its own limitation, features and state. Some examples are: - the number of Memory Macro Block (MMB) and their size - the number of lines that can be fetched - the state of MMB currently allocated - the computation of number of blocks required per plane - client IDs ... In order to avoid private data to be overwritten by other modules, let's make these private to the SMP module. Some of these depend on the hardware configuration, let's add them to the mdp5_config struct. In some hw configurations, some MMBs are statically tied to RGB pipes and cannot be re-allocated dynamically. This change introduces the concept of MMB static usage and makes sure that dynamic MMB requests are dimensioned accordingly. A note on passing a pipe pointer, instead of client IDs: Client IDs are SMP-related information. Passing PIPE information to SMP lets SMP module to find out which SMP client(s) are used. This allows the SMP module to access the PIPE pointer, which can be used for FIFO watermark configuration. By the way, even though REG_MDP5_PIPE_REQPRIO_FIFO_WM_* registers are part of the PIPE registers, their functionality is to reflect the behavior of the SMP block. These registers access is now restricted to the SMP module. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: get the core clock rate from MDP5 configStephane Viau2014-11-21
| | | | | | | | | | | The core clock rate depends on the hw configuration. Once we have read the hardware revision, we can set the core clock to its maximum value. Before then, the clock is set at a rate supported by all MDP5 revisions. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: use irqdomainsRob Clark2014-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mdp5, the irqs of hdmi/eDP/dsi0/dsi1 blocks get routed through the mdp block. In order to decouple hdmi/eDP/etc, register an irq domain in mdp5. When hdmi/dsi/etc are used with mdp4, they can directly setup their irqs in their DT nodes as normal. When used with mdp5, instead set the mdp device as the interrupt-parent, as in: mdp: qcom,mdss_mdp@fd900000 { compatible = "qcom,mdss_mdp"; interrupt-controller; #interrupt-cells = <1>; ... }; hdmi: qcom,hdmi_tx@fd922100 { compatible = "qcom,hdmi-tx-8074"; interrupt-parent = <&mdp>; interrupts = <8 0>; /* MDP5_HW_INTR_STATUS.INTR_HDMI */ ... }; There is a slight awkwardness, in that we cannot disable child irqs at the mdp level, they can only be cleared in the child block. So you must not use threaded irq handlers in the child. I'm not sure if there is a better way to deal with that. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: atomicRob Clark2014-11-16
| | | | | | Convert mdp4 display controller backend to atomic helpers. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: drop attached planes tableRob Clark2014-11-16
| | | | | | | Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: drop attached planes tableRob Clark2014-11-16
| | | | | | | | | Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. TODO move iterator macro somewhere common. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: don't care about fb in crtcRob Clark2014-11-16
| | | | | | | | | Since we are configuring things via MDP4_PIPE regs in the plane, it seems like setting the dimensions of the primary plane on the OVLP/DMA regs in crtc is unnecessary. This will make life easier when we want to do a nofb modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: drop private primary ptrRob Clark2014-11-16
| | | | | | Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: drop private primary ptrRob Clark2014-11-16
| | | | | | Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/hdmi: refactor bind/initRob Clark2014-11-16
| | | | | | | | | | | | Split up hdmi_init() into hdmi_init() (done at hdmi sub-device bind/probe time) and hdmi_modeset_init() done from master driver's modeset_init(). Anything that can fail due to dependencies on other drivers which may be missing or not probed yet should go in hdmi_init(), so that devm error/cleanup paths work properly. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2014-11-16
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: select REGULATORRob Clark2014-11-16
| | | | | | | | | | | | | | | | | | | | | Fixes a potential error, spotted by Felipe with randconfig: ----- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c: In function ‘mdp4_kms_init’: drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:2: error: implicit declaration \ of function ‘devm_regulator_get_exclusive’ [-Werror=implicit-function-declaration] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:16: error: assignment makes \ pointer from integer without a cast [-Werror] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ ----- Also add a brief comment explaining the use of _get_exclusive() Reported-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm: flip-work: change drm_flip_work_init prototypeBoris BREZILLON2014-11-14
| | | | | | | | | | | | | | | | Now that we're using lists instead of kfifo to store drm flip-work tasks we do not need the size parameter passed to drm_flip_work_init function anymore. Moreover this function cannot fail anymore, we can thus remove the return code. Modify drm_flip_work_init users to take account of these changes. [airlied: fixed two unused variable warnings] Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: backmerge tag 'v3.17-rc5' into drm-nextDave Airlie2014-09-15
|\ | | | | | | | | | | | | This is requested to get the fixes for intel and radeon into the same tree for future development work. i915_display.c: fix missing dev_priv conflict.
| * drm/msm/mdp4: request vblank during modesetRob Clark2014-08-26
| | | | | | | | | | | | | | | | | | | | | | This avoids a problem seen with weston (for example) where the display gets stuck in "black screen" if starting weston first thing after boot. Possibly mdp5 needs something similar. The downstream android fbdev driver always requests DMA_E (or DMA_P) when display is active, rather than only enabling it on-demand as the drm driver does, which I believe has the same end result. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm/mdp4: add LVDS panel supportRob Clark2014-09-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LVDS panel support uses the LCDC (parallel) encoder. Unlike with HDMI, there is not a separate LVDS block, so no need to split things into a bridge+connector. Nor is there is anything re-used with mdp5. Note that there can be some regulators shared between HDMI and LVDS (in particular, on apq8064, ext_3v3p), so we should not use the _exclusive() variants of devm_regulator_get(). The drm_panel framework is used for panel-specific driver. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm/mdp4: fix blend setup with multiple crtcsRob Clark2014-09-10
| | | | | | | | | | | | | | | | | | In particular, blend_setup() should not overwrite the other crtc's mixer settings. Also, the encoder needs to be able to specify the mixer-id explicitly, since both LVDS and DTV use 'INTF_LVDC_DTV', so we cannot guess the mixer-id from the interface. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm/msm: update generated headersRob Clark2014-09-10
|/ | | | | | | In particular, pick up the definitions for a handful of LVDS related registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: add support for MDP5 v1.3Stephane Viau2014-08-04
| | | | | | | | | | | | | | | | | | | MDP5 has several functional blocks (ie: VIG/RGB pipes, LMs, ...). From one revision to another, these blocks' base addresses might change due to the number of instances present in the MDP5 hw. A way of dealing with these offset changes is to introduce dynamic offsets 'per block'. This change adds support for the new revision of MDP5: v1.3. The idea is to define one hw config per MDP version and select either one of them at runtime, after reading the MDP5 version. Once the MDP version is known, 'per block' dynamic offsets are initialized through a global pointer, which is then used for read/write register access. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: use upstream iommuRob Clark2014-08-04
| | | | | | | | | | | | | | | | | Downstream kernel IOMMU had a non-standard way of dealing with multiple devices and multiple ports/contexts. We don't need that on upstream kernel, so rip out the crazy. Note that we have to move the pinning of the ringbuffer to after the IOMMU is attached. No idea how that managed to work properly on the downstream kernel. For now, I am leaving the IOMMU port name stuff in place, to simplify things for folks trying to backport latest drm/msm to device kernels. Once we no longer have to care about pre-DT kernels, we can drop this and instead backport upstream IOMMU driver. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix BUG_ON() in error cleanup pathRob Clark2014-08-04
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: add mdp axi clkRob Clark2014-08-04
| | | | | | | Downstream kernel holds this clk via a fake-parent relationship. Upstream clock framework requires that we hold it explicitly. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2014-08-04
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: DT support for 8960/8064 (v3)Rob Clark2014-08-04
| | | | | | | | | | Now that we (almost) have enough dependencies in place (MMCC, RPM, etc), add necessary DT support so that we can use drm/msm on upstream kernel. v2: update for review comments v3: rebase on component helper changes Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: activate iommu supportStephane Viau2014-08-04
| | | | | | | | This changes activates the iommu support for MDP5, through the platform config structure. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix IOMMU cleanup for -EPROBE_DEFERStephane Viau2014-06-22
| | | | | | | | | If probe fails after IOMMU is attached, we need to detach in order to clean up properly. Before this change, IOMMU faults would occur if the probe failed (-EPROBE_DEFER). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: fix error return valueRob Clark2014-06-02
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: remove redundant private plane cleanupRob Clark2014-06-02
| | | | | | | Now that drm core knows about private planes, it cleans them up for us. Trying to do this twice results in badness. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: fix crash in error/unload pathsRob Clark2014-05-30
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: cure for the cursor blues (v2)Rob Clark2014-04-25
| | | | | | | | | | | | | | | | | | The hw cursor is relatively adept at triggering underflows, which manifest as a "blue flash" (since blue is configured as the underflow color). Juggle a few things around to tighten up the timing for setting cursor registers in DONE irq. And most importantly, don't ever disable the hw cursor. Instead flip it to a blank/empty cursor. This seems far more reliable, as even simply clearing the cursor-enable bit (with no other updates in previous/ following frames) can in some cases cause underflow. v1: original v2: add missing locking spotted by Micah Cc: Micah Richert <richert@braincorporation.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into ↵Dave Airlie2014-04-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-next * 'msm-next' of git://people.freedesktop.org/~robclark/linux: drm/omap: Don't dereference list head when the connectors list is empty drm/msm/mdp: add timeout for irq wait drm/msm: validate flags, etc drm/msm: use componentised device support drm/msm: add chip-id param drm/msm: crank down gpu when inactive drm/msm: spin helper drm/msm: add hang_debug module param drm/msm: hdmi audio support
| * drm/msm/mdp: add timeout for irq waitRob Clark2014-03-31
| | | | | | | | | | | | | | Make things recover a bit more gracefully if we get stuck with no vblank irq ever coming. Signed-off-by: Rob Clark <robdclark@gmail.com>
* | drm: Replace crtc fb with primary plane fb (v3)Matt Roper2014-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that CRTC's have a primary plane, there's no need to track the framebuffer in the CRTC. Replace all references to the CRTC fb with the primary plane's fb. This patch was generated by the Coccinelle semantic patching tool using the following rules: @@ struct drm_crtc C; @@ - (C).fb + C.primary->fb @@ struct drm_crtc *C; @@ - (C)->fb + C->primary->fb v3: Generate patch via coccinelle. Actual removal of crtc->fb has been moved to a subsequent patch. v2: Fixup several lingering crtc->fb instances that were missed in the first patch iteration. [Rob Clark] Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rob Clark <robdclark@gmail.com>
* | drm/msm: Switch to universal plane API'sMatt Roper2014-04-01
|/ | | | | | | | | | | Use drm_universal_plane_init() and drm_crtc_init_with_planes() rather than the legacy drm_plane_init() / drm_crtc_init(). This will ensure that the proper primary plane is registered with the DRM (and eventually exposed to userspace in future patches). Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: cursor fixesRob Clark2014-02-05
| | | | | | | | It seems we need to update all cursor registers from vblank. This appears to be the cause of intermittent underflows when enabling/ disabling cursor. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: pageflip fixesRob Clark2014-02-05
| | | | | | | | | | | | | | | | | Backport a few fixes found in the course of getting mdp5 working. There is a window of time after pageflip is requested, before we start scanning out the new fb (ie. while we are waiting for gpu). During that time we need to continue holding a reference to the still-current scanout fb, to avoid the backing gem bo's from being destroyed. Possibly a common mdp_crtc parent class could be useful to share some of this logic between mdp4_crtc and mdp5_crtc. OTOH, this all can be removed from the driver once atomic is in place, as plane/crtc updates get deferred until all fb's are ready before calling in to .page_flip(), etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: fix ref leaks in error pathsRob Clark2014-02-05
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix inconsequential typoRob Clark2014-02-05
| | | | | | | Small typo I noticed in the mdp4_plane code.. no consequence because PIPE_SRC_XY and PIPE_DST_XY have same register layout. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add mdp5/apq8x74Rob Clark2014-01-09
| | | | | | | | | | | | | | | | | | | | | | | Add support for the new MDP5 display controller block. The mapping between parts of the display controller and KMS is: plane -> PIPE{RGBn,VIGn} \ crtc -> LM (layer mixer) |-> MDP "device" encoder -> INTF / connector -> HDMI/DSI/eDP/etc --> other device(s) Unlike MDP4, it appears we can get by with a single encoder, rather than needing a different implementation for DTV, DSI, etc. (Ie. the register interface is same, just different bases.) Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are routed through MDP. And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from which blocks need to be allocated to the active pipes based on fetch stride. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add hdmi support for apq8x74/mdp5Rob Clark2014-01-09
| | | | | | | | | | | | | | | | The HDMI block is basically the same between older SoC's with mdp4 display controller, and newer ones with mdp5. So mostly this consists of better abstracting out the different sets of regulators, clks, etc. In particular, for regulators and clks we can split it up by what is needed for hot plug detect to work, and what is needed to light up the display. Also, 8x74 has a new phy.. a very simple one, but split out into a different mmio space. And with mdp5, the irq is shared with mdp, so we don't directly register our own irq handler. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: move irq utils to mdp_kmsRob Clark2014-01-09
| | | | | | | We'll want basically the same thing for mdp5, so refactor it out so it can be shared. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: split out msm_kms.hRob Clark2014-01-09
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: mdp4_format -> mdp_formatRob Clark2014-01-09
| | | | | | | This can be shared between mdp4 and mdp5. Both use the same set of parameters to describe the format to the hw. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: resync generated headersRob Clark2014-01-09
| | | | | | resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: move mdp4 -> mdp/mdp4Rob Clark2014-01-09
There are some little bits and pieces that mdp4 and mdp5 can share, so move things around so that we can have both in a common parent directory. Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-06 19:07:44 -0400