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path: root/drivers/gpu/drm/i915/i915_drv.h
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* drm/i915: Move gpu_write_list to per-ringChris Wilson2010-10-24
| | | | | | | | | | ... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-21
| | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Enable SandyBridge blitter ringChris Wilson2010-10-21
| | | | | | | | Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Track objects in global active list (as well as per-ring)Chris Wilson2010-10-20
| | | | | | | | | | | To handle retirements, we need per-ring tracking of active objects. To handle evictions, we need global tracking of active objects. As we enable more rings, rebuilding the global list from the individual per-ring lists quickly grows tiresome and overly complicated. Tracking the active objects in two lists is the lesser of two evils. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/dp: cache eDP DPCD dataJesse Barnes2010-10-08
| | | | | | | | Cache the first 4 bytes of DPCD data in the eDP case. It's unlikely to change and can save us some trouble at link training time. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fetch eDP configuration data from the VBTJesse Barnes2010-10-08
| | | | | | | | We need to use some of these values in eDP configurations, so be sure to fetch them and store them in the i915 private structure. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: add _DSM supportJesse Barnes2010-10-08
| | | | | | | | | | | The _DSM method on the integrated graphics device can tell us which connectors are muxable, so add support for making the call and parsing out the connector info. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: fix compiler warnings for using uninitialized 'result' and downgrade error message for non-switchable devices] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: If the GPU hangs twice within 5 seconds, declare it wedged.Chris Wilson2010-10-01
| | | | | | | | | | The issue is that we may become stuck executing a long running shader and continually attempt to reset the GPU. (Or maybe we tickle some bug and need to break the vicious cycle.) So if we are detect a second hang within 5 seconds, give up trying to programme the GPU and report it wedged. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Clear fence registers on GPU resetChris Wilson2010-10-01
| | | | | | | When the GPU is reset, the fence registers are invalidated, so release the objects and clear them out. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm: Move the GTT accounting to i915Chris Wilson2010-10-01
| | | | | | | | | Only drm/i915 does the bookkeeping that makes the information useful, and the information maintained is driver specific, so move it out of the core and into its single user. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Airlie <airlied@redhat.com>
* drm/i915: Make get/put pages staticChris Wilson2010-09-30
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debug: Convert i915_verify_active() to scan all listsChris Wilson2010-09-30
| | | | | | ... and check more regularly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debug: Remove default WATCH_BUFChris Wilson2010-09-29
| | | | | | Replaced by tracepoints. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debug: Remove defunct WATCH_LRUChris Wilson2010-09-29
| | | | | | This has bitrotted through inuse and superseded by tracing and debugfs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Disable LVDS i2c probing when using GPIO bit bangingChris Wilson2010-09-28
| | | | | | | This check only appears to succeed when using GMBUS, so we need to skip it if we have fallen back to using GPIO bit banging. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/sdvo: Fix GMBUSificationChris Wilson2010-09-28
| | | | | | | | Besides a couple of bugs when writing more than a single byte along the GMBUS, SDVO was completely failing whilst trying to use GMBUS, so use bit banging instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Convert the file mutex into a spinlockChris Wilson2010-09-26
| | | | | | | | Daniel Vetter pointed out that in this case is would be clearer and cleaner to use a spinlock instead of a mutex to protect the per-file request list manipulation. Make it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Adjust hangcheck EIO semanticsChris Wilson2010-09-25
| | | | | | | | | | | | | | | | | Owain Ainsworth reported an issue between the interaction of the hangcheck and userspace immediately (and permanently) falling back to s/w rasterisation. In order to break the mutex and begin resetting the GPU, we must abort the current operation (usually within the wait) and climb sufficiently far back up the call chain to drop the mutex. In his implementation, Owain has a loop within the ioctl handler to detect the hang and then sleep until the error handler has run. I've chosen to return to userspace and report an EAGAIN which should trigger the userspace ioctl handler to repeat the call (simply because it felt less invasive...). Before hitting a wedged GPU, we then wait upon completion of the error handler. Reported-by: Owain G. Ainsworth <zerooa@googlemail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only hold a process-local lock whilst throttling.Chris Wilson2010-09-24
| | | | | | | | | Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Parse the eDP link configuration from the vBIOSChris Wilson2010-09-24
| | | | | | | First step, lets have a look at the values for troublesome panels and see if they may be used to improve our link training. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Use an uninterruptible wait for page-flips during modesetChris Wilson2010-09-24
| | | | | | | We need to drain the pending flips prior to disabling the pipe during modeset, and these need to be done in an uninterruptible fashion. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove unused dev_priv->panel_wants_ditherChris Wilson2010-09-24
| | | | | | | This is now private to the DVO connector, remove it from the main device private. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove the broken flush_ring from page-flipChris Wilson2010-09-23
| | | | | | | | | This is already performed with the pipelined flush, so by the time we schedule the flush in the page-flip, the ring is NULL and we OOPs instead. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Clear the gpu_write_list on resetting write_domain upon hangChris Wilson2010-09-22
| | | | | | | Otherwise we will hit a list handling assertion when moving the object to the inactive list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Track pinned objectsChris Wilson2010-09-21
| | | | | | | | Keep a list of pinned objects and display it via debugfs. Now all objects that exist in the GTT are always tracked on one of the active, flushing, inactive or pinned lists. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Drain any pending flips on the fb prior to unpinningChris Wilson2010-09-21
| | | | | | | | If we have queued a page flip on the current fb and then request a mode change, wait until the page flip completes before performing the new request. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Merge ring flushing and lazy requestsChris Wilson2010-09-21
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Track gpu fence usageChris Wilson2010-09-21
| | | | | | | | Track if the gpu requires the fence for the execution of a batch buffer and so only wait upon the retirement of the object's last rendering seqno if the fence is in use by the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Use ring->flush() instead of MI_FLUSHChris Wilson2010-09-21
| | | | | | | Use the ring abstraction to hide the details of having choose the appropriate flushing method. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fix HAS_BSD with a device info flagXiang, Haihao2010-09-21
| | | | | | Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Clean up bo lists on all hung gpusChris Wilson2010-09-21
| | | | | | | | | | Previously we only tidied up the active bo lists for chipsets were we would attempt to reset the GPU. However, this action is necessary for the system to continue and reclaim the dead bo for all chipsets. Pointed out, in passing, by Owain Ainsworth. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Clear GPU read domains on resetChris Wilson2010-09-21
| | | | | | | Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Clear flushing lists on GPU resetChris Wilson2010-09-21
| | | | | | | Owain Ainsworth noticed that the reset code failed to clear the flushing list leaving the driver in an inconsistent state following a hung GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only emit a flush request on the active ring.Chris Wilson2010-09-21
| | | | | | | | When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson2010-09-21
| | | | | | | Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use GMBUS to manage i2c linksChris Wilson2010-09-18
| | | | | | | | | | | | | | Use the GMBUS interface rather than direct bit banging to grab the EDID over DDC (and for other forms of auxiliary communication with external display controllers). The hope is that this method will be much faster and more reliable than bit banging for fetching EDIDs from buggy monitors or through switches, though we still preserve the bit banging as a fallback in case GMBUS fails. Based on an original patch by Jesse Barnes. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Allow get_fence_reg() to be uninterruptibleChris Wilson2010-09-14
| | | | | | | | As we currently may need to acquire a fence register during a modeset, we need to be able to do so in an uninterruptible manner. So expose that parameter to the callers of the fence management code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Push pipelining of display plane flushes to the callerChris Wilson2010-09-14
| | | | | | | This ensures that we do wait upon the flushes to complete if necessary and avoid the visual tears, whilst enabling pipelined page-flips. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Consolidate flushing the display planeChris Wilson2010-09-14
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Reduce hangcheck frequencyChris Wilson2010-09-14
| | | | | | | | | | | | | By reducing the hangcheck frequency we check less often, conserving resources, and still detect a lock up quickly. On a fast machine with a slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to misfire as we check too fast. Also once hung and if we fail to completely reset the chip, we have a nasty habit of proclaming a hang many times a second and generating a strobe-like display. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/lvds: Move private data to the connector from the device.Chris Wilson2010-09-13
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Fix updating FBCChris Wilson2010-09-11
| | | | | | | We need to track different state on each generation in order to detect when we need to refresh the FBC registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: die, i915_probe_agp, dieDaniel Vetter2010-09-08
| | | | | | | | | | | | | | | Use the detection from intel-gtt.ko instead. Hooray! Also move the stolen mem allocator to the other gtt stuff in dev_prv->mem. v2: Chris Wilson noted that my error handling was crap. Fix it. He also said that this fixes a problem on his i845. Indeed, i915_probe_agp misses a special case for i830/i845 stolen mem detection. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25476 Cc: stable@kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: introduce drm/intel-gtt.hDaniel Vetter2010-09-08
| | | | | | | | | Add a few definitions to it that are already shared and that will be shared in the future (like the number of stolen entries). No functional changes in here. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Refactor panel backlight controlsChris Wilson2010-09-08
| | | | | | | | | | | | | | | | | | There were two instances of code to control the panel backlight and neither handled the complete set of device variations. Fixes: Bug 29716 - [GM965] Regression: Backlight resets to minimum when changing resolution https://bugs.freedesktop.org/show_bug.cgi?id=29716 And a bug on one of my PineView boxes which overflowed the backlight value. Incorporates part of a similar patch by Matthew Garrett that exposes a native Intel backlight controller. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Kill the active list spinlockChris Wilson2010-09-08
| | | | | | | | | | This spinlock only served debugging purposes in a time when we could not be sure of the mutex ever being released upon a GPU hang. As we now should be able rely on hangcheck to do the job for us (and that error reporting should not itself require the struct mutex) we can kill the incomplete attempt at protection. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Compile out error state without DEBUG_FSChris Wilson2010-09-08
| | | | | | | | | | | Alexander reported that the compilation of intel_overlay.c was failing due to an inclusion that was only valid with CONFIG_DEBUG_FS. As the whole error reporting is only useful with debugfs enabled, remove all the redundant error state collection code when compiling without CONFIG_DEBUG_FS. Reported-by: Alexander Lam <lambchop468@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Preallocate requestsChris Wilson2010-09-08
| | | | | | | | By allocating the request prior to writing to the ringbuffer, we can abort the operation without leaving the GPU in an inconsistent state. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/overlay: Move capabilities bits to common info block.Chris Wilson2010-09-08
| | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: move flushing list processing to i915_retire_commandsDaniel Vetter2010-09-08
| | | | | | | | | | | | | | | ... instead of threading flush_domains through the execbuf code to i915_add_request. With this change 2 small cleanups are possible (likewise the majority of the patch): - The flush_domains parameter of i915_add_request is always 0. Drop it and the corresponding logic. - Ditto for the seqno param of i915_gem_process_flushing_list. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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