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* m68knommu: merge old ColdFire interrupt controller masking macrosGreg Ungerer2009-09-15
| | | | | | | | | | Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove duplicate ColdFire mcf_autovector() codeGreg Ungerer2009-09-15
| | | | | | | | | Each of the ColdFire CPU platform code that used the old style interrupt controller had its own copy of the mcf_autovector() function. They are all the same, remove them all and create a single function in the common coldfire/intc.c code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: move ColdFire INTC definitions to new include fileGreg Ungerer2009-09-15
| | | | | | | | Create an mcfintc.h include file with the definitions for the old style ColdFire interrupt controller. They are only needed on CPU's that use this old controller - so isolate them on their own. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: mask off all interrupts in ColdFire intc-simr controllerGreg Ungerer2009-09-15
| | | | | | | | The ColdFire intc-simr interrupt controller should mask off all interrupt sources at init time. Doing it here instead of separately in each platform setup. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove timer device interrupt setup for ColdFire 532xGreg Ungerer2009-09-15
| | | | | | | | With fully implemented interrupt controller code we don't need to do the custom interrupt setup for the timer device of the ColdFire 532x. Remove that code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove interrupt masking from ColdFire pit timerGreg Ungerer2009-09-15
| | | | | | | | With proper interrupt controller code in place there is no need for devices like the timers to have custom interrupt masking code. Remove it (and the defines that go along with it). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove unecessary interrupt level setting in ColdFire 520x setupGreg Ungerer2009-09-15
| | | | | | | | | The new code for the interrupt controller in the ColdFire 520x takes care of all the interrupt controller setup. No manual config of the level registers (ICR) is required by the platform device setup code. So remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove the common interrupt controller structureGreg Ungerer2009-09-15
| | | | | | | | Each different m68knommu CPU interrupt controller type has its own interrupt controller data structures now. Remove the old, and now not used, common irq structs and init code from here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: complete interrupt controller code for the 68360 CPUGreg Ungerer2009-09-15
| | | | | | | | Define the interrupt controller structures along with the interrupt controller code for the 68360 CPU. This brings the interrupt setup and control into one place for this CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: complete interrupt controller code for the 68328 CPU'sGreg Ungerer2009-09-15
| | | | | | | | Define the interrupt controller structures along with the interrupt controller code for the 68328 CPU family. This brings the interrupt setup and control into one place for this CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: use common interrupt controller code for older ColdFire CPU'sGreg Ungerer2009-09-15
| | | | | | | | | The old ColdFire CPU's (5206, 5307, 5407, 5249 etc) use a simple interrupt controller. Use common setup code for them. This addition means that all ColdFire CPU's now have some specific type of interrupt controller code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up ColdFire 532x interrupt setupGreg Ungerer2009-09-15
| | | | | | | | With the common intc-simr interrupt controller code in place the ColdFire 532x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: general interrupt controller for ColdFire 532x partsGreg Ungerer2009-09-15
| | | | | | | | | The ColdFire 532x family of parts uses 2 of the same INTC interrupt controlers used in the ColdFire 520x family. So modify the code to support both parts. The extra code for the second INTC controler in the case of the 520x is easily optimized away to nothing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up ColdFire 523x interrupt setupGreg Ungerer2009-09-15
| | | | | | | | With the common intc-2 interrupt controller code in place the ColdFire 523x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up ColdFire 528x interrupt setupGreg Ungerer2009-09-15
| | | | | | | | With the common intc-2 interrupt controller code in place the ColdFire 528x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up ColdFire 527x interrupt setupGreg Ungerer2009-09-15
| | | | | | | | With the common intc-2 interrupt controller code in place the ColdFire 527x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: general interrupt controller for ColdFire many 52xx partsGreg Ungerer2009-09-15
| | | | | | | | | | | | Create general interrupt controller code for the many ColdFire version 2 cores that use the two region INTC interrupt controller. This includes the 523x family, 5270, 5271, 5274, 5275, and the 528x families. This code does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: remove per device interrupt mask setting for ColdFire 520xGreg Ungerer2009-09-15
| | | | | | | With general interrupt controller code in place we don't need specific unmasking code for the internal ColdFire 520x UARTs or ethernet (FEC). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: use general interrupt controller for ColdFire 520x familyGreg Ungerer2009-09-15
| | | | | | | | | | | | | | | | | | Create general interrupt controller code for the ColdFire 520x family, that does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Within the ColdFire family there is a variety of different interrupt controllers in use. Some are used on multiple parts, some on only one. There is quite some differences in some varients, so much so that common code for all ColdFire parts would be impossible. This commit introduces code to support one of the newer interrupt controllers in the ColdFire 5208 and 5207 parts. It has very simple mask and unmask operations, so is one of the easiest to support. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: clean up comment delimiters in dma.hGreg Ungerer2009-09-15
| | | | | | Change C99 style comments to traditional K&R style. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge mmu and non-mmu versions of dma.hGreg Ungerer2009-09-15
| | | | | | | | The non-mmu version of dma.h contains a lot of ColdFire specific DMA support, but also all of the base m68k support. So use the non-mmu version of dma.h for all. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge the mmu and non-mmu versions of checksum.hGreg Ungerer2009-09-15
| | | | | | | The mmu and non-mmu versions of checksum.h are mostly the same, merge them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge mmu and non-mmu versions of irq.hGreg Ungerer2009-09-15
| | | | | | | It is reasonably strait forward to merge the mmu and non-mmu versions of irq.h. Most of the defines and structs are not needed on non-mmu. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge mmu and non-mmu versions of processor.hGreg Ungerer2009-09-15
| | | | | | | | The mmu and non-mmu versions of processor.h have a lot of common code. This is a strait forward merge. start_thread() could be improved, but that is not quite as strait forward, leaving for a follow on change. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: convert to asm-generic/hardirq.hChristoph Hellwig2009-09-15
| | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: remove unused elia.h include fileGreg Ungerer2009-09-15
| | | | Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* arch/m68knommu/kernel/time.c: Remove unnecessary semicolonsJoe Perches2009-09-15
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support misc files.sfking@fdwdc.com2009-09-09
| | | | | | | The definition of MCFSIM_PADDR and MCFSIM_PADAT now has MCF_BAR already added in. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 5407.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5407. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 532x.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 532x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 5307.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5307. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 528x.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 5272.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5272. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 527x.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5271 & 5275. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 5249.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5249. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 523x.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 520x.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 520x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldire 5206e.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5206e. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* generic GPIO support for the Freescale Coldfire 5206.sfking@fdwdc.com2009-09-09
| | | | | | | Add support for the 5206. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* core generic GPIO support for Freescale Coldfire processors.sfking@fdwdc.com2009-09-09
| | | | | | | This adds the basic infrastructure used by all of the different Coldfire CPUs. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* powerpc: Fix i8259 interrupt driver kernel crash on ML510Roderick Colenbrander2009-09-05
| | | | | | | | | | | | This patch fixes a null pointer exception caused by removal of 'ack()' for level interrupts in the Xilinx interrupt driver. A recent change to the xilinx interrupt controller removed the ack hook for level irqs. Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'release' of ↵Linus Torvalds2009-09-05
|\ | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] fix csum_ipv6_magic() [IA64] Fix warning in dma-mapping.c
| * [IA64] fix csum_ipv6_magic()Jiri Bohac2009-09-02
| | | | | | | | | | | | | | | | | | | | | | The 32-bit parameters (len and csum) of csum_ipv6_magic() are passed in 64-bit registers in2 and in4. The high order 32 bits of the registers were never cleared, and garbage was sometimes calculated into the checksum. Fix this by clearing the high order 32 bits of these registers. Signed-off-by: Jiri Bohac <jbohac@suse.cz> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Fix warning in dma-mapping.cLuck, Tony2009-09-02
| | | | | | | | | | | | | | | | | | | | arch/ia64/kernel/dma-mapping.c:14: warning: control reaches end of non-void function arch/ia64/kernel/dma-mapping.c:14: warning: no return statement in function returning non-void This warning was introduced by commit: 390bd132b2831a2ad0268e84bffbfc0680debfe5 Add dma_debug_init() for ia64 Signed-off-by: Tony Luck <tony.luck@intel.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2009-09-05
|\ \ | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6: sparc64: Fix bootup with mcount in some configs. sparc64: Kill spurious NMI watchdog triggers by increasing limit to 30 seconds.
| * | sparc64: Fix bootup with mcount in some configs.David S. Miller2009-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Functions invoked early when booting up a cpu can't use tracing because mcount requires a valid 'current_thread_info()' and TLB mappings to be setup. The code path of sun4v_register_mondo_queues --> register_one_mondo is one such case. sun4v_register_mondo_queues already has the necessary 'notrace' annotation, but register_one_mondo does not. Normally register_one_mondo is inlined so the bug doesn't trigger, but with some config/compiler combinations, it won't be so we must properly mark it notrace. While we're here, add 'notrace' annoations to prom_printf and prom_halt so that early error handling won't have the same problem. Reported-by: Alexander Beregalov <a.beregalov@gmail.com> Reported-by: Leif Sawyer <lsawyer@gci.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | sparc64: Kill spurious NMI watchdog triggers by increasing limit to 30 seconds.David S. Miller2009-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a compromise and a temporary workaround for bootup NMI watchdog triggers some people see with qla2xxx devices present. This happens when, for example: CPU 0 is in the driver init and looping submitting mailbox commands to load the firmware, then waiting for completion. CPU 1 is receiving the device interrupts. CPU 1 is where the NMI watchdog triggers. CPU 0 is submitting mailbox commands fast enough that by the time CPU 1 returns from the device interrupt handler, a new one is pending. This sequence runs for more than 5 seconds. The problematic case is CPU 1's timer interrupt running when the barrage of device interrupts begin. Then we have: timer interrupt return for softirq checking pending, thus enable interrupts qla2xxx interrupt return qla2xxx interrupt return ... 5+ seconds pass final qla2xxx interrupt for fw load return run timer softirq return At some point in the multi-second qla2xxx interrupt storm we trigger the NMI watchdog on CPU 1 from the NMI interrupt handler. The timer softirq, once we get back to running it, is smart enough to run the timer work enough times to make up for the missed timer interrupts. However, the NMI watchdogs (both x86 and sparc) use the timer interrupt count to notice the cpu is wedged. But in the above scenerio we'll receive only one such timer interrupt even if we last all the way back to running the timer softirq. The default watchdog trigger point is only 5 seconds, which is pretty low (the softwatchdog triggers at 60 seconds). So increase it to 30 seconds for now. Signed-off-by: David S. Miller <davem@davemloft.net>
* | | Merge branch 'perfcounters-fixes-for-linus' of ↵Linus Torvalds2009-09-05
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perfcounters-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf_counter/powerpc: Fix cache event codes for POWER7 perf_counter: Fix /0 bug in swcounters perf_counters: Increase paranoia level
| * | perf_counter/powerpc: Fix cache event codes for POWER7Paul Mackerras2009-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I had the codes for L1 D-cache load accesses and misses swapped around, and the wrong codes for LL-cache accesses and misses. This corrects them. Reported-by: Corey Ashford <cjashfor@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: <stable@kernel.org> LKML-Reference: <19103.8514.709300.585484@cargo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | parisc: fix warning in traps.cGrant Grundler2009-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tue, Aug 18, 2009 at 01:45:17PM -0400, John David Anglin wrote: > CC arch/parisc/kernel/traps.o > arch/parisc/kernel/traps.c: In function 'handle_interruption': > arch/parisc/kernel/traps.c:535:18: warning: operation on 'regs->iasq[0]' > may be undefined Yes - Line 535 should use both [0] and [1]. Reported-by: John David Anglin <dave@hiauly1.hia.nrc.ca> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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