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authorsfking@fdwdc.com <sfking@fdwdc.com>2009-06-19 21:11:04 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-09 22:01:22 -0400
commita03ce7d9ef05e145ef706f99e68d5ffacf0ad325 (patch)
treef654f0374276f65f9d61f80204b81949d1845168 /arch
parentafde8560b4217338c17b7dbc9e9d7676c1b3a5ff (diff)
generic GPIO support for the Freescale Coldfire 523x.
Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/m68k/include/asm/m523xsim.h77
-rw-r--r--arch/m68knommu/platform/523x/Makefile2
-rw-r--r--arch/m68knommu/platform/523x/gpio.c283
3 files changed, 361 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 55183b5df1b8..a34894cf8e6f 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -50,5 +50,82 @@
50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
52 52
53#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
54#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
55#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
56#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
57#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
58#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
59#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
60#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
61#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
62#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
63#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
64#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
65#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
66
67#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
68#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
69#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
70#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
71#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
72#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
73#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
74#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
75#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
76#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
77#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
78#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
79#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
80
81#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
82#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
83#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
84#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
85#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
86#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
87#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
88#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
89#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
90#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
91#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
92#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
93#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
94
95#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
96#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
97#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
98#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
99#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
100#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
101#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
102#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
103#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
104#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
105#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
106#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
107#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
108
109/*
110 * EPort
111 */
112
113#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
114#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
115#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
116
117/*
118 * Generic GPIO support
119 */
120#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
121#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
122#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
123#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
124#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
125
126#define MCFGPIO_PIN_MAX 107
127#define MCFGPIO_IRQ_MAX 8
128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
129
53/****************************************************************************/ 130/****************************************************************************/
54#endif /* m523xsim_h */ 131#endif /* m523xsim_h */
diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile
index 5694d593f029..b8f9b45440c2 100644
--- a/arch/m68knommu/platform/523x/Makefile
+++ b/arch/m68knommu/platform/523x/Makefile
@@ -14,4 +14,4 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c
new file mode 100644
index 000000000000..f02840d54d3c
--- /dev/null
+++ b/arch/m68knommu/platform/523x/gpio.c
@@ -0,0 +1,283 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "ADDR",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 13,
49 .ngpio = 3,
50 },
51 .pddr = MCFGPIO_PDDR_ADDR,
52 .podr = MCFGPIO_PODR_ADDR,
53 .ppdr = MCFGPIO_PPDSDR_ADDR,
54 .setr = MCFGPIO_PPDSDR_ADDR,
55 .clrr = MCFGPIO_PCLRR_ADDR,
56 },
57 {
58 .gpio_chip = {
59 .label = "DATAH",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = MCFGPIO_PDDR_DATAH,
70 .podr = MCFGPIO_PODR_DATAH,
71 .ppdr = MCFGPIO_PPDSDR_DATAH,
72 .setr = MCFGPIO_PPDSDR_DATAH,
73 .clrr = MCFGPIO_PCLRR_DATAH,
74 },
75 {
76 .gpio_chip = {
77 .label = "DATAL",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 8,
86 },
87 .pddr = MCFGPIO_PDDR_DATAL,
88 .podr = MCFGPIO_PODR_DATAL,
89 .ppdr = MCFGPIO_PPDSDR_DATAL,
90 .setr = MCFGPIO_PPDSDR_DATAL,
91 .clrr = MCFGPIO_PCLRR_DATAL,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 8,
104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BS",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_BS,
124 .podr = MCFGPIO_PODR_BS,
125 .ppdr = MCFGPIO_PPDSDR_BS,
126 .setr = MCFGPIO_PPDSDR_BS,
127 .clrr = MCFGPIO_PCLRR_BS,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 7,
140 },
141 .pddr = MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "SDRAM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 6,
158 },
159 .pddr = MCFGPIO_PDDR_SDRAM,
160 .podr = MCFGPIO_PODR_SDRAM,
161 .ppdr = MCFGPIO_PPDSDR_SDRAM,
162 .setr = MCFGPIO_PPDSDR_SDRAM,
163 .clrr = MCFGPIO_PCLRR_SDRAM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UARTH",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 2,
194 },
195 .pddr = MCFGPIO_PDDR_UARTH,
196 .podr = MCFGPIO_PODR_UARTH,
197 .ppdr = MCFGPIO_PPDSDR_UARTH,
198 .setr = MCFGPIO_PPDSDR_UARTH,
199 .clrr = MCFGPIO_PCLRR_UARTH,
200 },
201 {
202 .gpio_chip = {
203 .label = "UARTL",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 8,
212 },
213 .pddr = MCFGPIO_PDDR_UARTL,
214 .podr = MCFGPIO_PODR_UARTL,
215 .ppdr = MCFGPIO_PPDSDR_UARTL,
216 .setr = MCFGPIO_PPDSDR_UARTL,
217 .clrr = MCFGPIO_PCLRR_UARTL,
218 },
219 {
220 .gpio_chip = {
221 .label = "QSPI",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 5,
230 },
231 .pddr = MCFGPIO_PDDR_QSPI,
232 .podr = MCFGPIO_PODR_QSPI,
233 .ppdr = MCFGPIO_PPDSDR_QSPI,
234 .setr = MCFGPIO_PPDSDR_QSPI,
235 .clrr = MCFGPIO_PCLRR_QSPI,
236 },
237 {
238 .gpio_chip = {
239 .label = "TIMER",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 4,
248 },
249 .pddr = MCFGPIO_PDDR_TIMER,
250 .podr = MCFGPIO_PODR_TIMER,
251 .ppdr = MCFGPIO_PPDSDR_TIMER,
252 .setr = MCFGPIO_PPDSDR_TIMER,
253 .clrr = MCFGPIO_PCLRR_TIMER,
254 },
255 {
256 .gpio_chip = {
257 .label = "ETPU",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 3,
266 },
267 .pddr = MCFGPIO_PDDR_ETPU,
268 .podr = MCFGPIO_PODR_ETPU,
269 .ppdr = MCFGPIO_PPDSDR_ETPU,
270 .setr = MCFGPIO_PPDSDR_ETPU,
271 .clrr = MCFGPIO_PCLRR_ETPU,
272 },
273};
274
275static int __init mcf_gpio_init(void)
276{
277 unsigned i = 0;
278 while (i < ARRAY_SIZE(mcf_gpio_chips))
279 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
280 return 0;
281}
282
283core_initcall(mcf_gpio_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 18:08:44 -0500