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* ARM: mach-shmobile: ag5evm needs CONFIG_I2CGuennadi Liakhovetski2011-11-04
| | | | | | | | | | | | | | ag5evm implements a backlight control, using an I2C controller, therefore it needs CONFIG_I2C to fix this make failure arch/arm/mach-shmobile/built-in.o: In function `lcd_on': pfc-sh73a0.c:(.text+0x2334): undefined reference to `i2c_get_adapter' pfc-sh73a0.c:(.text+0x2370): undefined reference to `i2c_transfer' (ignore pfc-sh73a0.c) and to build successfully. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: sh73a0 and AG5EVM PINT supportMagnus Damm2011-11-04
| | | | | | | | | | Support PINT on sh73a0 and AG5EVM using INTC PINT macros. With this patch applied the AG5EVM ethernet is handled through one of the chained sh73a0 PINT interrupt controllers. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Add support for PINT though INTC macrosMagnus Damm2011-11-04
| | | | | | | | Add a INTC_PINT() macro with various helper bits to allow SoCs like sh73a0 to suppor the PINT hardware using regular INTC tables. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: SDHI0 GPIO hotplug for AG5EVMMagnus Damm2011-11-04
| | | | | | | | | | | Implement GPIO hotplugging via TMIO_MMC_HAS_COLD_CD for AG5EVM SDHI0. This is possible now when INTCA is used for IRQ triggering on sh73a0. Without INTCA IRQ support we are left with the GIC hardware block that does not support dealing with active low interrupt sources. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Use common INTC IRQ code on sh73a0Magnus Damm2011-11-04
| | | | | | | | | | | Improve IRQ triggering support by making use of the macro INTC_IRQ_PINS_32() for INTCA on sh73a0. Unfortunately it is not as easy as just using the macro as-is, we need to do mask and unmaks in the GIC but configure other bits and ack in INTCA. Update GPIO IRQ mappings while at it. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Use common INTC IRQ code on sh7372Magnus Damm2011-11-04
| | | | | | | Make use of INTC_IRQ_PINS_32() for INTCA on sh7372. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Use common INTC IRQ code on sh7377Magnus Damm2011-11-04
| | | | | | | Make use of INTC_IRQ_PINS_32() for INTCA on sh7377. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Use common INTC IRQ code on sh7367Magnus Damm2011-11-04
| | | | | | | Make use of INTC_IRQ_PINS_16() for INTCA on sh7367. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: sh73a0 GPIO IRQ supportMagnus Damm2011-11-04
| | | | | | | | | | | | | This patch adds support for sh73a0 GPIO IRQs by making use of the PFC GPIO IRQ feature. Only IRQ pins are supported at this time. In the future when PINT interrupts also are supported properly we can easily extend the table with such information. Also, the sh73a0 is currently making use of the GIC for external interrupt which is rather unflexible when it comes to triggering configuration at this point. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: sh7372 ap4evb NOR Flash USB boot fixBastian Hecht2011-11-04
| | | | | | | | | | | | | Always use CS0 shadow area for NOR flash instead of regular CS0 memory area on ap4evb. When booting from CS0 NOR Flash the regular CS0 memory area is available, but when booting via USB the MASK ROM gets mapped to 0x0 which gets in the way for the NOR Flash. Always using CS0 shadow area works well for both NOR Flash boot and USB boot. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: sh7372 Mackerel NOR Flash USB boot fixMagnus Damm2011-11-04
| | | | | | | | | | | | | Always use CS0 shadow area for NOR flash instead of regular CS0 memory area on Mackerel. When booting from CS0 NOR Flash the regular CS0 memory area is available, but when booting via USB the MASK ROM gets mapped to 0x0 which gets in the way for the NOR Flash. Always using CS0 shadow area works well for both NOR Flash boot and USB boot. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: mach-shmobile: Break out INTC IRQ codeMagnus Damm2011-11-04
| | | | | | | | | Add INTC_IRQ_PINS_16() and INTC_IRQ_PINS_32() to mach/intc.h. These macros define 16 or 32 external IRQ pins on a certain memory base address. Can be used with INTCA or INTCS. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'rmobile/kota2' into rmobile-latestPaul Mundt2011-11-04
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| * ARM: mach-shmobile: Kota2 SDHI0 and SDHI1 supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDHI0 and SDHI1 support to the Kota2 board. SDHI0 is hooked up to a microSD card slot and SDHI1 to a wireless module that also connects to SCIFB. This depends on the recently merged code for TMIO_MMC_HAS_IDLE_WAIT together with PFC support for pull-ups on SDHI0 and SDHI1. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 SCIFA4 and SCIFB supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | Add SCIFA4 and SCIFB support to the Kota2 board. Only pins are configured since the SCIF platform devices are already present in the sh73a0 code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 MMCIF supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | Add support for sh73a0 MMCIF hardware block on the Kota2 board. A non-removable eMMC chip is used with 8 data bits on the MMC bus. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 GPIO LEDs supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | | | | | This patch ties in GPIO LEDs support on the Kota2 board. For now all LEDs are driven by the GPIO LED driver, but in the not so distant future the LEDs hooked up to TPU pin functions will be moved over to the recently posted LED TPU driver. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 GPIO Keys supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | | | This patch ties in GPIO Keys support on the Kota2 board. For now the keys are used in polling mode, but after extending the sh73a0 PFC with IRQ support we should be able to switch to the IRQ driven driver. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 KEYSC supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | This patch adds KEYSC support to the Kota2 board. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * ARM: mach-shmobile: Kota2 SCIFA2 and SMSC911X supportMagnus Damm2011-08-29
| | | | | | | | | | | | | | | | | | | | Kota2 base board support including the on-chip SCIFA2 serial console and the on-board SMSC911X ethernet port. The s73a0 SMP bits are also updated to include Kota2. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | Merge branch 'master' of ↵Paul Mundt2011-11-04
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into rmobile-latest
| * \ Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2011-11-03
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
| | * | MIPS: O32: Provide definition of registers ta0 .. ta3.Ralf Baechle2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | Later IRIX versions provide them in <sys/regdef.h> and gas also accepts $ta0 .. $ta3 since binutils 2.18 so Linux should do the same for source compatibility.
| | * | MIPS: perf: Add Octeon support for hardware perf.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware counters for Octeon, and add the corresponding event mappings. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: perf: Add support for 64-bit perf counters.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hard coded constants are moved to struct mips_pmu. All counter register access move to the read_counter and write_counter function pointers, which are set to either 32-bit or 64-bit access methods at initialization time. Many of the function pointers in struct mips_pmu were not needed as there was only a single implementation, these were removed. I couldn't figure out what made struct cpu_hw_events.msbs[] at all useful, so I removed it too. Some functions and other declarations were reordered to reduce the need for forward declarations. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2792/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: perf: Reorganize contents of perf support files.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The contents of arch/mips/kernel/perf_event.c and arch/mips/kernel/perf_event_mipsxx.c were divided in a seemingly ad hoc manner, with the first including the second. I moved all the hardware counter support code to perf_event_mipsxx.c and removed the gating #ifdefs to the Kconfig and Makefile. Now perf_event.c contains only the callchain support, everything else is in perf_event_mipsxx.c There are no code changes, only moving of functions from one file to the other, or removing empty unneeded functions. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Dezhong Diao <dediao@cisco.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2791/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.cDavid Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of a bunch of useless inline declarations, and join a bunch of improperly split lines. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Add accessor macros for 64-bit performance counter registers.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Add probes for more Octeon II CPUs.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium(). Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Add more CPU identifiers for Octeon II CPUs.David Daney2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU identifiers for cn68XX, cn66XX and cn61XX are known, so add them. Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2776/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: XLR, XLS: Add comment for smp setupHillf Danton2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that BSP could be setup twice, but the nlm_cpu_ready array is only set for ASPs in smpboot.S, not including BSP. Signed-off-by: Hillf Danton <dhillf@gmail.com> Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2695/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>,
| | * | MIPS: JZ4740: GPIO: Check correct IRQ in demux handlerLars-Peter Clausen2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the trigger direction for the triggered IRQ instead of the parent IRQ. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/2433/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: JZ4740: GPIO: Simplify IRQ demuxerLars-Peter Clausen2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already know the base IRQ for a GPIO chip, so there is no need to recalculate it in the demux handler. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen <lars@metafoo.de> Patchwork: http://patchwork.linux-mips.org/patch/2432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: JZ4740: Use generic irq chipLars-Peter Clausen2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic irq chip framework to implement the jz4740 INTC and GPIO irq chips. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2434/ Patchwork: https://patchwork.linux-mips.org/patch/2771/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: remove all CONFIG_SOC_AU1??? definesManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: kill au1xxx.h headerManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No longer required Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h
| | * | MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? definesManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of all CONFIG_SOC_AU1XXX defines in DMA/DBDMA-related code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header depManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | au1xxx-ide uses defines from the pb1200/db1200 headers: get DBDMA ID through platform resource information, hardcode register spacing. The only 2 users of this driver (and the only boards it can really work on realiably) use the same register layout. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-ide@vger.kernel.org To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-ide@vger.kernel.org Acked-by: David S. Miller <davem@davemloft.net> Patchwork: https://patchwork.linux-mips.org/patch/2716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: Redo PCI as platform driverManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c
| | * | MIPS: Alchemy: more base address cleanupManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove all redundant peripheral base address defines, fix all affected boards and drivers. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: rewrite USB platform setup.Manuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use runtime CPU detection to setup all USB parts. Remove the Au1200 OTG and UDC platform devices since there are no drivers for them anyway. Clean up the USB address mess in the au1000 header. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: abstract USB block control register accessManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alchemy chips have one or more registers which control access to the usb blocks as well as PHY configuration. I don't want the OHCI/EHCI glues to know about the different registers and bits; new code hides the gory details of USB configuration from them. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-usb@vger.kernel.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2709/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 drivers/usb/host/alchemy-common.c
| | * | MIPS: Remove __init from add_wired_entry()Manuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Alchemy-PCI I need to add a wired entry after resuming from RAM; remove the __init from add_wired_entry() so that this actually works. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: support multiple GPIO styles in one kernelManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: Always build power codeManuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No reason NOT to build it Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | NET: au1000_eth: Pass MACDMA address through platform resource info.Manuel Lauss2011-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the last hardcoded base address from the au1000_eth driver. The base address of the MACDMA unit was derived from the platform device id; if someone registered the MACs in inverse order both would not work. So instead pass the base address of the DMA unit to the driver with the other platform resource information. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Acked-by: David S. Miller <davem@davemloft.net> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2674/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Fix build with C=1Aaro Koskinen2011-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to compile the 3.1-rc10 kernel for my MIPS board with C=1 (sparse checking), the build fails early with the error: CHK include/linux/version.h UPD include/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h Checking missing-syscalls for N32 CALL scripts/checksyscalls.sh Checking missing-syscalls for O32 CALL scripts/checksyscalls.sh CC kernel/bounds.s GEN include/generated/bounds.h CC arch/mips/kernel/asm-offsets.s GEN include/generated/asm-offsets.h CALL scripts/checksyscalls.sh HOSTCC scripts/genksyms/genksyms.o SHIPPED scripts/genksyms/lex.lex.c SHIPPED scripts/genksyms/keywords.hash.c SHIPPED scripts/genksyms/parse.tab.h HOSTCC scripts/genksyms/lex.lex.o SHIPPED scripts/genksyms/parse.tab.c HOSTCC scripts/genksyms/parse.tab.o HOSTLD scripts/genksyms/genksyms /bin/sh: Syntax error: "(" unexpected make[3]: *** [scripts/mod/empty.o] Error 2 make[2]: *** [scripts/mod] Error 2 make[1]: *** [scripts] Error 2 It seems the shell chokes because sparse is called with command line arguments such as: -D__INT8_C(c)='c' Converting these to form: -D'__INT8_C(c)'='c' seems to fix the problem. [ralf@linux-mips.org: This affects builds with gcc 4.5 and newer.] Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2827/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: MSP71xx: Fix build error.Ralf Baechle2011-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the recent cleanup of the register_*_smp_ops() functions msp71xx wasn't fixed to include the now necessary header resulting in: /home/ralf/src/linux/upstream-linus/arch/mips/pmc-sierra/msp71xx/msp_setup.c: In function ‘prom_init’: /home/ralf/src/linux/upstream-linus/arch/mips/pmc-sierra/msp71xx/msp_setup.c:231:2: error: implicit declaration of function ‘register_vsmp_smp_ops’ [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Don't install vmlinuz if compressed kernel has not been configured.Ralf Baechle2011-10-20
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Netlogic: Specify architecture CFLAGSJayachandran C2011-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use -march=xlr if available, otherwise fallback to mips64. This allows us to support compilation with MIPS toolchains which are not customized for XLR. [ralf@linux-mips.org: And more importantly it works around a gas bug in binutils 2.21 which otherwise may result in an assertion failure building arch/mips/kernel/genex.S. See http://sourceware.org/bugzilla/show_bug.cgi?id=12915 for details.] Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2534/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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