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* powerpc/83xx: Add localbus node and MTD partitions for SBC834xLiang Li2009-08-24
| | | | | | | | | | | | | There is 8MB flash, 8kB EEPROM and 128MB SDRAM on the sbc834x local bus, so add a localbus node in DTS with MTD partitions. The recent U-boot commit fe613cdd4eb moves u-boot to the beginning of flash, hence the legacy label on the partition at the end of flash. Signed-off-by: Liang Li <liang.li@windriver.com> Signed-off-by: Yang Shi <yang.shi@windriver.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: Remove second USB node from SBC834x DTSLiang Li2009-08-24
| | | | | | | | | | | Since only one of the SoC USB devices is brought out to a physical connector on the board, remove the 2nd (USB-DR) node from the DTS. Having it present and USB enabled will cause a hang at boot. Signed-off-by: Liang Li <liang.li@windriver.com> Signed-off-by: Yang Shi <yang.shi@windriver.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the P2020RDB reference board from Freescale. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/booke: Move MMUCSR definition into mmu-book3e.hKumar Gala2009-08-24
| | | | | | | | The MMUCSR is now defined as part of the Book-3E architecture so we can move it into mmu-book3e.h and add some of the additional bits defined by the architecture specs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/82xx: mgcoge - updated defconfigHeiko Schocher2009-08-24
| | | | | | | | - add I2C support - add FCC1 and FCC2 support Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge commit 'paulus-perf/master' into nextBenjamin Herrenschmidt2009-08-19
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| * perf_counter: powerpc: Add callchain supportPaul Mackerras2009-08-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for tracing callchains for powerpc, both 32-bit and 64-bit, and both in the kernel and userspace, from PMU interrupt context. The first three entries stored for each callchain are the NIP (next instruction pointer), LR (link register), and the contents of the LR save area in the second stack frame (the first is ignored because the ABI convention on powerpc is that functions save their return address in their caller's stack frame). Because leaf functions don't have to save their return address (LR value) and don't have to establish a stack frame, it's possible for either or both of LR and the second stack frame's LR save area to have valid return addresses in them. This is basically impossible to disambiguate without either reading the code or looking at auxiliary information such as CFI tables. Since we don't want to do either of those things at interrupt time, we store both LR and the second stack frame's LR save area. Once we get past the second stack frame, there is no ambiguity; all return addresses we get are reliable. For kernel traces, we check whether they are valid kernel instruction addresses and store zero instead if they are not (rather than omitting them, which would make it impossible for userspace to know which was which). We also store zero instead of the second stack frame's LR save area value if it is the same as LR. For kernel traces, we check for interrupt frames, and for user traces, we check for signal frames. In each case, since we're starting a new trace, we store a PERF_CONTEXT_KERNEL/USER marker so that userspace knows that the next three entries are NIP, LR and the second stack frame for the interrupted context. We read user memory with __get_user_inatomic. On 64-bit, if this PMU interrupt occurred while interrupts are soft-disabled, and there is no MMU hash table entry for the page, we will get an -EFAULT return from __get_user_inatomic even if there is a valid Linux PTE for the page, since hash_page isn't reentrant. Thus we have code here to read the Linux PTE and access the page via the kernel linear mapping. Since 64-bit doesn't use (or need) highmem there is no need to do kmap_atomic. On 32-bit, we don't do soft interrupt disabling, so this complication doesn't occur and there is no need to fall back to reading the Linux PTE, since hash_page (or the TLB miss handler) will get called automatically if necessary. Note that we cannot get PMU interrupts in the interval during context switch between switch_mm (which switches the user address space) and switch_to (which actually changes current to the new process). On 64-bit this is because interrupts are hard-disabled in switch_mm and stay hard-disabled until they are soft-enabled later, after switch_to has returned. So there is no possibility of trying to do a user stack trace when the user address space is not current's address space. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * powerpc: Allow perf_counters to access user memory at interrupt timePaul Mackerras2009-08-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a mechanism to allow the perf_counters code to access user memory in a PMU interrupt routine. Such an access can cause various kinds of interrupt: SLB miss, MMU hash table miss, segment table miss, or TLB miss, depending on the processor. This commit only deals with 64-bit classic/server processors, which use an MMU hash table. 32-bit processors are already able to access user memory at interrupt time. Since we don't soft-disable on 32-bit, we avoid the possibility of reentering hash_page or the TLB miss handlers, since they run with interrupts disabled. On 64-bit processors, an SLB miss interrupt on a user address will update the slb_cache and slb_cache_ptr fields in the paca. This is OK except in the case where a PMU interrupt occurs in switch_slb, which also accesses those fields. To prevent this, we hard-disable interrupts in switch_slb. Interrupts are already soft-disabled at this point, and will get hard-enabled when they get soft-enabled later. This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice, and to make sure that it clears the slb_cache_ptr when called from other callers than switch_slb, the existing routine is renamed to __slb_flush_and_rebolt, which is called by switch_slb and the new version of slb_flush_and_rebolt. Similarly, switch_stab (used on POWER3 and RS64 processors) gets a hard_irq_disable() to protect the per-cpu variables used there and in ste_allocate. If a MMU hashtable miss interrupt occurs, normally we would call hash_page to look up the Linux PTE for the address and create a HPTE. However, hash_page is fairly complex and takes some locks, so to avoid the possibility of deadlock, we check the preemption count to see if we are in a (pseudo-)NMI handler, and if so, we don't call hash_page but instead treat it like a bad access that will get reported up through the exception table mechanism. An interrupt whose handler runs even though the interrupt occurred when soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI handler, which should use nmi_enter()/nmi_exit() rather than irq_enter()/irq_exit(). Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
| * powerpc/32: Always order writes to halves of 64-bit PTEsPaul Mackerras2009-08-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit systems with 64-bit PTEs, the PTEs have to be written in two 32-bit halves. On SMP we write the higher-order half and then the lower-order half, with a write barrier between the two halves, but on UP there was no particular ordering of the writes to the two halves. This extends the ordering that we already do on SMP to the UP case as well. The reason is that with the perf_counter subsystem potentially accessing user memory at interrupt time to get stack traces, we have to be careful not to create an incorrect but apparently valid PTE even on UP. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | powerpc: use consistent types in mktreeStephen Rothwell2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | gcc v4.4 currently produces this build warning: arch/powerpc/boot/mktree.c: In function 'main': arch/powerpc/boot/mktree.c:104: warning: dereferencing type-punned pointer will break strict-aliasing rules tmpbuf is only used as an array of unsigned ints, so declare it that way. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/vmlinux.lds: Move _edata downMichael Ellerman2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | Currently _edata does not include several data sections, this causes the kernel's report of memory usage at boot to not match reality, and also prevents kmemleak from working - because it scan between _sdata and _edata for pointers to allocated memory. This mirrors a similar change made recently to the x86 linker script. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Enable GCOVMichael Ellerman2009-08-19
| | | | | | | | | | | | | | | | | | Make it possible to enable GCOV code coverage measurement on powerpc. Lightly tested on 64-bit, seems to work as expected. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Switch to asm-generic/hardirq.hChristoph Hellwig2009-08-19
| | | | | | | | | | | | | | | | hardirq.h on powerpc defines a __last_jiffy_stamp field, but it's not actually used anywhere. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Use DIV_ROUND_CLOSEST in time init codeJulia Lawall2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel.h macro DIV_ROUND_CLOSEST performs the computation (x + d/2)/d but is perhaps more readable. The semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @haskernel@ @@ #include <linux/kernel.h> @depends on haskernel@ expression x,__divisor; @@ - (((x) + ((__divisor) / 2)) / (__divisor)) + DIV_ROUND_CLOSEST(x,__divisor) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/cell: Move CBE_IOPTE_* to <asm/cell-regs.h>Geert Uytterhoeven2009-08-19
| | | | | | | | | | | | | | | | | | As <asm/iommu.h> doesn't contain any other hardware specific definitions but only interfaces. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Missing tests for NULL after ioremap()roel kluin2009-08-19
| | | | | | | | | | | | | | Missing tests after ioremap() Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/prom_init: Evaluate mem kernel parameter for early allocationBenjamin Krill2009-08-19
| | | | | | | | | | | | | | | | | | | | Evaluate mem kernel parameter for early memory allocations. If mem is set no allocation in the region above the given boundary is allowed. The current code doesn't take care about this and allocate memory above the given mem boundary. Signed-off-by: Benjamin Krill <ben@codiert.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: ARRAY_SIZE changes in pasemi and powermac codeStoyan Gaydarov2009-08-19
| | | | | | | | | | | | | | | | These changes were a direct result of using a semantic patch More information can be found at http://www.emn.fr/x-info/coccinelle/ Signed-off-by: Stoyan Gaydarov <sgayda2@uiuc.edu> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/nvram: Allow byte length reads from mmio NVRAM driverMartyn Welch2009-08-19
| | | | | | | | | | | | | | | | Add a byte length read and write interface compatible with the nvram_generic driver interface to the mmio driver. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/sputrace: Use the generic event tracerChristoph Hellwig2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I wrote sputrace before generic tracing infrastrucure was available. Now that we have the generic event tracer we can convert it over and remove a lot of code: 8 files changed, 45 insertions(+), 285 deletions(-) To use it make sure CONFIG_EVENT_TRACING is enabled and then enable the spufs trace channel by echo 1 > /sys/kernel/debug/tracing/events/spufs/spufs_context/enable and then read the trace records using e.g. cat /sys/kernel/debug/tracing/trace Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Fix assert_pte_locked to work properly on uniprocessorKumar Gala2009-08-19
| | | | | | | | | | | | | | | | | | | | Since the pte_lockptr is a spinlock it gets optimized away on uniprocessor builds so using spin_is_locked is not correct. We can use assert_spin_locked instead and get the proper behavior between UP and SMP builds. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/86xx: Update GE Fanuc sbc310 DTSMartyn Welch2009-08-19
| | | | | | | | | | | | | | | | | | Update GE Fanuc DTS to match the alterations suggested during the merge of the ppc9a DTS in commit 740d36ae6344f38c4da64c2ede765d7d2dd1f132 Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/86xx: Enable XMC site on GE Fanuc SBC310Martyn Welch2009-08-19
| | | | | | | | | | | | | | | | | | This patch enables the XMC (PCIe daughter card) site on the SBC310. STG enter the description for the patch above. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/86xx: Correct reading of information presented in cpuinfoMartyn Welch2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | /proc/cpuinfo should be showing the boards revision and the revision of the FPGA fitted. The functions currently used to access this information as incorrect. Additionally the VME geographical address of the PPC9A and it's status as system contoller are available in the board registers. Show these in cpuinfo. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/83xx: Add eSDHC support for MPC837xE-RDB/WLAN boardsAnton Vorontsov2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Actually, the support is already there, but it requires newer U-Boots (to fill-in clock-frequency, and setup pin multiplexing). Though, it appears that on RDB boards USBB pins aren't multiplexed between USB and eSDHC (unlike MDS boards, where USB and eSDHC share pctl and pwrfault pins). So, for RDB boards we can safely setup pinmux and manually fill-in clock-frequency, thus making eSDHC work even with older u-boots. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/85xx: Add support for I2C EEPROMs on MPC8548CDS boardsAnton Vorontsov2009-08-19
| | | | | | | | | | | | | | | | This patch simply adds four eeprom nodes to MPC8548CDS' device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/83xx: Add support for MPC8377E-WLAN boardsAnton Vorontsov2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8377E-WLAN are basically RDB boards except: - RAM extended to 512 MB; - NAND flash removed, NOR flash extended to 64 MB; - Vitesse VSC7385 5-port switch removed, RTL8211B PHY added; - Power management MCU removed; - PCI slot removed, another mini-PCI slot added (IRQ routing changed); - USB3300 PHY's ID pin grounded, thus USB port is host-only. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/qe: introduce missing kfreeJulia Lawall2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error handling code following a kzalloc should free the allocated data. The semantic match that finds the problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @r exists@ local idexpression x; statement S; expression E; identifier f,f1,l; position p1,p2; expression *ptr != NULL; @@ x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...x...+> } ( x->f1 = E | (x->f1 == NULL || ...) | f(...,x->f1,...) ) ...> ( return \(0\|<+...x...+>\|ptr\); | return@p2 ...; ) @script:python@ p1 << r.p1; p2 << r.p2; @@ print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/ipic: introduce missing kfreeJulia Lawall2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error handling code following a kzalloc should free the allocated data. The semantic match that finds the problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @r exists@ local idexpression x; statement S; expression E; identifier f,f1,l; position p1,p2; expression *ptr != NULL; @@ x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...x...+> } ( x->f1 = E | (x->f1 == NULL || ...) | f(...,x->f1,...) ) ...> ( return \(0\|<+...x...+>\|ptr\); | return@p2 ...; ) @script:python@ p1 << r.p1; p2 << r.p2; @@ print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/82xx: mgcoge - updates for 2.6.32Heiko Schocher2009-08-19
| | | | | | | | | | | | | | | | | | | | - add I2C support - add FCC1 and FCC2 support - fix bogus gpio numbering in plattform code Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/ipic: unmask all interrupt sourcesSebastian Andrzej Siewior2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in case the interrupt controller was used in an earlier life then it is possible it is that some of its sources were used and are still unmask. If the (unmasked) device is active and is creating interrupts (or one interrupts was pending since the interrupts were disabled) then the boot process "ends" very soon. Once external interrupts are enabled, we land in -> do_IRQ -> call ppc_md.get_irq() -> ipic_read() gets the source number -> irq_linear_revmap(source) -> revmap[source] == NO_IRQ -> irq_find_mapping(source) returns NO_IRQ because no source is registered -> source is NO_IRQ, ppc_spurious_interrupts gets incremented, no further action. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/fsl_rio: Add kmalloc NULL testsJulia Lawall2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check that the result of kmalloc/kzalloc is not NULL before dereferencing it. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression *x; identifier f; constant char *C; @@ x = \(kmalloc\|kcalloc\|kzalloc\)(...); ... when != x == NULL when != x != NULL when != (x || ...) ( kfree(x) | f(...,C,...,x,...) | *f(...,x,...) | *x->f ) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/fsl-booke: read buffer overflowRoel Kluin2009-08-19
| | | | | | | | | | | | | | | | | | cam[tlbcam_index] is checked before tlbcam_index < ARRAY_SIZE(cam) Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/85xx: Added 36-bit physical device tree for mpc8536ds boardKumar Gala2009-08-19
| | | | | | | | | | | | | | | | Added a device tree that should be similiar to mpc8536ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/85xx: Move mpc8536ds.dts to address-cells/size-cells = <2>Kumar Gala2009-08-19
| | | | | | | | | | | | | | | | | | Change the top-level #address-cells and #size-cells to <2> so the mpc8536ds.dts is easier to deal with both a true 32-bit physical or 36-bit physical address space. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/40x: Update kilauea defconfig to support NAND, RTC and HWMONStefan Roese2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following devices to the Kilauea defconfig file: - PPC4xx NAND controller (NDFC) - I2C RTC (Dallas DS1338) - I2C HWMON (Dallas DS1775) Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/44x: Update Canyonlands defconfig to support NOR, NAND and RTCStefan Roese2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following devices to the Canyonlands defconfig file: - NOR FLASH - PPC4xx NAND controller (NDFC) - I2C RTC (M41T80) Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/40x: Update Kilauea dts to support NAND, RTC and HWMONStefan Roese2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following devices to the Kilauea dts: - PPC4xx NAND controller (NDFC) - I2C RTC (Dallas DS1338) - I2C HWMON (Dallas DS1775) Additionally the partitioning of the NOR FLASH is changed. The dtb partition has been missing. Fixed in this patch. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/44x: Add NAND support to Canyonlands dtsStefan Roese2009-08-19
| | | | | | | | | | | | | | | | Also some whitespace cleanup in the USB device nodes. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add AMCC 460EX/460GT Rev. B support to cputable.cStefan Roese2009-08-19
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Fix switch_mmu_context to iterate of the proper list of cpusKumar Gala2009-08-19
| | | | | | | | | | | | | | | | | | Introduced a temporary variable into our iterating over the list cpus that are threads on the same core. For some reason Ben forgot how for loops work. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Fix encoding of page table cache numbersBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | The mask used to encode the page table cache number in the batch when freeing page tables was too small for the new possible values of MMU page sizes. This increases it along with a comment explaining the constraints. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Remaining 64-bit Book3E supportBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Add support for SPARSEMEM_VMEMMAP on 64-bit Book3EBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | The base TLB support didn't include support for SPARSEMEM_VMEMMAP, though we did carve out some virtual space for it, the necessary support code wasn't there. This implements it by using 16M pages for now, though the page size could easily be changed at runtime if necessary. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add TLB management code for 64-bit Book3EBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | | | This adds the TLB miss handler assembly, the low level TLB flush routines along with the necessary hook for dealing with our virtual page tables or indirect TLB entries that need to be flushes when PTE pages are freed. There is currently no support for hugetlbfs Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc/mm: Move around mmu_gathers definition on 64-bitBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | The definition for the global structure mmu_gathers, used by generic code, is currently defined in multiple places not including anything used by 64-bit Book3E. This changes it by moving to one place common to all processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add PACA fields specific to 64-bit Book3E processorsBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | This adds various fields in the PACA that are for use specifically by Book3E processors, such as exception save areas, current pgd pointer, special exceptions kernel stacks etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add definitions used by exception handling on 64-bit Book3EBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | This adds various definitions and macros used by the exception and TLB miss handling on 64-bit BookE It also adds the definitions of the SPRGs used for various exception types Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add memory management headers for new 64-bit BookEBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds the PTE and pgtable format definitions, along with changes to the kernel memory map and other definitions related to implementing support for 64-bit Book3E. This also shields some asm-offset bits that are currently only relevant on 32-bit We also move the definition of the "linux" page size constants to the common mmu.h file and add a few sizes that are relevant to embedded processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add SPR definitions for new 64-bit BookEBenjamin Herrenschmidt2009-08-19
| | | | | | | | | | | | | | | | This adds various SPRs defined on 64-bit BookE, along with changes to the definition of the base MSR values to add the values needed for 64-bit Book3E. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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