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authorMartyn Welch <martyn.welch@gefanuc.com>2009-06-30 10:32:26 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-19 20:27:55 -0400
commit2eaa50e9670ecab9712317723cb7836a4da1c0dc (patch)
tree8017a6c4aff334aae6d67865a5d404bdafa38dfb /arch
parent89f3729642cf33bfbc742b85e134936b562f9731 (diff)
powerpc/86xx: Correct reading of information presented in cpuinfo
/proc/cpuinfo should be showing the boards revision and the revision of the FPGA fitted. The functions currently used to access this information as incorrect. Additionally the VME geographical address of the PPC9A and it's status as system contoller are available in the board registers. Show these in cpuinfo. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/platforms/86xx/gef_ppc9a.c37
1 files changed, 30 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 2efa052975e6..287f7bd17dd9 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -102,8 +102,8 @@ static unsigned int gef_ppc9a_get_pcb_rev(void)
102{ 102{
103 unsigned int reg; 103 unsigned int reg;
104 104
105 reg = ioread32(ppc9a_regs); 105 reg = ioread32be(ppc9a_regs);
106 return (reg >> 8) & 0xff; 106 return (reg >> 16) & 0xff;
107} 107}
108 108
109/* Return the board (software) revision */ 109/* Return the board (software) revision */
@@ -111,8 +111,8 @@ static unsigned int gef_ppc9a_get_board_rev(void)
111{ 111{
112 unsigned int reg; 112 unsigned int reg;
113 113
114 reg = ioread32(ppc9a_regs); 114 reg = ioread32be(ppc9a_regs);
115 return (reg >> 16) & 0xff; 115 return (reg >> 8) & 0xff;
116} 116}
117 117
118/* Return the FPGA revision */ 118/* Return the FPGA revision */
@@ -120,8 +120,26 @@ static unsigned int gef_ppc9a_get_fpga_rev(void)
120{ 120{
121 unsigned int reg; 121 unsigned int reg;
122 122
123 reg = ioread32(ppc9a_regs); 123 reg = ioread32be(ppc9a_regs);
124 return (reg >> 24) & 0xf; 124 return reg & 0xf;
125}
126
127/* Return VME Geographical Address */
128static unsigned int gef_ppc9a_get_vme_geo_addr(void)
129{
130 unsigned int reg;
131
132 reg = ioread32be(ppc9a_regs + 0x4);
133 return reg & 0x1f;
134}
135
136/* Return VME System Controller Status */
137static unsigned int gef_ppc9a_get_vme_is_syscon(void)
138{
139 unsigned int reg;
140
141 reg = ioread32be(ppc9a_regs + 0x4);
142 return (reg >> 9) & 0x1;
125} 143}
126 144
127static void gef_ppc9a_show_cpuinfo(struct seq_file *m) 145static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
@@ -131,10 +149,15 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
131 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n"); 149 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
132 150
133 seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(), 151 seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
134 ('A' + gef_ppc9a_get_board_rev() - 1)); 152 ('A' + gef_ppc9a_get_board_rev()));
135 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev()); 153 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
136 154
137 seq_printf(m, "SVR\t\t: 0x%x\n", svid); 155 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
156
157 seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
158
159 seq_printf(m, "VME syscon\t: %s\n",
160 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
138} 161}
139 162
140static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev) 163static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)