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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-09-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This has been sitting in -next for a while with no objections and all MIPS defconfigs except one are building fine; that one platform got broken by another patch in your tree and I'm going to submit a patch separately. - a handful of fixes that didn't make 3.11 - a few bits of Octeon 3 support with more to come for a later release - platform enhancements for Octeon, ath79, Lantiq, Netlogic and Ralink SOCs - a GPIO driver for the Octeon - some dusting off of the DECstation code - the usual dose of cleanups" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits) MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code MIPS: kexec: Fix random crashes while loading crashkernel MIPS: kdump: Skip walking indirection page for crashkernels MIPS: DECstation HRT calibration bug fixes MIPS: Export copy_from_user_page() (needed by lustre) MIPS: Add driver for the built-in PCI controller of the RT3883 SoC MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000 MIPS: ralink: Add support for reset-controller API MIPS: ralink: mt7620: Add cpu-feature-override header MIPS: ralink: mt7620: Add spi clock definition MIPS: ralink: mt7620: Add wdt clock definition MIPS: ralink: mt7620: Improve clock frequency detection MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts MIPS: ralink: mt7620: Add verbose ram info MIPS: ralink: Probe clocksources from OF MIPS: ralink: Add support for systick timer found on newer ralink SoC MIPS: ralink: Add support for periodic timer irq MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards MIPS: Netlogic: Add support for USB on XLP2xx MIPS: Netlogic: XLP2xx update for I2C controller ...
| * Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-06
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| | * MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible codeJerin Jacob2013-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of current_cpu_type() in cpu_is_noncoherent_r10000() is not preemption-safe. Use boot_cpu_type() instead to make it preemption-safe. <log> / # insmod mtd_readtest.ko dev=4 mtd_readtest: MTD device: 4 mtd_readtest: MTD device size 996671488, eraseblock size 524288, page size 4096, count of eraseblocks 1901, pages per eraseblock 128, OOB size 224 mtd_readtest: scanning for bad eraseblocks mtd_readtest: scanned 1901 eraseblocks, 0 are bad mtd_readtest: testing page read BUG: using smp_processor_id() in preemptible [00000000] code: insmod/99 caller is mips_dma_sync_single_for_cpu+0x2c/0x128 CPU: 2 PID: 99 Comm: insmod Not tainted 3.10.4 #67 Stack : 00000006 69735f63 00000000 00000000 00000000 00000000 808273d6 00000032 80820000 00000002 8d700000 8de48fa0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8d6afb00 8d6afb24 80721f24 807b9927 8012c130 80820000 80721f24 00000002 00000063 8de48fa0 8082333c 807b98e6 8d6afaa0 ... Call Trace: [<80109984>] show_stack+0x64/0x7c [<80666230>] dump_stack+0x20/0x2c [<803a2210>] debug_smp_processor_id+0xe0/0xf0 [<801116f0>] mips_dma_sync_single_for_cpu+0x2c/0x128 [<8043456c>] nand_plat_read_page+0x16c/0x234 [<8042fad4>] nand_do_read_ops+0x194/0x480 [<804301dc>] nand_read+0x50/0x7c [<804261c8>] part_read+0x70/0xc0 [<804231dc>] mtd_read+0x80/0xe4 [<c0431354>] init_module+0x354/0x6f8 [mtd_readtest] [<8010057c>] do_one_initcall+0x140/0x1a4 [<80176d7c>] load_module+0x1b5c/0x2258 [<8017752c>] SyS_init_module+0xb4/0xec [<8010f3fc>] stack_done+0x20/0x44 BUG: using smp_processor_id() in preemptible [00000000] code: insmod/99 </log> Signed-off-by: Jerin Jacob <jerinjacobk@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5800/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-05
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| | * MIPS: kexec: Fix random crashes while loading crashkernelPrem Mallappa2013-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed compilation errors in case of non-KEXEC kernel Rearranging code so that crashk_res gets updated. - crashk_res is updated after mips_parse_crashkernel(), after resource_init(), which is after arch_mem_init(). - The reserved memory is actually treated as Usable memory, Unless we load the crash kernel, everything works. Signed-off-by: Prem Mallappa <pmallappa@caviumnetworks.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/5805/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: kdump: Skip walking indirection page for crashkernelsPrem Mallappa2013-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KDUMP: skip indirection page, as crashkernel has already copied to destination [ralf@linux-mips.org: cosmetic changes.] Signed-off-by: Prem Mallappa <pmallappa@caviumnetworks.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5786/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: DECstation HRT calibration bug fixesMaciej W. Rozycki2013-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change corrects DECstation HRT calibration, by removing the following bugs: 1. Calibration period selection -- HZ / 10 has been chosen, however on DECstation computers, HZ never divides by 10, as the choice for HZ is among 128, 256 and 1024. The choice therefore results in a systematic calibration error, e.g. 6.25% for the usual choice of 128 for HZ: 128 / 10 * 10 = 120 (128 - 120) / 128 -> 6.25% The change therefore makes calibration use HZ / 8 that is always accurate for the HZ values available, getting rid of the systematic error. 2. Calibration starting point synchronisation -- the duration of a number of intervals between DS1287A periodic interrupt assertions is measured, however code does not ensure at the beginning that the interrupt has not been previously asserted. This results in a variable error of e.g. up to another 6.25% for the period of HZ / 8 (8.(3)% with the original HZ / 10 period) and the usual choice of 128 for HZ: 1 / 16 -> 6.25% 1 / 12 -> 8.(3)% The change therefore adds an initial call to ds1287_timer_state that clears any previous periodic interrupt pending. The same issue applies to both I/O ASIC counter and R4k CP0 timer calibration on DECstation systems as similar code is used in both cases and both pieces of code are covered by this fix. On an R3400 test system used this fix results in a change of the I/O ASIC clock frequency reported from values like: I/O ASIC clock frequency 23185830Hz to: I/O ASIC clock frequency 24999288Hz removing the miscalculation by 6.25% from the systematic error and (for the individual sample provided) a further 1.00% from the variable error, accordingly. The nominal I/O ASIC clock frequency is 25MHz on this system. Here's another result, with the fix applied, from a system that has both HRTs available (using an R4400 at 60MHz nominal): MIPS counter frequency 59999328Hz I/O ASIC clock frequency 24999432Hz Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5807/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Export copy_from_user_page() (needed by lustre)Geert Uytterhoeven2013-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ERROR: "copy_from_user_page" [drivers/staging/lustre/lustre/libcfs/libcfs.ko] undefined! Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-04
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| | * MIPS: powertv: Drop BOOTLOADER_DRIVER Kconfig symbolMarkos Chandras2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kbldr.h header file required for this was neither committed in the original submission in a3a0f8c8ed2e2470f4dcd6da95020d41fed84747 "MIPS: PowerTV: Base files for Cisco PowerTV platform" nor was it ever present in the git tree so this option never worked. Fixes the following build problem: arch/mips/powertv/reset.c:25:36: fatal error: asm/mach-powertv/kbldr.h: No such file or directory compilation terminated. Cc: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: David VomLehn <dvomlehn@cisco.com> Patchwork: https://patchwork.linux-mips.org/patch/5801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Kconfig: Drop obsolete NR_CPUS_DEFAULT_{1,2} optionsMarkos Chandras2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NR_CPUS_DEFAULT_1 introduced as an aid for the QEMU platform in 72ede9b18967e7a8a62a88f164f003193f6d891f "[MIPS] Qemu: Fix Symmetric Uniprocessor support" which was later removed in 302922e5f6901eb6f29c58539631f71b3d9746b8 "[MIPS] Qemu: Remove platform." On certain randconfigs it may happen for NR_CPUS to have an empty value because not all SMP platforms select a suitable NR_CPUS_DEFAULT_* value. We fix this by restoring the range of NR_CPUS to 2..64 and drop the NR_CPUS_DEFAULT_{1,2} symbols. The first one is no longer used and the latter is not needed since NR_CPUS=2 is now the default value. Fixes the following problem on a randconfig: .config:164:warning: symbol value '' invalid for NR_CPUS Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: TXx9: Fix build error if CONFIG_TOSHIBA_JMR3927 is not selectedMarkos Chandras2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The jmr3927_vec txx9_board_vec struct is defined in txx9/jmr3927/setup.c which is only built if CONFIG_TOSHIBA_JMR3927 is selected. This patch fixes the following build problem: arch/mips/txx9/generic/setup.c: In function 'select_board': arch/mips/txx9/generic/setup.c:354:20: error: 'jmr3927_vec' undeclared (first use in this function) arch/mips/txx9/generic/setup.c:354:20: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [arch/mips/txx9/generic/setup.o] Error 1 Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5713/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Loongson: Hide the pci code behind CONFIG_PCIMarkos Chandras2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci.c code depends on symbols which are only visible if CONFIG_PCI is selected. Also fixes the following problem on loongson allnoconfig: arch/mips/built-in.o: In function `pcibios_init': pci.c:(.init.text+0x528): undefined reference to `register_pci_controller' arch/mips/built-in.o:(.data+0xc): undefined reference to `loongson_pci_ops' Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5584/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Ftrace: Fix function tracing return address to matchCorey Minyard2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dynamic function tracing was not working on MIPS. When doing dynamic tracing, the tracer attempts to match up the passed in address with the one the compiler creates in the mcount tables. The MIPS code was passing in the return address from the tracing function call, but the compiler tables were the address of the function call. So they wouldn't match. Just subtracting 8 from the return address will give the address of the function call. Easy enough. Signed-off-by: Corey Minyard <cminyard@mvista.com> [david.daney@cavium.com: Adjusted code comment and patch Subject.] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5592/
| | * MIPS: R4k clock source initialization bug fixMaciej W. Rozycki2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for a bug introduced with commit 447cdf2628b59aa513a42785450b348dced26d8a, submitted as archived here: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20080312235002.c717dde3.yoichi_yuasa%40tripeaks.co.jp regrettably with no further explanation. The issue is with the CP0 Count register read erratum present on R4000 and some R4400 processors. If this erratum is present, then a read from this register that happens around the time it reaches the value stored in the CP0 Compare register causes a CP0 timer interrupt that is supposed to happen when the values in the two registers match to be missed. The implication for the chips affected is the CP0 timer can be used either as a source of a timer interrupt (a clock event) or as a source of a high-resolution counter (a clock source), but not both at a time. The erratum does not affect timer interrupt operation itself, because in this case the CP0 Count register is only read while the timer interrupt has already been raised, while high-resolution counter references happen at random times. Additionally some systems apparently have issues with the timer interrupt line being routed externally and not following the usual CP0 Count/Compare semantics. In this case we don't want to use the R4k clock event. We've meant to address the erratum and the timer interrupt routing issue in time_init, however the commit referred to above broke our solution. What we currently have is we enable the R4k clock source if the R4k clock event initialization has succeeded (the timer is present and has no timer interrupt routing issue) or there is no CP0 Count register read erratum. Which gives the following boolean matrix: clock event | count erratum => clock source ------------+---------------+-------------- 0 | 0 | 1 (OK) 0 | 1 | 0 (bug!) -> no interference, could use 1 | 0 | 1 (OK) 1 | 1 | 1 (bug!) -> can't use, interference What we want instead is to enable the R4k clock source if there is no CP0 Count register read erratum (obviously) or the R4k clock event initialization has *failed* -- because in the latter case we won't be using the timer interrupt anyway, so we don't care about any interference CP0 Count reads might cause with the interrupt. This corresponds to the following boolean matrix: clock event | count erratum => clock source ------------+---------------+-------------- 0 | 0 | 1 0 | 1 | 1 1 | 0 | 1 1 | 1 | 0 This is implemented here, effectively reverting the problematic commit, and a short explanation is given next to code modified so that the rationale is known to future readers and confusion is prevented from happening here again. It is worth noting that mips_clockevent_init returns 0 upon success while cpu_has_mfc0_count_bug returns 0 upon failure. This is because the former function returns an error code while the latter returns a boolean value. To signify the difference I have therefore chosen to compare the result of the former call explicitly against 0. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5799/
| | * MIPS: Fix get_user_page_fast() for mips with cache aliasKamal Dasu2013-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_user_pages_fast() is missing cache flushes for MIPS platforms with cache aliases. Filesystem failures observed with DirectIO operations due to missing flush_anon_page() that use page coloring logic to work with cache aliases. This fix falls through to take slow_irqon path that calls get_user_pages() that has required logic for platforms where cpu_has_dc_aliases is true. [ralf@linux-mips.org: Explicity include <asm/cpu-features.h>.] Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5469/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add driver for the built-in PCI controller of the RT3883 SoCGabor Juhos2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ralink RT3883 SoCs have a built-in PCI Host Controller device. The patch adds a platform driver and device tree binding documentation for that. The patch also enables the HW_HAS_PCI config option. This is required in order to be able to enable the PCI support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000Jim Quinlan2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A stale misprediction address in either the JTB or the CRS may trigger a prefetch inside a region that is currently being used by a DMA engine, which is not IO-coherent. This prefetch will fetch a line into the scache, and that line will soon become stale (ie wrong) during/after the DMA. Mayhem ensues. In dma-default.c, the r10000 is handled as a special case in the same way that we want to handle Zephyr. So we generalize the exception cases into a function, and include Zephyr as one of the processors that needs this special care. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5776/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Add support for reset-controller APIJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper for reseting different devices on the SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5804/ Patchwork: https://patchwork.linux-mips.org/patch/5797/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: Add cpu-feature-override headerGabor Juhos2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override certain CPU features to help GCC to optimize the generated code. Saves about 150KB in the vmlinux image with a generic configuration. text data bss dec hex filename 3824158 134820 234192 4193170 3ffb92 vmlinux.no-override 3664054 138804 234192 4037050 3d99ba vmlinux.override Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5759/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: Add spi clock definitionJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: Add wdt clock definitionJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5756/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: Improve clock frequency detectionGabor Juhos2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: This SoC has EHCI and OHCI hostsJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Select the the EHCI and OHCI symbols. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5675/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: mt7620: Add verbose ram infoJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the code print which of SDRAM, DDR1 or DDR2 was detected. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Probe clocksources from OFJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make plat_time_init() call clocksource_of_init() allowing the systick cevt to load. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Add support for systick timer found on newer ralink SoCJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent of the SoC master clock. If we want to automatic frequency scaling to work we need to use the systick timer as the clock source. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Add support for periodic timer irqJohn Crispin2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a driver for the periodic timer found on Ralink SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5682/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Built-in DTB for XLP2xx SoC boardsGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a default built-in device tree for XLP2xx SoC. The new file xlp_fvp.dts has updated entries for I2C and memory. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Add support for USB on XLP2xxGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5744/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: XLP2xx update for I2C controllerGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Core wakeup changes for XLP2XXJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On XLP2xx, wakeup code does not need to enable clock on the core. Update xlp/wakeup.c to handle this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: XLP2XX CPU and PIC frequencyGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Call xlp_mmu_init on all threadsJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Add support for XLP2XXJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XLP2XX is first in the series of 28nm XLPII processors. The changes are to: * Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c. * Add a cpu_is_xlpii() function to check for XLPII processors. * Update xlp_mmu_init() to use config4 to enable extended TLB. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Fix DT flash size parameterJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flash chipselects can span 32MB, fix this in the built-in device tree. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Remove memory section from built-in DTJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not pass a memory section in the built-in DTB, and let the boot code use the values from the DRAM BARs. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Netlogic: Read memory from DRAM BARsJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Switch to the clkdev frameworkGabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ath79 code uses static clock devices and provides its own clk_{get,put} implementations. Change the code to use dynamically allocated clock devices and register the clocks within the clkdev framework. Additionally, remove the local clk_{get,put} implementation. The clkdev framework has a common implementation of those. Also move the call of ath79_clock_init() from plat_mem_init() to plat_time_init(). Otherwise it would not be possible to use memory allocation functions from ath79clock_init() becasuse the memory subsystem is not yet initialized when plat_mem_init() runs. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5780/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Use local variables for clock ratesGabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Use ath79_get_sys_clk_rate to get basic clock ratesGabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5782/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Use a helper function to get system clock ratesGabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Use local ref clock rate in ar934x_get_pll_freqGabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5779/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Fix ar933x watchdog clockFelix Fietkau2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d227c8e68d685936ecf42ac175fec0e54 (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0Gabor Juhos2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ath79 code supports various SoCs which are using either a 24Kc or a 74Kc core. The 74Kc core has DSP support, so don't hardwire the values to zero. Commit 00dc5ce2a653a332190aa29b2e1f3bceaa7d5b8d (MIPS: ath79: don't hardcode the unavailability of the DSP ASE) has fixed this already, but that change got reverted by 475032564ed96c94c085e3e7a90e07d150a7cec9 (MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.) Reported-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5750/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Lantiq: Add defconfig for xway SoCJohn Crispin2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | This add a default config for the Lantiq XWAY SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5796/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Lantiq: Falcon: fix asc clock definitionThomas Langer2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks of the serial ports were not setup properly. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5659/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Lantiq: Falcon: add cpu-feature-override.hThomas Langer2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu-feature-override.h for the GPON SoC Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5658/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Lantiq: Adds minimal dcdc driverJohn Crispin2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver so far only reads the core voltage. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5677/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Move declaration of Octeon function fixup_irqs() to header.Ralf Baechle2013-09-03
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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