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| * | | | MIPS: Netlogic: Update XLP9XX/2XX core freq calculationJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This should give the correct value for all board configurations. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6870/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XXGanesan Ramalingam2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Fix XLP9XX pic entryJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6869/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Use PRID_IMP_MASK macroJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: IRQ mapping for some more SoC blocksJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6911/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Enable access to more than 64GBJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Reduce size of reset codeJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6910/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Use cpumask_scnprintf for wakeup_maskJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use standard function to print cpumask. Also fixup a typo in the same file. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6909/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Warn on invalid irqJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6862/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Move coremask setup to nlm_node_initJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for nlm_node_present(0) to work on uniprocessor compile. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6861/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Netlogic: Fix uniprocessor compilationJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macros in topology.h need CONFIG_SMP, and the uniprocessor compilation fails due to this. Wrap the macros in an ifdef so that uniprocessor works. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6863/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Support upto 256 CPUsJayachandran C2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for two node XLP9xx configurations. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Enable the BPF_JIT symbol for MIPSMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: net: Add BPF JITMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for BPF-JIT on MIPS Tested on mips32 LE/BE and mips64 BE/n64 using dhcp, ping and various tcpdump filters. Benchmarking: Assuming the remote MIPS target uses 192.168.154.181 as its IP address, and the local host uses 192.168.154.136, the following results can be obtained using the following tcpdump filter (catches no frames) and a simple 'time ping -f -c 1000000' command. [root@(none) ~]# tcpdump -p -n -s 0 -i eth0 net 10.0.0.0/24 -d (000) ldh [12] (001) jeq #0x800 jt 2 jf 8 (002) ld [26] (003) and #0xffffff00 (004) jeq #0xa000000 jt 16 jf 5 (005) ld [30] (006) and #0xffffff00 (007) jeq #0xa000000 jt 16 jf 17 (008) jeq #0x806 jt 10 jf 9 (009) jeq #0x8035 jt 10 jf 17 (010) ld [28] (011) and #0xffffff00 (012) jeq #0xa000000 jt 16 jf 13 (013) ld [38] (014) and #0xffffff00 (015) jeq #0xa000000 jt 16 jf 17 (016) ret #65535 - BPF-JIT Disabled real 1m38.005s user 0m1.510s sys 0m6.710s - BPF-JIT Enabled real 1m35.215s user 0m1.200s sys 0m4.140s [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: uasm: Add lb uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: uasm: Add mflo uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: uasm: Add mul uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add lh uam instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6733/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add wsbh uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add sltu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add sltiu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add jalr uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add mfhi uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add divu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add srlv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add sllv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: uasm: Add u3u2u1 instruction buildersMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by the sllv and srlv instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: math-emu: Add IEEE754 exception statistics to debugfsDeng-Cheng Zhu2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes it's useful to let the user, while doing performance research, know what in the IEEE754 exceptions has caused many times of FP emulation when running a specific application. This patch adds 5 more files to /sys/kernel/debug/mips/fpuemustats/, whose filenames begin with "ieee754". These stats are in addition to the existing cp1ops, cp1xops, errors, loads and stores, which may not be useful in understanding the reasons of ieee754 exceptions. [ralf@linux-mips.org: Fixed reject due to other changes to the kernel FP assist software.] Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Cc: james.hogan@imgtec.com Patchwork: http://patchwork.linux-mips.org/patch/7044/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: BCM47XX: Slightly clean memory detectionRafał Miłecki2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch was tested on devices with 64 MiB and 256 MiB of RAM. It documents every part nicely and drops this hacky part of code: max = off | ((128 << 20) - 1); Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/6808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: octeon: Add interface mode detection for Octeon IIAlex Smith2014-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add interface mode detection for Octeon II. This is necessary to detect the interface modes correctly on the UBNT E200 board. Code is taken from the UBNT GPL source release, with some alterations: SRIO, ILK and RXAUI interface modes are removed and instead return disabled as these modes are not currently supported. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Tested-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7039/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle2014-05-29
| |\ \ \ \ | | | | | | | | | | | | | | | | | | mips-for-linux-next
| | * | | | MIPS: Malta: CPS SMP by defaultPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_MIPS_CPS SMP implementation should be able to handle all cases the CONFIG_MIPS_CMP implementation does, but without requiring bootloader assistance. It is also required in order to make use of features such as hotplug & cpuidle core power gating. Enable it by default for Malta configs that previously enabled the now deprecated CONFIG_MIPS_CMP, and disable the latter. The local version suffix "cmp" is removed rather than replaced with "cps" since there are other ways to tell that the CPS SMP implementation is in use (the "VPE topology" line in the boot log being one). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | cpuidle: cpuidle-cps: add MIPS CPS cpuidle driverPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a cpuidle driver for systems based around the MIPS Coherent Processing System (CPS) architecture. It supports four idle states: - The standard MIPS wait instruction. - The non-coherent wait, clock gated & power gated states exposed by the recently added pm-cps layer. The pm-cps layer is used to enter all the deep idle states. Since cores in the clock or power gated states cannot service interrupts, the gic_send_ipi_single function is modified to send a power up command for the appropriate core to the CPC in cases where the target CPU has marked itself potentially incoherent. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: include cpuidle Kconfig menuPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch simply includes the cpuidle Kconfig entries in preparation for cpuidle drivers used on MIPS systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: cpuidle wait instruction statePaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defines a macro intended to allow trivial use of the regular MIPS wait instruction from cpuidle drivers, which may simply invoke the macro within their array of states. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: duplicate core0 CCA on secondary coresPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from the boot CPU. This allows overrides of the CCA using the cca= kernel parameter to take effect on all CPUs for consistency. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: set a coherent default CCAPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets a default CCA suited for use with multi-core SMP on all current MIPS CPS based systems. It may still be overriden by the cca= argument on the kernel command line. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: prevent multi-core SMP with unsuitable CCAPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the user or bootloader sets the CCA to a value which is not suited for multi-core SMP (ie. anything non-coherent) then limit the system to using only a single core and warn the user. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: hotplug supportPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for offlining CPUs via hotplug when using the CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2 things will happen: - If the CPU is part of a core which implements the MT ASE and there is at least one other VPE online within that core then the VPE will be halted by settings its TCHalt bit. - Otherwise if supported the core will be powered down via the CPC. - Otherwise the CPU will hang by executing an infinite loop. Bringing CPUs back online is then a process of either clearing the appropriate VPEs TCHalt bit or powering up the appropriate core via the CPC. Throughout the process the struct core_boot_config vpe_mask field must be maintained such that mips_cps_boot_vpes will start & stop the correct VPEs. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: pm-cps: add PM state entry code for CPS systemsPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code to generate entry & exit code for various low power states available on systems based around the MIPS Coherent Processing System architecture (ie. those with a Coherence Manager, Global Interrupt Controller & for >=CM2 a Cluster Power Controller). States supported are: - Non-coherent wait. This state first leaves the coherent domain and then executes a regular MIPS wait instruction. Power savings are found from the elimination of coherency interventions between the core and any other coherent requestors in the system. - Clock gated. This state leaves the coherent domain and then gates the clock input to the core. This removes all dynamic power from the core but leaves the core at the mercy of another to restart its clock. Register state is preserved, but the core can not service interrupts whilst its clock is gated. - Power gated. This deepest state removes all power input to the core. All register state is lost and the core will restart execution from its BEV when another core powers it back up. Because register state is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP implementation in order for the core to exit the state successfully. The code will detect which states are available on the current system during boot & generate the entry/exit code for those states. This will be used by cpuidle & hotplug implementations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: use CPC core-other lockingPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core which the CPC core-other region relates to is based upon the core-local core-other addressing register. As its name suggests this register is shared between all VPEs within a core, and if there is a possibility that multiple VPEs within a core will attempt to access another core simultaneously then locking is required. This wasn't previously a problem with the only user being cpu0 during boot, but will be an issue once hotplug is implemented & may race with other users such as cpuidle. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: flush cache after patching mips_cps_core_entryPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The start of mips_cps_core_entry is patched in order to provide the code with the address of the CM register region at a point where it will be running non-coherent with the rest of the system. However the cache wasn't being flushed after that patching which could in principle lead to secondary cores using an invalid CM base address. The patching is moved to cps_prepare_cpus since local_flush_icache_range has not been initialised at the point cps_smp_setup is called. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: function to determine whether CPS SMP is in usePaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core power down state for cpuidle will require that the CPS SMP implementation is in use. This patch provides a mips_cps_smp_in_use function which determines whether or not the CPS SMP implementation is currently in use. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: smp-cps: rework core/VPE initialisationPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hotplug and/or a powered down idle state are supported cases will arise where a non-zero VPE must be brought online without VPE 0, and it where multiple VPEs must be onlined simultaneously. This patch prepares for that by: - Splitting struct boot_config into core & VPE boot config structures, allocated one per core or VPE respectively. This allows for multiple VPEs to be onlined simultaneously without clobbering each others configuration. - Indicating which VPEs should be online within a core at any given time using a bitmap. This allows multiple VPEs to be brought online simultaneously and also indicates to VPE 0 whether it should halt after starting any non-zero VPEs that should be online within the core. For example if all VPEs within a core are offlined via hotplug and the user onlines the second VPE within that core: 1) The core will be powered up. 2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to initialise the core. 3) VPE 0 will start VPE 1 because its bit is set in the cores bitmap. 4) VPE 0 will halt itself because its bit is clear in the cores bitmap. - Moving the core & VPE initialisation to assembly code which does not make any use of the stack. This is because if a non-zero VPE is to be brought online in a powered down core then when VPE 0 of that core runs it may not have a valid stack, and even if it did then it's messy to run through parts of generic kernel code on VPE 0 before starting the correct VPE. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: uasm: add MT ASE yield instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: uasm: add wait instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: uasm: add sync instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: uasm: add jalr instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: uasm: add a label variant of beqPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: inst.h: define microMIPS wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The opcode for the wait instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 08:53:30 -0500