cpuidle: cpuidle-cps: add MIPS CPS cpuidle driver

This patch adds a cpuidle driver for systems based around the MIPS
Coherent Processing System (CPS) architecture. It supports four idle
states:

  - The standard MIPS wait instruction.

  - The non-coherent wait, clock gated & power gated states exposed by
    the recently added pm-cps layer.

The pm-cps layer is used to enter all the deep idle states. Since cores
in the clock or power gated states cannot service interrupts, the
gic_send_ipi_single function is modified to send a power up command for
the appropriate core to the CPC in cases where the target CPU has marked
itself potentially incoherent.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/arch/mips/kernel/smp-gic.c b/arch/mips/kernel/smp-gic.c
index 3bb1f92ab525..3b21a96d1ccb 100644
--- a/arch/mips/kernel/smp-gic.c
+++ b/arch/mips/kernel/smp-gic.c
@@ -15,12 +15,14 @@
 #include <linux/printk.h>
 
 #include <asm/gic.h>
+#include <asm/mips-cpc.h>
 #include <asm/smp-ops.h>
 
 void gic_send_ipi_single(int cpu, unsigned int action)
 {
         unsigned long flags;
         unsigned int intr;
+        unsigned int core = cpu_data[cpu].core;
 
         pr_debug("CPU%d: %s cpu %d action %u status %08x\n",
                  smp_processor_id(), __func__, cpu, action, read_c0_status());
@@ -41,6 +43,15 @@ void gic_send_ipi_single(int cpu, unsigned int action)
         }
 
         gic_send_ipi(intr);
+
+        if (mips_cpc_present() && (core != current_cpu_data.core)) {
+                while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
+                        mips_cpc_lock_other(core);
+                        write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
+                        mips_cpc_unlock_other();
+                }
+        }
+
         local_irq_restore(flags);
 }