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path: root/arch/mips/mm/c-r4k.c
Commit message (Expand)AuthorAge
* [MIPS] Sibyte: resurrect old cache hack.Ralf Baechle2007-11-15
* [MIPS] MT: Fix bug in multithreaded kernels.Ralf Baechle2007-10-29
* [MIPS] Cache: Provide more information on cache policy on bootup.Ralf Baechle2007-10-16
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-11
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-11
* [MIPS] Avoid indexed cacheops.Ralf Baechle2007-10-11
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-11
* [MIPS] Replace use of stext with _stext.Ralf Baechle2007-07-31
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-10
* [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.Ralf Baechle2006-11-29
* [MIPS] Remove redundant r4k_blast_icache() callsAtsushi Nemoto2006-11-29
* [MIPS] Remove __flush_icache_pageAtsushi Nemoto2006-10-01
* [MIPS] c-r4k: Convert init functions from inline to __init.Ralf Baechle2006-09-27
* [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.Atsushi Nemoto2006-09-27
* [MIPS] Retire flush_icache_page from mm use.Ralf Baechle2006-09-27
* [MIPS] c-r4k: Typo fix.Ralf Baechle2006-09-27
* [MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa2006-07-13
* [MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa2006-07-13
* [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa2006-07-13
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-13
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-30
* [MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle2006-06-29
* [MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle2006-06-29
* [MIPS] Fix handling of 0 length I & D caches.Chris Dearman2006-06-29
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-29
* [MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov2006-06-05
* [MIPS] Treat R14000 like R10000.Kumba2006-05-31
* [MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle2006-05-31
* [MIPS] Add missing 34K processor IDsNigel Stephens2006-05-31
* [MIPS] Use __ffs() instead of ffs() for waybit calculation.Atsushi Nemoto2006-04-18
* [MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle2006-04-18
* [MIPS] Fix tx49_blast_icache32_page_indexed.Atsushi Nemoto2006-04-18
* [MIPS] TX49XX has prefetch.Atsushi Nemoto2006-03-21
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-18
* [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle2006-02-28
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-14
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-07
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-10
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-29
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
* Minor code cleanup.Thiemo Seufer2005-10-29
* More .set push/pop.Thiemo Seufer2005-10-29
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-29
* Sparseify MIPS.Ralf Baechle2005-10-29
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